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you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +-------------------------------------------------------------------------------*/ +#include "stdio.h" +#include "lpp_apb_functions.h" + + + +int main() +{ + int d=0; + while(d!=10) + { + scanf("%d",&d); + switch(d) + { + case 0: + printf("cursor OFF \n"); + break; + case 1: + printf("cursor ON \n"); + break; + case 2: + break; + case 3: + apbprintdeviceslist(); + break; + case 10: + return 0; + break; + default: + break; + } + } + return 0; +} diff --git a/LPP_drivers/Doc/ressources/footer.jpg b/LPP_drivers/Doc/ressources/footer.jpg new file mode 100644 index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..31794cf931ac6c280d8c78cffc2dd41e60c9c6cc GIT binary patch literal 8823 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z&40!i8QCpMD#M>Jc;9zv5I6a)x_q>}X%nK@8GF>h0(9|x1j2k6ZBk-pa3!|~cU9I~id9U=>zYk{|n>2YpyG&;wae>FjX#Xqj zyxT!el+^j>%JGUz%eBg7a*I>Q+C91YD(g1lB@?qf5q|-UyaxxJ5|Xh10000LJ%Z3brsR%R9! z7G_o;!OF_Y#?HgR4g~z%+?+gu{6a#4{DOkQVlv{wB2uD)f)a`nQnIr0^76vsN-9cn zDl&5Nav(z(fm+$w*!eg(_~b+cMdU~Z{|_(-axlm-JY!~5Vqg+vWEN!ne}q9C)m91<^DxFbMs>#lXYN2(*t`kinke^{Z8) zRjaQT@*8blwTicD^(AhzwJS_ttqxQnYj5bQgK1YG(z8PYR)LIMwJ?0uUWLtBP3wbBCWeM+ zWi8usSQaR`a@8zHklL(e6C$^Ua?M(~WLj>h)3Q~Wst`#}R7o)uNk@E=K%K0=66000 generate - clkdivider: Clk_divider - generic map(clkkHz*1000,60000000) - Port map( clk ,reset,clk_int); -end generate; - -clknodiv: if clkkHz<66000 generate -nodiv: clk_int <= clk; + clkdivider: Clk_divider + generic map(clkkHz*1000,60000000) + Port map( clk ,reset,clk_int); end generate; -AD_out.CNV <= cnv_int; -AD_out.SCK <= clk_int; +clknodiv: if clkkHz<66000 generate +nodiv: clk_int <= clk; +end generate; + +AD_out.CNV <= cnv_int; +AD_out.SCK <= clk_int; sckgen: process(clk,reset) begin - if reset = '0' then - i <= 0; - cnv_int <= '0'; - smplClk_reg <= '0'; - elsif clk'event and clk = '1' then - if smplClk = '1' and smplClk_reg = '0' then - if i = convTrigger then - smplClk_reg <= '1'; - i <= 0; - cnv_int <= '0'; - else - i <= i+1; - cnv_int <= '1'; - end if; - elsif smplClk = '0' and smplClk_reg = '1' then - smplClk_reg <= '0'; - end if; - end if; + if reset = '0' then + i <= 0; + cnv_int <= '0'; + smplClk_reg <= '0'; + elsif clk'event and clk = '1' then + if smplClk = '1' and smplClk_reg = '0' then + if i = convTrigger then + smplClk_reg <= '1'; + i <= 0; + cnv_int <= '0'; + else + i <= i+1; + cnv_int <= '1'; + end if; + elsif smplClk = '0' and smplClk_reg = '1' then + smplClk_reg <= '0'; + end if; + end if; end process; spidrvr: AD7688_spi_if - generic map(ChanelCount) - Port map(clk_int,reset,cnv_int,DataReady,AD_in,smpout); + generic map(ChanelCount) + Port map(clk_int,reset,cnv_int,DataReady,AD_in,smpout); diff --git a/lib/lpp/lpp_uart/APB_UART.vhd b/lib/lpp/lpp_uart/APB_UART.vhd --- a/lib/lpp/lpp_uart/APB_UART.vhd +++ b/lib/lpp/lpp_uart/APB_UART.vhd @@ -30,7 +30,8 @@ use lpp.lpp_amba.all; use lpp.apb_devices_list.all; use lpp.lpp_uart.all; ---! Driver APB, va faire le lien entre l'IP VHDL de l'UART et le bus Amba +--! This is an APB UART you should use it with a processor as UART and drive it with its register over AMBA bus. +--! \author Martin Morlot martin.morlot@lpp.polytechnique.fr entity APB_UART is generic ( @@ -41,12 +42,12 @@ entity APB_UART is abits : integer := 8; Data_sz : integer := 8); port ( - clk : in std_logic; --! Horloge du composant - rst : in std_logic; --! Reset general du composant - apbi : in apb_slv_in_type; --! Registre de gestion des entrées du bus - apbo : out apb_slv_out_type; --! Registre de gestion des sorties du bus - TXD : out std_logic; --! Transmission série, côté composant - RXD : in std_logic --! Reception série, côté composant + clk : in std_logic; --! System clock + rst : in std_logic; --! System reset + apbi : in apb_slv_in_type; --! APB input signals see grlib.amba package + apbo : out apb_slv_out_type; --! APB input signals see grlib.amba package + TXD : out std_logic; --! UART Transmission pin + RXD : in std_logic --! UART Reception pin ); end APB_UART; diff --git a/lib/lpp/lpp_uart/BaudGen.vhd b/lib/lpp/lpp_uart/BaudGen.vhd --- a/lib/lpp/lpp_uart/BaudGen.vhd +++ b/lib/lpp/lpp_uart/BaudGen.vhd @@ -23,17 +23,19 @@ library IEEE; use IEEE.numeric_std.all; use IEEE.std_logic_1164.all; ---! Generateur de Bauds +--! This is an automatic Baud generator. To synchronize baudrate, it measure the smalest time between two transitions of RXD. So to set baud rate, the device connected to this UART should send at least one data such as 0xA5 (0b10100101) witch gives a lot of transition of one bit length. + +--! \author Alexis Jeandet alexis.jeandet@lpp.polytechnique.fr entity BaudGen is port( - clk : in std_logic; - reset : in std_logic; - Capture : in std_logic; - Bclk : out std_logic; - RXD : in std_logic; - BTrigger : out std_logic_vector(11 downto 0) + clk : in std_logic; --! System clock + reset : in std_logic; --! System reset + Capture : in std_logic; --! baudrate reset so if you want to synchronize again the baudrate generator, usefull if you whant to decrease speed. + Bclk : out std_logic; --! Output baud clock + RXD : in std_logic; --! UART Reception pin used to sample baudrate + BTrigger : out std_logic_vector(11 downto 0) --! Current value of the frequency divider ); end BaudGen; diff --git a/lib/lpp/lpp_uart/Shift_REG.vhd b/lib/lpp/lpp_uart/Shift_REG.vhd --- a/lib/lpp/lpp_uart/Shift_REG.vhd +++ b/lib/lpp/lpp_uart/Shift_REG.vhd @@ -23,20 +23,25 @@ library IEEE; use IEEE.numeric_std.all; use IEEE.std_logic_1164.all; ---! Gestion Reception/Transmission +--! \brief Universal shift register can be used to serialize or deserialize data. +--! +--! \Author Alexis Jeandet alexis.jeandet@lpp.polytechnique.fr +--! \todo move to general purpose library, explain more in detail the code and add some schematic in doc. entity Shift_REG is -generic(Data_sz : integer := 10); +generic( + Data_sz : integer := 10 --! Width of the shift register +); port( - clk : in std_logic; - Sclk : in std_logic; - reset : in std_logic; - SIN : in std_logic; - SOUT : out std_logic; - Serialize : in std_logic; - Serialized : out std_logic; - D : in std_logic_vector(Data_sz-1 downto 0); - Q : out std_logic_vector(Data_sz-1 downto 0) + clk : in std_logic; --! System clock + Sclk : in std_logic; --! Serial clock + reset : in std_logic; --! System reset + SIN : in std_logic; --! Serial data in + SOUT : out std_logic; --! Serial data out + Serialize : in std_logic; --! Launch serialization + Serialized : out std_logic; --! Serialization complete + D : in std_logic_vector(Data_sz-1 downto 0); --! Parallel data to be shifted out + Q : out std_logic_vector(Data_sz-1 downto 0) --! Unserialized data ); end entity; @@ -90,9 +95,6 @@ begin if (Serialized_int = '0' and Serialize_reg ='1') then REG <= SIN & D(Data_sz-1 downto 1); SOUT <= D(0); --- elsif CptBits_flag ='1' then --- REG <= SIN & D(Data_sz-1 downto 1); --- SOUT <= D(0); elsif Serialized_int = '0' then REG <= SIN & REG(Data_sz-1 downto 1); SOUT <= REG(0); diff --git a/lib/lpp/lpp_uart/UART.vhd b/lib/lpp/lpp_uart/UART.vhd --- a/lib/lpp/lpp_uart/UART.vhd +++ b/lib/lpp/lpp_uart/UART.vhd @@ -25,29 +25,29 @@ use IEEE.std_logic_1164.all; library lpp; use lpp.lpp_uart.all; ---! Programme qui va gerer toute la communication entre le PC et le FPGA +--! \brief A general purpose UART with automatic baudrate +--! +--! \author Alexis Jeandet alexis.jeandet@lpp.polytechnique.fr entity UART is -generic(Data_sz : integer := 8); --! Constante de taille pour un mot de donnee +generic(Data_sz : integer := 8); --! Data width port( - clk : in std_logic; --! Horloge a 25Mhz du systeme - reset : in std_logic; --! Reset du systeme - TXD : out std_logic; --! Transmission, cote PC - RXD : in std_logic; --! Reception, cote PC - Capture : in std_logic; --! "Reset" cible pour le generateur de bauds, ici indissocie du reset global - NwDat : out std_logic; --! Flag, Nouvelle donnee presente - ACK : in std_logic; --! Flag, Reponse au flag precedent - Send : in std_logic; --! Flag, Demande d'envoi sur le bus - Sended : out std_logic; --! Flag, Envoi termine - BTrigger : out std_logic_vector(11 downto 0); --! Registre contenant la valeur du diviseur de frequence pour la transmission - RDATA : out std_logic_vector(Data_sz-1 downto 0); --! Mot de donnee en provenance de l'utilisateur - WDATA : in std_logic_vector(Data_sz-1 downto 0) --! Mot de donnee a transmettre a l'utilisateur + clk : in std_logic; --! System clock + reset : in std_logic; --! System reset + TXD : out std_logic; --! UART Transmission pin + RXD : in std_logic; --! UART Reception pin + Capture : in std_logic; --! Automatic baudrate module reset + NwDat : out std_logic; --! New data flag, means that a new data have been received by the UART + ACK : in std_logic; --! Acknowledge flag to clear NwDat flag + Send : in std_logic; --! To send a data you have to set this flag + Sended : out std_logic; --! When this flag is set you can sed a new data + BTrigger : out std_logic_vector(11 downto 0); --! Baudrate generator current value, could be usefull if you whant to know the current value of the baudrate or of the oscillator (it suppose that you know baudrate) + RDATA : out std_logic_vector(Data_sz-1 downto 0); --! Current read word + WDATA : in std_logic_vector(Data_sz-1 downto 0) --! Put here the word you whant to send ); end entity; ---! @details Gestion de la Reception/Transmission donc de la Vectorisation/Serialisation ---! ainsi que la detection et le reglage de le frequence de transmission optimale sur le bus (Generateur de Bauds) - + architecture ar_UART of UART is signal Bclk : std_logic;