HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Files · designs/ICI4-Integ1/ici4.vhd

MiniSpartan6:...

MiniSpartan6: added ftdi chip config to switch between UART and Async FIFO. added few WIP designs with either spwlight core, FIFO_deom IP... Libs: added SpaceWire Light IP (Works really well!) started design of ahb_ftdi_fifo -> same protocol than AHBUART but over FTDI's Async FIFO interface. This might lead to much faster transfers UP to 12MB/s.

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        jeandet
    
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      library ieee;

        jeandet
    
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      use ieee.std_logic_1164.all;

        jeandet
    
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      use IEEE.numeric_std.all;

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      library grlib, techmap;

      use grlib.amba.all;

      use grlib.amba.all;

      use grlib.stdlib.all;

      use techmap.gencomp.all;

      use techmap.allclkgen.all;

      library gaisler;

      use gaisler.memctrl.all;

      use gaisler.leon3.all;

      use gaisler.uart.all;

      use gaisler.misc.all;

      --use gaisler.sim.all;

      library lpp;

      use lpp.lpp_ad_conv.all;

      use lpp.lpp_amba.all;

      use lpp.apb_devices_list.all;

      use lpp.general_purpose.all;

        jeandet
    
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      use lpp.Rocket_PCM_Encoder.all;

        jeandet
    
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      use work.Convertisseur_config.all;

      use work.config.all;

        jeandet
    
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      --==================================================================

      --

      --

      --			FPGA FREQ = 48MHz

      --			ADC Oscillator frequency = 12MHz

      --

      --

      --==================================================================

        jeandet
    
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      entity ici4 is

        generic (

          fabtech       : integer := CFG_FABTECH;

          memtech       : integer := CFG_MEMTECH;

          padtech       : integer := CFG_PADTECH;

          clktech       : integer := CFG_CLKTECH;

      WordSize : integer := 8; WordCnt    :   integer := 144;MinFCount   :   integer := 64

        );

        port (

        jeandet
    
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          reset         : in  std_ulogic;

          clk           : in  std_ulogic;

          sclk          : in  std_logic;

          Gate          : in  std_logic;

          MinF          : in  std_logic;

          MajF          : in  std_logic;

          Data          : out std_logic;

      	 LF_SCK	      : out std_logic;

          LF_CNV	      : out std_logic;

          LF_SDO1	      : in  std_logic;

      	 LF_SDO2	      : in  std_logic;

      	 LF_SDO3	      : in  std_logic;

          DC_ADC_Sclk   : out std_logic;

          DC_ADC_IN     : in  std_logic_vector(1 downto 0);

          DC_ADC_ClkDiv : out std_logic;

          DC_ADC_FSynch : out std_logic;

      	 SET_RESET0    : out std_logic;

      	 SET_RESET1    : out std_logic;

      	 LED           : out std_logic

        jeandet
    
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         );

      end;

      architecture rtl of ici4 is

      signal  clk_buf,reset_buf   :   std_logic;

      Constant FramePlacerCount    :   integer := 2;

        jeandet
    
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        jeandet
    
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      signal  WordCount   :   integer range 0 to WordCnt-1;

      signal  WordClk     :   std_logic;

        jeandet
    
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      signal  AMR1X   :     std_logic_vector(23 downto 0);

      signal  AMR1Y   :     std_logic_vector(23 downto 0);

      signal  AMR1Z   :     std_logic_vector(23 downto 0);

      signal  AMR2X   :     std_logic_vector(23 downto 0);

      signal  AMR2Y   :     std_logic_vector(23 downto 0);

      signal  AMR2Z   :     std_logic_vector(23 downto 0);

      signal  AMR3X   :     std_logic_vector(23 downto 0);

      signal  AMR3Y   :     std_logic_vector(23 downto 0);

      signal  AMR3Z   :     std_logic_vector(23 downto 0);

      signal  AMR4X   :     std_logic_vector(23 downto 0);

      signal  AMR4Y   :     std_logic_vector(23 downto 0);

      signal  AMR4Z   :     std_logic_vector(23 downto 0);

        jeandet
    
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        jeandet
    
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      signal  TEMP1   :     std_logic_vector(23 downto 0);

      signal  TEMP2   :     std_logic_vector(23 downto 0);

      signal  TEMP3   :     std_logic_vector(23 downto 0);

      signal  TEMP4   :     std_logic_vector(23 downto 0);

        jeandet
    
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      signal  LF1     :     std_logic_vector(15 downto 0);

      signal  LF2     :     std_logic_vector(15 downto 0);

      signal  LF3     :     std_logic_vector(15 downto 0);

        jeandet
    
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      signal  data_int :    std_logic;

        jeandet
    
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        jeandet
    
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              r223
            
      signal  CrossDomainSync	:	std_logic;

        jeandet
    
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      begin

        jeandet
    
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      LED         <= not data_int;

        jeandet
    
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              r223
            
      data			<=	data_int;

        jeandet
    
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        jeandet
    
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      CDS0 : entity  work.CrossDomainSyncGen

      Port map( 

      		  reset      => reset,

      		  ClockS     => sclk,

      		  ClockF     => clk,

      		  SyncSignal => CrossDomainSync

      );

        jeandet
    
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        jeandet
    
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              r223
            
      TM : entity work.TM_MODULE 

      generic map(

      	WordSize   =>  WordSize,

      	WordCnt    =>  WordCnt,

      	MinFCount  =>  MinFCount

      )

      port map(

       reset	=>reset,

       clk     =>clk,

       MinF    =>MinF,

       MajF    =>MajF,

       sclk    =>sclk,

       gate		=>gate,

       data		=>data_int,

       WordClk =>WordClk,

        jeandet
    
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        jeandet
    
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       LF1     =>      LF1,

       LF2     =>      LF2,

       LF3     =>      LF3,

       AMR1X   =>      AMR1X,

       AMR1Y   =>      AMR1Y,

       AMR1Z   =>      AMR1Z,

       AMR2X   =>      AMR2X,

       AMR2Y   =>      AMR2Y,

       AMR2Z   =>      AMR2Z,

       AMR3X   =>      AMR3X,

       AMR3Y   =>      AMR3Y,

       AMR3Z   =>      AMR3Z,

       AMR4X   =>      AMR4X,

       AMR4Y   =>      AMR4Y,

       AMR4Z   =>      AMR4Z,

       Temp1   =>      Temp1,

       Temp2   =>      Temp2,

       Temp3   =>      Temp3,

       Temp4   =>      Temp4

      );

      DC_ADC0:entity work.DC_ACQ_TOP

      generic map (

      	WordSize  => WordSize,

      	WordCnt   => WordCnt,

      	MinFCount => MinFCount,

      	EnableSR  => 0,

        jeandet
    
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              r226
            
      	CstDATA   => SEND_CONSTANT_DATA,

      	FakeADC	 => 0

        jeandet
    
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              r223
            
      )

      port map(

        jeandet
    
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        jeandet
    
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              r223
            
       reset	=>  reset,

       clk     =>  clk,

       SyncSig =>  CrossDomainSync,

       minorF  =>  minF,

       majorF  =>  majF,

       sclk    =>  sclk,

       WordClk =>  WordClk,

       DC_ADC_Sclk     =>  DC_ADC_Sclk,

       DC_ADC_IN       =>  DC_ADC_IN,

       DC_ADC_ClkDiv   =>  DC_ADC_ClkDiv,

       DC_ADC_FSynch   =>  DC_ADC_FSynch,

       SET_RESET0      =>  SET_RESET0,

       SET_RESET1      =>  SET_RESET1,

       AMR1X   =>  AMR1X,

       AMR1Y   =>  AMR1Y,

       AMR1Z   =>  AMR1Z,

       AMR2X   =>  AMR2X,

       AMR2Y   =>  AMR2Y,

       AMR2Z   =>  AMR2Z,

       AMR3X   =>  AMR3X,

       AMR3Y   =>  AMR3Y,

       AMR3Z   =>  AMR3Z,

       AMR4X   =>  AMR4X,

       AMR4Y   =>  AMR4Y,

       AMR4Z   =>  AMR4Z,

       Temp1   =>  Temp1,

       Temp2   =>  Temp2,

       Temp3   =>  Temp3,

       Temp4   =>  Temp4

        jeandet
    
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      );

        jeandet
    
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              r223
            
      LF: entity work.LF_ACQ_TOP

      generic map(

      	WordSize  => WordSize,

      	WordCnt   => WordCnt,

      	MinFCount => MinFCount,

        jeandet
    
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              r226
            
      	CstDATA   => SEND_CONSTANT_DATA,

      	IIRFilter => 0

        jeandet
    
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              r223
            
      )

      port map(

        jeandet
    
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        jeandet
    
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              r223
            
       reset	=>  reset,

       clk     =>  clk,

       SyncSig =>  CrossDomainSync,

       minorF  =>  minF,

       majorF  =>  majF,

       sclk    =>  sclk,

       WordClk =>  WordClk,

       LF_SCK	=>  LF_SCK,

       LF_CNV	=>  LF_CNV,

       LF_SDO1	=>  LF_SDO1,

       LF_SDO2	=>  LF_SDO2,

       LF_SDO3	=>  LF_SDO3,

       LF1   	=>  LF1,

       LF2   	=>  LF2,

       LF3   	=>  LF3

      );

        jeandet
    
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      end rtl;

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jeandet Added ICI4 designs....	r129	library ieee;
jeandet Added cross domain synchronisation blocks.	r223	use ieee.std_logic_1164.all;
jeandet ICI rockets designs added	r168	use IEEE.numeric_std.all;
jeandet Added ICI4 designs....	r129	library grlib, techmap;
		use grlib.amba.all;
		use grlib.amba.all;
		use grlib.stdlib.all;
		use techmap.gencomp.all;
		use techmap.allclkgen.all;
		library gaisler;
		use gaisler.memctrl.all;
		use gaisler.leon3.all;
		use gaisler.uart.all;
		use gaisler.misc.all;
		--use gaisler.sim.all;
		library lpp;
		use lpp.lpp_ad_conv.all;
		use lpp.lpp_amba.all;
		use lpp.apb_devices_list.all;
		use lpp.general_purpose.all;
jeandet ICI rockets designs added	r168	use lpp.Rocket_PCM_Encoder.all;
jeandet Added ICI4 designs....	r129

		use work.Convertisseur_config.all;


		use work.config.all;
jeandet Added cross domain synchronisation blocks.	r223	--==================================================================
		--
		--
		-- FPGA FREQ = 48MHz
		-- ADC Oscillator frequency = 12MHz
		--
		--
		--==================================================================
jeandet Added ICI4 designs....	r129
		entity ici4 is
		generic (
		fabtech : integer := CFG_FABTECH;
		memtech : integer := CFG_MEMTECH;
		padtech : integer := CFG_PADTECH;
		clktech : integer := CFG_CLKTECH;
		WordSize : integer := 8; WordCnt : integer := 144;MinFCount : integer := 64
		);
		port (
jeandet Added cross domain synchronisation blocks.	r223	reset : in std_ulogic;
		clk : in std_ulogic;
		sclk : in std_logic;
		Gate : in std_logic;
		MinF : in std_logic;
		MajF : in std_logic;
		Data : out std_logic;
		LF_SCK : out std_logic;
		LF_CNV : out std_logic;
		LF_SDO1 : in std_logic;
		LF_SDO2 : in std_logic;
		LF_SDO3 : in std_logic;
		DC_ADC_Sclk : out std_logic;
		DC_ADC_IN : in std_logic_vector(1 downto 0);
		DC_ADC_ClkDiv : out std_logic;
		DC_ADC_FSynch : out std_logic;
		SET_RESET0 : out std_logic;
		SET_RESET1 : out std_logic;
		LED : out std_logic
jeandet Added ICI4 designs....	r129	);
		end;

		architecture rtl of ici4 is

		signal clk_buf,reset_buf : std_logic;

		Constant FramePlacerCount : integer := 2;

jeandet Added cross domain synchronisation blocks.	r223
jeandet Added ICI4 designs....	r129	signal WordCount : integer range 0 to WordCnt-1;
		signal WordClk : std_logic;


jeandet ICI rockets designs added	r168	signal AMR1X : std_logic_vector(23 downto 0);
		signal AMR1Y : std_logic_vector(23 downto 0);
		signal AMR1Z : std_logic_vector(23 downto 0);

		signal AMR2X : std_logic_vector(23 downto 0);
		signal AMR2Y : std_logic_vector(23 downto 0);
		signal AMR2Z : std_logic_vector(23 downto 0);

		signal AMR3X : std_logic_vector(23 downto 0);
		signal AMR3Y : std_logic_vector(23 downto 0);
		signal AMR3Z : std_logic_vector(23 downto 0);

		signal AMR4X : std_logic_vector(23 downto 0);
		signal AMR4Y : std_logic_vector(23 downto 0);
		signal AMR4Z : std_logic_vector(23 downto 0);

jeandet Added ICI4 designs....	r129
jeandet Added cross domain synchronisation blocks.	r223	signal TEMP1 : std_logic_vector(23 downto 0);
		signal TEMP2 : std_logic_vector(23 downto 0);
		signal TEMP3 : std_logic_vector(23 downto 0);
		signal TEMP4 : std_logic_vector(23 downto 0);
jeandet Added ICI4 designs....	r129
		signal LF1 : std_logic_vector(15 downto 0);
		signal LF2 : std_logic_vector(15 downto 0);
		signal LF3 : std_logic_vector(15 downto 0);

jeandet Added cross domain synchronisation blocks.	r223	signal data_int : std_logic;
jeandet Added ICI4 designs....	r129
jeandet Added cross domain synchronisation blocks.	r223	signal CrossDomainSync : std_logic;
jeandet Added ICI4 designs....	r129
		begin


jeandet ICI rockets designs added	r168	LED <= not data_int;
jeandet Added cross domain synchronisation blocks.	r223	data <= data_int;
jeandet ICI rockets designs added	r168


jeandet Added cross domain synchronisation blocks.	r223	CDS0 : entity work.CrossDomainSyncGen
		Port map(
		reset => reset,
		ClockS => sclk,
		ClockF => clk,
		SyncSignal => CrossDomainSync
		);
jeandet Added ICI4 designs....	r129
jeandet Added cross domain synchronisation blocks.	r223	TM : entity work.TM_MODULE
		generic map(
		WordSize => WordSize,
		WordCnt => WordCnt,
		MinFCount => MinFCount
		)
		port map(

		reset =>reset,
		clk =>clk,
		MinF =>MinF,
		MajF =>MajF,
		sclk =>sclk,
		gate =>gate,
		data =>data_int,
		WordClk =>WordClk,
jeandet Added ICI4 designs....	r129

jeandet Added cross domain synchronisation blocks.	r223	LF1 => LF1,
		LF2 => LF2,
		LF3 => LF3,

		AMR1X => AMR1X,
		AMR1Y => AMR1Y,
		AMR1Z => AMR1Z,

		AMR2X => AMR2X,
		AMR2Y => AMR2Y,
		AMR2Z => AMR2Z,

		AMR3X => AMR3X,
		AMR3Y => AMR3Y,
		AMR3Z => AMR3Z,

		AMR4X => AMR4X,
		AMR4Y => AMR4Y,
		AMR4Z => AMR4Z,

		Temp1 => Temp1,
		Temp2 => Temp2,
		Temp3 => Temp3,
		Temp4 => Temp4
		);

		DC_ADC0:entity work.DC_ACQ_TOP
		generic map (
		WordSize => WordSize,
		WordCnt => WordCnt,
		MinFCount => MinFCount,
		EnableSR => 0,
jeandet Restored previous ALU version as ALU_V0 for IIR filter first version...	r226	CstDATA => SEND_CONSTANT_DATA,
		FakeADC => 0
jeandet Added cross domain synchronisation blocks.	r223	)
		port map(
jeandet ICI rockets designs added	r168
jeandet Added cross domain synchronisation blocks.	r223	reset => reset,
		clk => clk,
		SyncSig => CrossDomainSync,
		minorF => minF,
		majorF => majF,
		sclk => sclk,
		WordClk => WordClk,

		DC_ADC_Sclk => DC_ADC_Sclk,
		DC_ADC_IN => DC_ADC_IN,
		DC_ADC_ClkDiv => DC_ADC_ClkDiv,
		DC_ADC_FSynch => DC_ADC_FSynch,
		SET_RESET0 => SET_RESET0,
		SET_RESET1 => SET_RESET1,

		AMR1X => AMR1X,
		AMR1Y => AMR1Y,
		AMR1Z => AMR1Z,

		AMR2X => AMR2X,
		AMR2Y => AMR2Y,
		AMR2Z => AMR2Z,

		AMR3X => AMR3X,
		AMR3Y => AMR3Y,
		AMR3Z => AMR3Z,

		AMR4X => AMR4X,
		AMR4Y => AMR4Y,
		AMR4Z => AMR4Z,

		Temp1 => Temp1,
		Temp2 => Temp2,
		Temp3 => Temp3,
		Temp4 => Temp4
jeandet Added ICI4 designs....	r129	);


jeandet Added cross domain synchronisation blocks.	r223	LF: entity work.LF_ACQ_TOP
		generic map(
		WordSize => WordSize,
		WordCnt => WordCnt,
		MinFCount => MinFCount,
jeandet Restored previous ALU version as ALU_V0 for IIR filter first version...	r226	CstDATA => SEND_CONSTANT_DATA,
		IIRFilter => 0
jeandet Added cross domain synchronisation blocks.	r223	)
		port map(
jeandet Added ICI4 designs....	r129
jeandet Added cross domain synchronisation blocks.	r223	reset => reset,
		clk => clk,
		SyncSig => CrossDomainSync,
		minorF => minF,
		majorF => majF,
		sclk => sclk,
		WordClk => WordClk,
		LF_SCK => LF_SCK,
		LF_CNV => LF_CNV,
		LF_SDO1 => LF_SDO1,
		LF_SDO2 => LF_SDO2,
		LF_SDO3 => LF_SDO3,
		LF1 => LF1,
		LF2 => LF2,
		LF3 => LF3
		);
jeandet Added ICI4 designs....	r129
		end rtl;