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#ifndef FSW_PARAMS_H_INCLUDED
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#define FSW_PARAMS_H_INCLUDED
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#include "fsw_params_processing.h"
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#include "fsw_params_nb_bytes.h"
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#include "tm_byte_positions.h"
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#include "ccsds_types.h"
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#define GRSPW_DEVICE_NAME "/dev/grspw0"
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#define UART_DEVICE_NAME "/dev/console"
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//*******
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// MACROS
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#ifdef PRINT_MESSAGES_ON_CONSOLE
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#define PRINTF(x) printf(x);
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#define PRINTF1(x,y) printf(x,y);
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#define PRINTF2(x,y,z) printf(x,y,z);
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#else
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#define PRINTF(x) ;
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#define PRINTF1(x,y) ;
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#define PRINTF2(x,y,z) ;
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#endif
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#ifdef BOOT_MESSAGES
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#define BOOT_PRINTF(x) printf(x);
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#define BOOT_PRINTF1(x,y) printf(x,y);
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#define BOOT_PRINTF2(x,y,z) printf(x,y,z);
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#else
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#define BOOT_PRINTF(x) ;
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#define BOOT_PRINTF1(x,y) ;
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#define BOOT_PRINTF2(x,y,z) ;
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#endif
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#ifdef DEBUG_MESSAGES
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#define DEBUG_PRINTF(x) printf(x);
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#define DEBUG_PRINTF1(x,y) printf(x,y);
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#define DEBUG_PRINTF2(x,y,z) printf(x,y,z);
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#else
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#define DEBUG_PRINTF(x) ;
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#define DEBUG_PRINTF1(x,y) ;
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#define DEBUG_PRINTF2(x,y,z) ;
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#endif
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#define CONST_65536 65536 // 2^16
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#define CONST_2048 2048 // 2^11
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#define CONST_512 512 // 2^9
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#define CONST_256 256 // 2^8
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#define CONST_128 128 // 2^7
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#define UINT8_MAX 255
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#define FLOAT_MSBYTE 0
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#define FLOAT_LSBYTE 3
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#define BITS_PER_BYTE 8
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#define INIT_FLOAT 0.
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#define INIT_CHAR 0x00
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#define INIT_INT 0
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#define INT8_ALL_F 0xff
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#define INT16_ALL_F 0xffff
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#define INT32_ALL_F 0xffffffff
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#define INT32_ALL_0 0x00000000
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#define SHIFT_1_BYTE 8
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#define SHIFT_2_BYTES 16
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#define SHIFT_3_BYTES 24
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#define SHIFT_4_BYTES 32
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#define SHIFT_5_BYTES 40
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#define SHIFT_2_BITS 2
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#define SHIFT_3_BITS 3
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#define SHIFT_4_BITS 4
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#define SHIFT_5_BITS 5
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#define SHIFT_6_BITS 6
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#define SHIFT_7_BITS 7
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#define BYTE_0 0
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#define BYTE_1 1
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#define BYTE_2 2
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#define BYTE_3 3
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#define BYTE_4 4
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#define BYTE_5 5
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#define BYTE_6 6
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#define BYTE_7 7
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#define BYTE0_MASK 0xff00
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#define BYTE1_MASK 0x00ff
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enum lfr_transition_type_t{
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TRANSITION_NOT_SPECIFIC,
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TRANSITION_NORM_TO_S1,
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TRANSITION_NORM_TO_S2,
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TRANSITION_S1_TO_NORM,
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TRANSITION_S2_TO_NORM,
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TRANSITION_S1_TO_S2,
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TRANSITION_S2_TO_S1
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};
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typedef struct ring_node
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{
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struct ring_node *previous;
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struct ring_node *next;
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unsigned int sid;
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unsigned int coarseTime;
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unsigned int fineTime;
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int buffer_address;
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unsigned int status;
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} ring_node;
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//************************
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// flight software version
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// this parameters is handled by the Qt project options
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#define NB_PACKETS_PER_GROUP_OF_CWF 8 // 8 packets containing 336 blk
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#define NB_PACKETS_PER_GROUP_OF_CWF_LIGHT 4 // 4 packets containing 672 blk
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#define NB_SAMPLES_PER_SNAPSHOT 2688 // 336 * 8 = 672 * 4 = 2688
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#define TIME_OFFSET 2
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#define TIME_OFFSET_IN_BYTES 8
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//#define WAVEFORM_EXTENDED_HEADER_OFFSET 22
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#define NB_BYTES_SWF_BLK (2 * 6)
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#define NB_WORDS_SWF_BLK 3
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#define NB_BYTES_CWF3_LIGHT_BLK 6
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//#define WFRM_INDEX_OF_LAST_PACKET 6 // waveforms are transmitted in groups of 2048 blocks, 6 packets of 340 and 1 of 8
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#define NB_RING_NODES_F0 3 // AT LEAST 3
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#define NB_RING_NODES_F1 5 // AT LEAST 3
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#define NB_RING_NODES_F2 5 // AT LEAST 3
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#define NB_RING_NODES_F3 3 // AT LEAST 3
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//**********
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// LFR MODES
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#define LFR_MODE_STANDBY 0
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#define LFR_MODE_NORMAL 1
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#define LFR_MODE_BURST 2
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#define LFR_MODE_SBM1 3
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#define LFR_MODE_SBM2 4
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#define TDS_MODE_LFM 5
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#define TDS_MODE_STANDBY 0
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#define TDS_MODE_NORMAL 1
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#define TDS_MODE_BURST 2
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#define TDS_MODE_SBM1 3
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#define TDS_MODE_SBM2 4
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#define THR_MODE_STANDBY 0
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#define THR_MODE_NORMAL 1
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#define THR_MODE_BURST 2
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#define RTEMS_EVENT_MODE_STANDBY RTEMS_EVENT_0
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#define RTEMS_EVENT_MODE_NORMAL RTEMS_EVENT_1
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#define RTEMS_EVENT_MODE_BURST RTEMS_EVENT_2
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#define RTEMS_EVENT_MODE_SBM1 RTEMS_EVENT_3
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#define RTEMS_EVENT_MODE_SBM2 RTEMS_EVENT_4
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#define RTEMS_EVENT_MODE_NORM_S1_S2 RTEMS_EVENT_5
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#define RTEMS_EVENT_NORM_BP1_F0 RTEMS_EVENT_6
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#define RTEMS_EVENT_NORM_BP2_F0 RTEMS_EVENT_7
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#define RTEMS_EVENT_NORM_ASM_F0 RTEMS_EVENT_8 // ASM only in NORM mode
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#define RTEMS_EVENT_NORM_BP1_F1 RTEMS_EVENT_9
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#define RTEMS_EVENT_NORM_BP2_F1 RTEMS_EVENT_10
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#define RTEMS_EVENT_NORM_ASM_F1 RTEMS_EVENT_11 // ASM only in NORM mode
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#define RTEMS_EVENT_NORM_BP1_F2 RTEMS_EVENT_12
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#define RTEMS_EVENT_NORM_BP2_F2 RTEMS_EVENT_13
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#define RTEMS_EVENT_NORM_ASM_F2 RTEMS_EVENT_14 // ASM only in NORM mode
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#define RTEMS_EVENT_SBM_BP1_F0 RTEMS_EVENT_15
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#define RTEMS_EVENT_SBM_BP2_F0 RTEMS_EVENT_16
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#define RTEMS_EVENT_SBM_BP1_F1 RTEMS_EVENT_17
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#define RTEMS_EVENT_SBM_BP2_F1 RTEMS_EVENT_18
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#define RTEMS_EVENT_BURST_BP1_F0 RTEMS_EVENT_19
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#define RTEMS_EVENT_BURST_BP2_F0 RTEMS_EVENT_20
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#define RTEMS_EVENT_BURST_BP1_F1 RTEMS_EVENT_21
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#define RTEMS_EVENT_BURST_BP2_F1 RTEMS_EVENT_22
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#define RTEMS_EVENT_SWF_RESYNCH RTEMS_EVENT_23
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//********************************************
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//********************************************
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// LFR PARAMETERS: DEFAULT, MIN AND MAX VALUES
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#define DEFAULT_LAST_VALID_TRANSITION_DATE 0xffffffff
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// COMMON
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#define DEFAULT_SY_LFR_COMMON0 0x00
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#define DEFAULT_SY_LFR_COMMON1 0x20 // default value bw sp0 sp1 r0 r1 r2 = 1 0 0 0 0 0
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// NORM
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#define DFLT_SY_LFR_N_SWF_L 2048 // nb sample
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#define DFLT_SY_LFR_N_SWF_P 300 // sec
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#define MIN_SY_LFR_N_SWF_P 22 // sec
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#define DFLT_SY_LFR_N_ASM_P 3600 // sec
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#define DFLT_SY_LFR_N_BP_P0 4 // sec
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#define DFLT_SY_LFR_N_BP_P1 20 // sec
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#define DFLT_SY_LFR_N_CWF_LONG_F3 0 // 0 => production of light continuous waveforms at f3
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#define MIN_DELTA_SNAPSHOT 16 // sec
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// BURST
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#define DEFAULT_SY_LFR_B_BP_P0 1 // sec
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#define DEFAULT_SY_LFR_B_BP_P1 5 // sec
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// SBM1
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#define S1_BP_P0_SCALE 0.25
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#define DEFAULT_SY_LFR_S1_BP_P0 1 // 0.25 sec
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#define DEFAULT_SY_LFR_S1_BP_P1 1 // sec
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// SBM2
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#define DEFAULT_SY_LFR_S2_BP_P0 1 // sec
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#define DEFAULT_SY_LFR_S2_BP_P1 5 // sec
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// ADDITIONAL PARAMETERS
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#define TIME_BETWEEN_TWO_SWF_PACKETS 30 // nb x 10 ms => 300 ms
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#define TIME_BETWEEN_TWO_CWF3_PACKETS 1000 // nb x 10 ms => 10 s
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// STATUS WORD
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#define DEFAULT_STATUS_WORD_BYTE0 0x0d // [0000] [1] [101] mode 4 bits / SPW enabled 1 bit / state is run 3 bits
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#define DEFAULT_STATUS_WORD_BYTE1 0x00
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// TC_LFR_LOAD_FILTER_PAR
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#define MIN_PAS_FILTER_MODULUS 4
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#define MAX_PAS_FILTER_MODULUS 8
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#define MIN_PAS_FILTER_TBAD 0.0
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#define MAX_PAS_FILTER_TBAD 4.0
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#define MIN_PAS_FILTER_OFFSET 0
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#define MAX_PAS_FILTER_OFFSET 7
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#define MIN_PAS_FILTER_SHIFT 0.0
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#define MAX_PAS_FILTER_SHIFT 1.0
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#define MIN_SY_LFR_SC_RW_DELTA_F 0
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#define MIN_SY_LFR_RW_K 0
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#define MIN_SY_LFR_RW_F 0
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//
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#define SY_LFR_DPU_CONNECT_TIMEOUT 100 // 100 * 10 ms = 1 s
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#define SY_LFR_DPU_CONNECT_ATTEMPT 3
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//****************************
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//*****************************
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// APB REGISTERS BASE ADDRESSES
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#define REGS_ADDR_APBUART 0x80000100
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#define REGS_ADDR_GPTIMER 0x80000300
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#define REGS_ADDR_GRSPW 0x80000500
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#define APB_OFFSET_GRSPW_STATUS_REGISTER 0x04
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#define APB_OFFSET_GRSPW_TIME_REGISTER 0x14
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#define REGS_ADDR_TIME_MANAGEMENT 0x80000600
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#define REGS_ADDR_GRGPIO 0x80000b00
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#define REGS_ADDR_SPECTRAL_MATRIX 0x80000f00
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#define REGS_ADDR_WAVEFORM_PICKER 0x80000f54 // PDB >= 0.1.28
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#define APB_OFFSET_VHDL_REV 0xb0
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#define REGS_ADDR_VHDL_VERSION 0x80000ff0
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#define APBUART_CTRL_REG_MASK_DB 0xfffff7ff
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#define APBUART_CTRL_REG_MASK_TE 0x00000002
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// scaler value = system_clock_frequency / ( baud_rate * 8 ) - 1
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#define APBUART_SCALER_RELOAD_VALUE 0x00000050 // 25 MHz => about 38400
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//**********
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// IRQ LINES
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#define IRQ_GPTIMER_WATCHDOG 9
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#define IRQ_SPARC_GPTIMER_WATCHDOG 0x19 // see sparcv8.pdf p.76 for interrupt levels
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#define IRQ_WAVEFORM_PICKER 14
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#define IRQ_SPARC_WAVEFORM_PICKER 0x1e // see sparcv8.pdf p.76 for interrupt levels
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#define IRQ_SPECTRAL_MATRIX 6
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#define IRQ_SPARC_SPECTRAL_MATRIX 0x16 // see sparcv8.pdf p.76 for interrupt levels
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//*****
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// TIME
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#define CLKDIV_WATCHDOG (10000000 - 1) // 10.0s => 10 000 000
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#define TIMER_WATCHDOG 1
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#define WATCHDOG_PERIOD 100 // 1s
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#define HK_PERIOD 100 // 100 * 10ms => 1s
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#define AVGV_PERIOD 6 // 6 * 10ms => 60ms (1 / 16 = 62.5ms)
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#define SY_LFR_TIME_SYN_TIMEOUT_in_ticks 200 // 200 * 10 ms = 2 s
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#define HK_SYNC_WAIT 10 // 10 * 10 ms = 100 ms
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#define SPW_LINK_WAIT 10 // 10 * 10 ms = 100 ms
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#define TIMECODE_TIMER_TIMEOUT 120 // 120 * 10 ms = 1.2 s
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#define TIMECODE_TIMER_TIMEOUT_INIT 200 // 200 * 10 ms = 2.0 s
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#define TIMECODE_MASK 0x3f // 0011 1111
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//**********
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// LPP CODES
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#define LFR_SUCCESSFUL 0
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#define LFR_DEFAULT 1
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#define LFR_EXE_ERROR 2
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#define LFR_DEFAULT_ALT -1
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//******
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// RTEMS
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#define STACK_SIZE_MULT 2
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#define TASKID_AVGV 0
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#define TASKID_RECV 1
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#define TASKID_ACTN 2
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#define TASKID_SPIQ 3
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#define TASKID_LOAD 4
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#define TASKID_AVF0 5
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#define TASKID_SWBD 6
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#define TASKID_WFRM 7
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#define TASKID_DUMB 8
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#define TASKID_HOUS 9
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#define TASKID_PRC0 10
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#define TASKID_CWF3 11
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#define TASKID_CWF2 12
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#define TASKID_CWF1 13
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#define TASKID_SEND 14
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#define TASKID_LINK 15
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#define TASKID_AVF1 16
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#define TASKID_PRC1 17
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#define TASKID_AVF2 18
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#define TASKID_PRC2 19
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#define TASK_PRIORITY_SPIQ 5
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#define TASK_PRIORITY_LINK 20
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#define TASK_PRIORITY_AVGV 25
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#define TASK_PRIORITY_HOUS 30
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#define TASK_PRIORITY_CWF1 35 // CWF1 and CWF2 are never running together
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#define TASK_PRIORITY_CWF2 35 //
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#define TASK_PRIORITY_SWBD 37 // SWBD has a lower priority than WFRM, this is to extract the snapshot before sending it
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#define TASK_PRIORITY_WFRM 40
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#define TASK_PRIORITY_CWF3 40 // there is a printf in this function, be careful with its priority wrt CWF1
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#define TASK_PRIORITY_SEND 45
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#define TASK_PRIORITY_RECV 50
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#define TASK_PRIORITY_ACTN 50
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#define TASK_PRIORITY_AVF0 60
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#define TASK_PRIORITY_AVF1 70
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#define TASK_PRIORITY_PRC0 100
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#define TASK_PRIORITY_PRC1 100
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#define TASK_PRIORITY_AVF2 110
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#define TASK_PRIORITY_PRC2 110
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#define TASK_PRIORITY_LOAD 190
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#define TASK_PRIORITY_DUMB 200
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#define MSG_QUEUE_COUNT_RECV 10
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#define MSG_QUEUE_COUNT_SEND 50
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#define MSG_QUEUE_COUNT_PRC0 10
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#define MSG_QUEUE_COUNT_PRC1 10
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#define MSG_QUEUE_COUNT_PRC2 5
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#define MSG_QUEUE_SIZE_SEND 812 // 808 + 4 => TM_LFR_SCIENCE_BURST_BP2_F1
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#define ACTION_MSG_SPW_IOCTL_SEND_SIZE 24 // hlen *hdr dlen *data sent options
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#define MSG_QUEUE_SIZE_PRC0 36 // two pointers, one rtems_event + 6 integers
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#define MSG_QUEUE_SIZE_PRC1 36 // two pointers, one rtems_event + 6 integers
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#define MSG_QUEUE_SIZE_PRC2 36 // two pointers, one rtems_event + 6 integers
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#define QUEUE_RECV 0
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#define QUEUE_SEND 1
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#define QUEUE_PRC0 2
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#define QUEUE_PRC1 3
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#define QUEUE_PRC2 4
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#define CPU_USAGE_REPORT_PERIOD 6 // * 10 s = period
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struct param_local_str{
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unsigned int local_sbm1_nb_cwf_sent;
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unsigned int local_sbm1_nb_cwf_max;
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unsigned int local_sbm2_nb_cwf_sent;
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unsigned int local_sbm2_nb_cwf_max;
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};
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//************
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// FBINS MASKS
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#define BYTES_PER_FBINS_MASK 16
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typedef struct {
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unsigned char merged_fbins_mask_f0[BYTES_PER_FBINS_MASK];
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unsigned char merged_fbins_mask_f1[BYTES_PER_FBINS_MASK];
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unsigned char merged_fbins_mask_f2[BYTES_PER_FBINS_MASK];
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} fbins_masks_t;
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#define DEFAULT_SY_LFR_PAS_FILTER_ENABLED 0
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#define DEFAULT_SY_LFR_PAS_FILTER_MODULUS 4
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#define DEFAULT_SY_LFR_PAS_FILTER_TBAD 1.0
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#define DEFAULT_SY_LFR_PAS_FILTER_OFFSET 0
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#define DEFAULT_SY_LFR_PAS_FILTER_SHIFT 0.5
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#define DEFAULT_SY_LFR_SC_RW_DELTA_F 0.045
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#define DEFAULT_SY_LFR_RW_K1 1.
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#define DEFAULT_SY_LFR_RW_K2 8.
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#define DEFAULT_SY_LFR_RW_K3 24.
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#define DEFAULT_SY_LFR_RW_K4 48.
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typedef struct{
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unsigned char spare_sy_lfr_pas_filter_enabled;
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unsigned char sy_lfr_pas_filter_modulus;
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float sy_lfr_pas_filter_tbad;
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unsigned char sy_lfr_pas_filter_offset;
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float sy_lfr_pas_filter_shift;
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float sy_lfr_sc_rw_delta_f;
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// rw1_k
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float sy_lfr_rw1_k1;
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float sy_lfr_rw1_k2;
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float sy_lfr_rw1_k3;
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float sy_lfr_rw1_k4;
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// rw2_k
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float sy_lfr_rw2_k1;
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float sy_lfr_rw2_k2;
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float sy_lfr_rw2_k3;
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float sy_lfr_rw2_k4;
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// rw3_k
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float sy_lfr_rw3_k1;
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float sy_lfr_rw3_k2;
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float sy_lfr_rw3_k3;
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float sy_lfr_rw3_k4;
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// rw4_k
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float sy_lfr_rw4_k1;
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float sy_lfr_rw4_k2;
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float sy_lfr_rw4_k3;
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float sy_lfr_rw4_k4;
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} filterPar_t;
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typedef struct{
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// rw1_f
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float cp_rpw_sc_rw1_f1;
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float cp_rpw_sc_rw1_f2;
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float cp_rpw_sc_rw1_f3;
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float cp_rpw_sc_rw1_f4;
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// rw2_f
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float cp_rpw_sc_rw2_f1;
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float cp_rpw_sc_rw2_f2;
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float cp_rpw_sc_rw2_f3;
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float cp_rpw_sc_rw2_f4;
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// rw3_f
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float cp_rpw_sc_rw3_f1;
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float cp_rpw_sc_rw3_f2;
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float cp_rpw_sc_rw3_f3;
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float cp_rpw_sc_rw3_f4;
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// rw4_f
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float cp_rpw_sc_rw4_f1;
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float cp_rpw_sc_rw4_f2;
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float cp_rpw_sc_rw4_f3;
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float cp_rpw_sc_rw4_f4;
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} rw_f_t;
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#define NB_ACQUISITION_DURATION 3
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#define ACQUISITION_DURATION_F0 683 // 256 / 24576 * 65536
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#define ACQUISITION_DURATION_F1 4096 // 256 / 4096 * 65536
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#define ACQUISITION_DURATION_F2 65536 // 256 / 256 * 65536
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#endif // FSW_PARAMS_H_INCLUDED
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