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1 1 #ifndef FSW_PARAMS_H_INCLUDED
2 2 #define FSW_PARAMS_H_INCLUDED
3 3
4 4 #include "fsw_params_processing.h"
5 5 #include "fsw_params_nb_bytes.h"
6 6 #include "tm_byte_positions.h"
7 7 #include "ccsds_types.h"
8 8
9 9 #define GRSPW_DEVICE_NAME "/dev/grspw0"
10 10 #define UART_DEVICE_NAME "/dev/console"
11 11
12 12 typedef struct ring_node
13 13 {
14 14 struct ring_node *previous;
15 15 struct ring_node *next;
16 16 unsigned int sid;
17 17 unsigned int coarseTime;
18 18 unsigned int fineTime;
19 19 int buffer_address;
20 20 unsigned int status;
21 21 } ring_node;
22 22
23 23 //************************
24 24 // flight software version
25 25 // this parameters is handled by the Qt project options
26 26
27 27 #define NB_PACKETS_PER_GROUP_OF_CWF 8 // 8 packets containing 336 blk
28 28 #define NB_PACKETS_PER_GROUP_OF_CWF_LIGHT 4 // 4 packets containing 672 blk
29 29 #define NB_SAMPLES_PER_SNAPSHOT 2688 // 336 * 8 = 672 * 4 = 2688
30 30 #define TIME_OFFSET 2
31 31 #define TIME_OFFSET_IN_BYTES 8
32 32 //#define WAVEFORM_EXTENDED_HEADER_OFFSET 22
33 33 #define NB_BYTES_SWF_BLK (2 * 6)
34 34 #define NB_WORDS_SWF_BLK 3
35 35 #define NB_BYTES_CWF3_LIGHT_BLK 6
36 36 //#define WFRM_INDEX_OF_LAST_PACKET 6 // waveforms are transmitted in groups of 2048 blocks, 6 packets of 340 and 1 of 8
37 37 #define NB_RING_NODES_F0 3 // AT LEAST 3
38 38 #define NB_RING_NODES_F1 5 // AT LEAST 3
39 39 #define NB_RING_NODES_F2 5 // AT LEAST 3
40 40 #define NB_RING_NODES_F3 3 // AT LEAST 3
41 41
42 42 //**********
43 43 // LFR MODES
44 44 #define LFR_MODE_STANDBY 0
45 45 #define LFR_MODE_NORMAL 1
46 46 #define LFR_MODE_BURST 2
47 47 #define LFR_MODE_SBM1 3
48 48 #define LFR_MODE_SBM2 4
49 49
50 50 #define TDS_MODE_LFM 5
51 51 #define TDS_MODE_STANDBY 0
52 52 #define TDS_MODE_NORMAL 1
53 53 #define TDS_MODE_BURST 2
54 54 #define TDS_MODE_SBM1 3
55 55 #define TDS_MODE_SBM2 4
56 56
57 57 #define THR_MODE_STANDBY 0
58 58 #define THR_MODE_NORMAL 1
59 59 #define THR_MODE_BURST 2
60 60
61 61 #define RTEMS_EVENT_MODE_STANDBY RTEMS_EVENT_0
62 62 #define RTEMS_EVENT_MODE_NORMAL RTEMS_EVENT_1
63 63 #define RTEMS_EVENT_MODE_BURST RTEMS_EVENT_2
64 64 #define RTEMS_EVENT_MODE_SBM1 RTEMS_EVENT_3
65 65 #define RTEMS_EVENT_MODE_SBM2 RTEMS_EVENT_4
66 66 #define RTEMS_EVENT_MODE_NORM_S1_S2 RTEMS_EVENT_5
67 67 #define RTEMS_EVENT_NORM_BP1_F0 RTEMS_EVENT_6
68 68 #define RTEMS_EVENT_NORM_BP2_F0 RTEMS_EVENT_7
69 69 #define RTEMS_EVENT_NORM_ASM_F0 RTEMS_EVENT_8 // ASM only in NORM mode
70 70 #define RTEMS_EVENT_NORM_BP1_F1 RTEMS_EVENT_9
71 71 #define RTEMS_EVENT_NORM_BP2_F1 RTEMS_EVENT_10
72 72 #define RTEMS_EVENT_NORM_ASM_F1 RTEMS_EVENT_11 // ASM only in NORM mode
73 73 #define RTEMS_EVENT_NORM_BP1_F2 RTEMS_EVENT_12
74 74 #define RTEMS_EVENT_NORM_BP2_F2 RTEMS_EVENT_13
75 75 #define RTEMS_EVENT_NORM_ASM_F2 RTEMS_EVENT_14 // ASM only in NORM mode
76 76 #define RTEMS_EVENT_SBM_BP1_F0 RTEMS_EVENT_15
77 77 #define RTEMS_EVENT_SBM_BP2_F0 RTEMS_EVENT_16
78 78 #define RTEMS_EVENT_SBM_BP1_F1 RTEMS_EVENT_17
79 79 #define RTEMS_EVENT_SBM_BP2_F1 RTEMS_EVENT_18
80 80 #define RTEMS_EVENT_BURST_BP1_F0 RTEMS_EVENT_19
81 81 #define RTEMS_EVENT_BURST_BP2_F0 RTEMS_EVENT_20
82 82 #define RTEMS_EVENT_BURST_BP1_F1 RTEMS_EVENT_21
83 83 #define RTEMS_EVENT_BURST_BP2_F1 RTEMS_EVENT_22
84 84
85 85 //****************************
86 86 // LFR DEFAULT MODE PARAMETERS
87 #define DEFAULT_LAST_VALID_TRANSITION_DATE 0x00
87 88 // COMMON
88 89 #define DEFAULT_SY_LFR_COMMON0 0x00
89 90 #define DEFAULT_SY_LFR_COMMON1 0x20 // default value bw sp0 sp1 r0 r1 r2 = 1 0 0 0 0 0
90 91 // NORM
91 92 #define DFLT_SY_LFR_N_SWF_L 2048 // nb sample
92 93 #define DFLT_SY_LFR_N_SWF_P 300 // sec
93 94 #define DFLT_SY_LFR_N_ASM_P 3600 // sec
94 95 #define DFLT_SY_LFR_N_BP_P0 4 // sec
95 96 #define DFLT_SY_LFR_N_BP_P1 20 // sec
96 97 #define DFLT_SY_LFR_N_CWF_LONG_F3 0 // 0 => production of light continuous waveforms at f3
97 98 #define MIN_DELTA_SNAPSHOT 16 // sec
98 99 // BURST
99 100 #define DEFAULT_SY_LFR_B_BP_P0 1 // sec
100 101 #define DEFAULT_SY_LFR_B_BP_P1 5 // sec
101 102 // SBM1
102 103 #define DEFAULT_SY_LFR_S1_BP_P0 1 // sec
103 104 #define DEFAULT_SY_LFR_S1_BP_P1 1 // sec
104 105 // SBM2
105 106 #define DEFAULT_SY_LFR_S2_BP_P0 1 // sec
106 107 #define DEFAULT_SY_LFR_S2_BP_P1 5 // sec
107 108 // ADDITIONAL PARAMETERS
108 109 #define TIME_BETWEEN_TWO_SWF_PACKETS 30 // nb x 10 ms => 300 ms
109 110 #define TIME_BETWEEN_TWO_CWF3_PACKETS 1000 // nb x 10 ms => 10 s
110 111 // STATUS WORD
111 112 #define DEFAULT_STATUS_WORD_BYTE0 0x0d // [0000] [1] [101] mode 4 bits / SPW enabled 1 bit / state is run 3 bits
112 113 #define DEFAULT_STATUS_WORD_BYTE1 0x00
113 114 //
114 115 #define SY_LFR_DPU_CONNECT_TIMEOUT 100 // 100 * 10 ms = 1 s
115 116 #define SY_LFR_DPU_CONNECT_ATTEMPT 3
116 117 //****************************
117 118
118 119 //*****************************
119 120 // APB REGISTERS BASE ADDRESSES
120 121 #define REGS_ADDR_APBUART 0x80000100
121 122 #define REGS_ADDR_GPTIMER 0x80000300
122 123 #define REGS_ADDR_GRSPW 0x80000500
123 124 #define APB_OFFSET_GRSPW_TIME_REGISTER 0x14
124 125 #define REGS_ADDR_TIME_MANAGEMENT 0x80000600
125 126 #define REGS_ADDR_GRGPIO 0x80000b00
126 127
127 128 #define REGS_ADDR_SPECTRAL_MATRIX 0x80000f00
128 129 //#define REGS_ADDR_WAVEFORM_PICKER 0x80000f50
129 130 #define REGS_ADDR_WAVEFORM_PICKER 0x80000f54 // PDB >= 0.1.28
130 131 #define REGS_ADDR_VHDL_VERSION 0x80000ff0
131 132
132 133 #define APBUART_CTRL_REG_MASK_DB 0xfffff7ff
133 134 #define APBUART_CTRL_REG_MASK_TE 0x00000002
134 135 // scaler value = system_clock_frequency / ( baud_rate * 8 ) - 1
135 136 #define APBUART_SCALER_RELOAD_VALUE 0x00000050 // 25 MHz => about 38400
136 137
137 138 //**********
138 139 // IRQ LINES
139 140 #define IRQ_GPTIMER_WATCHDOG 9
140 141 #define IRQ_SPARC_GPTIMER_WATCHDOG 0x19 // see sparcv8.pdf p.76 for interrupt levels
141 142 #define IRQ_WAVEFORM_PICKER 14
142 143 #define IRQ_SPARC_WAVEFORM_PICKER 0x1e // see sparcv8.pdf p.76 for interrupt levels
143 144 #define IRQ_SPECTRAL_MATRIX 6
144 145 #define IRQ_SPARC_SPECTRAL_MATRIX 0x16 // see sparcv8.pdf p.76 for interrupt levels
145 146
146 147 //*****
147 148 // TIME
148 149 #define CLKDIV_WATCHDOG (1100000 - 1) // 1.1s => 1100000
149 150 #define TIMER_WATCHDOG 1
150 151 #define WATCHDOG_PERIOD 100 // 1s
151 152 #define HK_PERIOD 100 // 100 * 10ms => 1s
152 153 #define SY_LFR_TIME_SYN_TIMEOUT_in_ms 2000
153 154 #define SY_LFR_TIME_SYN_TIMEOUT_in_ticks 200 // 200 * 10 ms = 2 s
154 155
155 156 //**********
156 157 // LPP CODES
157 158 #define LFR_SUCCESSFUL 0
158 159 #define LFR_DEFAULT 1
159 160 #define LFR_EXE_ERROR 2
160 161
161 162 //******
162 163 // RTEMS
163 164 #define TASKID_RECV 1
164 165 #define TASKID_ACTN 2
165 166 #define TASKID_SPIQ 3
166 167 #define TASKID_LOAD 4
167 168 #define TASKID_AVF0 5
168 169 #define TASKID_SWBD 6
169 170 #define TASKID_WFRM 7
170 171 #define TASKID_DUMB 8
171 172 #define TASKID_HOUS 9
172 173 #define TASKID_PRC0 10
173 174 #define TASKID_CWF3 11
174 175 #define TASKID_CWF2 12
175 176 #define TASKID_CWF1 13
176 177 #define TASKID_SEND 14
177 178 #define TASKID_WTDG 15
178 179 #define TASKID_AVF1 16
179 180 #define TASKID_PRC1 17
180 181 #define TASKID_AVF2 18
181 182 #define TASKID_PRC2 19
182 183
183 184 #define TASK_PRIORITY_SPIQ 5
184 185 #define TASK_PRIORITY_WTDG 20
185 186 #define TASK_PRIORITY_HOUS 30
186 187 #define TASK_PRIORITY_CWF1 35 // CWF1 and CWF2 are never running together
187 188 #define TASK_PRIORITY_CWF2 35 //
188 189 #define TASK_PRIORITY_SWBD 37 // SWBD has a lower priority than WFRM, this is to extract the snapshot before sending it
189 190 #define TASK_PRIORITY_WFRM 40
190 191 #define TASK_PRIORITY_CWF3 40 // there is a printf in this function, be careful with its priority wrt CWF1
191 192 #define TASK_PRIORITY_SEND 45
192 193 #define TASK_PRIORITY_RECV 50
193 194 #define TASK_PRIORITY_ACTN 50
194 195 #define TASK_PRIORITY_AVF0 60
195 196 #define TASK_PRIORITY_AVF1 70
196 197 #define TASK_PRIORITY_PRC0 100
197 198 #define TASK_PRIORITY_PRC1 100
198 199 #define TASK_PRIORITY_AVF2 110
199 200 #define TASK_PRIORITY_PRC2 110
200 201 #define TASK_PRIORITY_DUMB 200
201 202 #define TASK_PRIORITY_LOAD 220
202 203
203 204 #define MSG_QUEUE_COUNT_RECV 10
204 205 #define MSG_QUEUE_COUNT_SEND 50
205 206 #define MSG_QUEUE_COUNT_PRC0 10
206 207 #define MSG_QUEUE_COUNT_PRC1 10
207 208 #define MSG_QUEUE_COUNT_PRC2 5
208 209 #define MSG_QUEUE_SIZE_SEND 812 // 808 + 4 => TM_LFR_SCIENCE_BURST_BP2_F1
209 210 #define ACTION_MSG_SPW_IOCTL_SEND_SIZE 24 // hlen *hdr dlen *data sent options
210 211 #define MSG_QUEUE_SIZE_PRC0 28 // two pointers, one rtems_event + 4 integers
211 212 #define MSG_QUEUE_SIZE_PRC1 28 // two pointers, one rtems_event + 4 integers
212 213 #define MSG_QUEUE_SIZE_PRC2 28 // two pointers, one rtems_event + 4 integers
213 214
214 215 #define QUEUE_RECV 0
215 216 #define QUEUE_SEND 1
216 217 #define QUEUE_PRC0 2
217 218 #define QUEUE_PRC1 3
218 219 #define QUEUE_PRC2 4
219 220
220 221 //*******
221 222 // MACROS
222 223 #ifdef PRINT_MESSAGES_ON_CONSOLE
223 224 #define PRINTF(x) printf(x);
224 225 #define PRINTF1(x,y) printf(x,y);
225 226 #define PRINTF2(x,y,z) printf(x,y,z);
226 227 #else
227 228 #define PRINTF(x) ;
228 229 #define PRINTF1(x,y) ;
229 230 #define PRINTF2(x,y,z) ;
230 231 #endif
231 232
232 233 #ifdef BOOT_MESSAGES
233 234 #define BOOT_PRINTF(x) printf(x);
234 235 #define BOOT_PRINTF1(x,y) printf(x,y);
235 236 #define BOOT_PRINTF2(x,y,z) printf(x,y,z);
236 237 #else
237 238 #define BOOT_PRINTF(x) ;
238 239 #define BOOT_PRINTF1(x,y) ;
239 240 #define BOOT_PRINTF2(x,y,z) ;
240 241 #endif
241 242
242 243 #ifdef DEBUG_MESSAGES
243 244 #define DEBUG_PRINTF(x) printf(x);
244 245 #define DEBUG_PRINTF1(x,y) printf(x,y);
245 246 #define DEBUG_PRINTF2(x,y,z) printf(x,y,z);
246 247 #else
247 248 #define DEBUG_PRINTF(x) ;
248 249 #define DEBUG_PRINTF1(x,y) ;
249 250 #define DEBUG_PRINTF2(x,y,z) ;
250 251 #endif
251 252
252 253 #define CPU_USAGE_REPORT_PERIOD 6 // * 10 s = period
253 254
254 255 struct param_local_str{
255 256 unsigned int local_sbm1_nb_cwf_sent;
256 257 unsigned int local_sbm1_nb_cwf_max;
257 258 unsigned int local_sbm2_nb_cwf_sent;
258 259 unsigned int local_sbm2_nb_cwf_max;
259 260 };
260 261
261 262 #endif // FSW_PARAMS_H_INCLUDED
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