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1 | 1 | #ifndef FSW_PARAMS_H_INCLUDED |
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2 | 2 | #define FSW_PARAMS_H_INCLUDED |
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3 | 3 | |
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4 | 4 | #include "fsw_params_processing.h" |
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5 | 5 | #include "fsw_params_nb_bytes.h" |
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6 | 6 | #include "tm_byte_positions.h" |
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7 | 7 | #include "ccsds_types.h" |
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8 | 8 | |
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9 | 9 | #define GRSPW_DEVICE_NAME "/dev/grspw0" |
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10 | 10 | #define UART_DEVICE_NAME "/dev/console" |
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11 | 11 | |
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12 | 12 | //******* |
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13 | 13 | // MACROS |
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14 | 14 | #ifdef PRINT_MESSAGES_ON_CONSOLE |
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15 | 15 | #define PRINTF(x) printf(x); |
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16 | 16 | #define PRINTF1(x,y) printf(x,y); |
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17 | 17 | #define PRINTF2(x,y,z) printf(x,y,z); |
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18 | 18 | #else |
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19 | 19 | #define PRINTF(x) ; |
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20 | 20 | #define PRINTF1(x,y) ; |
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21 | 21 | #define PRINTF2(x,y,z) ; |
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22 | 22 | #endif |
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23 | 23 | |
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24 | 24 | #ifdef BOOT_MESSAGES |
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25 | 25 | #define BOOT_PRINTF(x) printf(x); |
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26 | 26 | #define BOOT_PRINTF1(x,y) printf(x,y); |
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27 | 27 | #define BOOT_PRINTF2(x,y,z) printf(x,y,z); |
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28 | 28 | #else |
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29 | 29 | #define BOOT_PRINTF(x) ; |
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30 | 30 | #define BOOT_PRINTF1(x,y) ; |
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31 | 31 | #define BOOT_PRINTF2(x,y,z) ; |
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32 | 32 | #endif |
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33 | 33 | |
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34 | 34 | #ifdef DEBUG_MESSAGES |
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35 | 35 | #define DEBUG_PRINTF(x) printf(x); |
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36 | 36 | #define DEBUG_PRINTF1(x,y) printf(x,y); |
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37 | 37 | #define DEBUG_PRINTF2(x,y,z) printf(x,y,z); |
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38 | 38 | #else |
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39 | 39 | #define DEBUG_PRINTF(x) ; |
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40 | 40 | #define DEBUG_PRINTF1(x,y) ; |
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41 | 41 | #define DEBUG_PRINTF2(x,y,z) ; |
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42 | 42 | #endif |
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43 | 43 | |
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44 | 44 | #define CONST_65536 65536 // 2^16 |
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45 | 45 | #define CONST_2048 2048 // 2^11 |
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46 | 46 | #define CONST_512 512 // 2^9 |
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47 | 47 | #define CONST_256 256 // 2^8 |
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48 | 48 | #define CONST_128 128 // 2^7 |
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49 | 49 | #define UINT8_MAX 255 |
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50 | 50 | |
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51 | 51 | #define FLOAT_MSBYTE 0 |
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52 | 52 | #define FLOAT_LSBYTE 3 |
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53 | 53 | #define BITS_PER_BYTE 8 |
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54 | 54 | #define INIT_FLOAT 0. |
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55 | 55 | #define INIT_CHAR 0x00 |
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56 | 56 | #define INT8_ALL_F 0xff |
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57 | 57 | #define INT16_ALL_F 0xffff |
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58 | 58 | #define INT32_ALL_F 0xffffffff |
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59 | 59 | #define INT32_ALL_0 0x00000000 |
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60 | 60 | #define SHIFT_1_BYTE 8 |
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61 | 61 | #define SHIFT_2_BYTES 16 |
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62 | 62 | #define SHIFT_3_BYTES 24 |
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63 | 63 | #define SHIFT_4_BYTES 32 |
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64 | 64 | #define SHIFT_5_BYTES 40 |
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65 | 65 | #define SHIFT_2_BITS 2 |
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66 | 66 | #define SHIFT_3_BITS 3 |
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67 | 67 | #define SHIFT_4_BITS 4 |
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68 | 68 | #define SHIFT_5_BITS 5 |
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69 | 69 | #define SHIFT_6_BITS 6 |
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70 | 70 | #define SHIFT_7_BITS 7 |
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71 | 71 | #define BYTE_0 0 |
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72 | 72 | #define BYTE_1 1 |
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73 | 73 | #define BYTE_2 2 |
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74 | 74 | #define BYTE_3 3 |
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75 | 75 | #define BYTE_4 4 |
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76 | 76 | #define BYTE_5 5 |
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77 | 77 | #define BYTE_6 6 |
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78 | 78 | #define BYTE_7 7 |
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79 | 79 | #define BYTE0_MASK 0xff00 |
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80 | 80 | #define BYTE1_MASK 0x00ff |
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81 | 81 | |
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82 | 82 | enum lfr_transition_type_t{ |
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83 | 83 | TRANSITION_NOT_SPECIFIC, |
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84 | 84 | TRANSITION_NORM_TO_S1, |
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85 | 85 | TRANSITION_NORM_TO_S2, |
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86 | 86 | TRANSITION_S1_TO_NORM, |
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87 | 87 | TRANSITION_S2_TO_NORM, |
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88 | 88 | TRANSITION_S1_TO_S2, |
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89 | 89 | TRANSITION_S2_TO_S1 |
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90 | 90 | }; |
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91 | 91 | |
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92 | 92 | typedef struct ring_node |
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93 | 93 | { |
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94 | 94 | struct ring_node *previous; |
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95 | 95 | struct ring_node *next; |
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96 | 96 | unsigned int sid; |
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97 | 97 | unsigned int coarseTime; |
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98 | 98 | unsigned int fineTime; |
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99 | 99 | int buffer_address; |
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100 | 100 | unsigned int status; |
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101 | 101 | } ring_node; |
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102 | 102 | |
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103 | 103 | //************************ |
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104 | 104 | // flight software version |
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105 | 105 | // this parameters is handled by the Qt project options |
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106 | 106 | |
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107 | 107 | #define NB_PACKETS_PER_GROUP_OF_CWF 8 // 8 packets containing 336 blk |
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108 | 108 | #define NB_PACKETS_PER_GROUP_OF_CWF_LIGHT 4 // 4 packets containing 672 blk |
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109 | 109 | #define NB_SAMPLES_PER_SNAPSHOT 2688 // 336 * 8 = 672 * 4 = 2688 |
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110 | 110 | #define TIME_OFFSET 2 |
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111 | 111 | #define TIME_OFFSET_IN_BYTES 8 |
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112 | 112 | //#define WAVEFORM_EXTENDED_HEADER_OFFSET 22 |
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113 | 113 | #define NB_BYTES_SWF_BLK (2 * 6) |
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114 | 114 | #define NB_WORDS_SWF_BLK 3 |
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115 | 115 | #define NB_BYTES_CWF3_LIGHT_BLK 6 |
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116 | 116 | //#define WFRM_INDEX_OF_LAST_PACKET 6 // waveforms are transmitted in groups of 2048 blocks, 6 packets of 340 and 1 of 8 |
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117 | 117 | #define NB_RING_NODES_F0 3 // AT LEAST 3 |
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118 | 118 | #define NB_RING_NODES_F1 5 // AT LEAST 3 |
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119 | 119 | #define NB_RING_NODES_F2 5 // AT LEAST 3 |
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120 | 120 | #define NB_RING_NODES_F3 3 // AT LEAST 3 |
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121 | 121 | |
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122 | 122 | //********** |
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123 | 123 | // LFR MODES |
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124 | 124 | #define LFR_MODE_STANDBY 0 |
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125 | 125 | #define LFR_MODE_NORMAL 1 |
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126 | 126 | #define LFR_MODE_BURST 2 |
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127 | 127 | #define LFR_MODE_SBM1 3 |
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128 | 128 | #define LFR_MODE_SBM2 4 |
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129 | 129 | |
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130 | 130 | #define TDS_MODE_LFM 5 |
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131 | 131 | #define TDS_MODE_STANDBY 0 |
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132 | 132 | #define TDS_MODE_NORMAL 1 |
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133 | 133 | #define TDS_MODE_BURST 2 |
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134 | 134 | #define TDS_MODE_SBM1 3 |
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135 | 135 | #define TDS_MODE_SBM2 4 |
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136 | 136 | |
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137 | 137 | #define THR_MODE_STANDBY 0 |
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138 | 138 | #define THR_MODE_NORMAL 1 |
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139 | 139 | #define THR_MODE_BURST 2 |
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140 | 140 | |
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141 | 141 | #define RTEMS_EVENT_MODE_STANDBY RTEMS_EVENT_0 |
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142 | 142 | #define RTEMS_EVENT_MODE_NORMAL RTEMS_EVENT_1 |
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143 | 143 | #define RTEMS_EVENT_MODE_BURST RTEMS_EVENT_2 |
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144 | 144 | #define RTEMS_EVENT_MODE_SBM1 RTEMS_EVENT_3 |
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145 | 145 | #define RTEMS_EVENT_MODE_SBM2 RTEMS_EVENT_4 |
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146 | 146 | #define RTEMS_EVENT_MODE_NORM_S1_S2 RTEMS_EVENT_5 |
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147 | 147 | #define RTEMS_EVENT_NORM_BP1_F0 RTEMS_EVENT_6 |
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148 | 148 | #define RTEMS_EVENT_NORM_BP2_F0 RTEMS_EVENT_7 |
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149 | 149 | #define RTEMS_EVENT_NORM_ASM_F0 RTEMS_EVENT_8 // ASM only in NORM mode |
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150 | 150 | #define RTEMS_EVENT_NORM_BP1_F1 RTEMS_EVENT_9 |
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151 | 151 | #define RTEMS_EVENT_NORM_BP2_F1 RTEMS_EVENT_10 |
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152 | 152 | #define RTEMS_EVENT_NORM_ASM_F1 RTEMS_EVENT_11 // ASM only in NORM mode |
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153 | 153 | #define RTEMS_EVENT_NORM_BP1_F2 RTEMS_EVENT_12 |
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154 | 154 | #define RTEMS_EVENT_NORM_BP2_F2 RTEMS_EVENT_13 |
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155 | 155 | #define RTEMS_EVENT_NORM_ASM_F2 RTEMS_EVENT_14 // ASM only in NORM mode |
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156 | 156 | #define RTEMS_EVENT_SBM_BP1_F0 RTEMS_EVENT_15 |
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157 | 157 | #define RTEMS_EVENT_SBM_BP2_F0 RTEMS_EVENT_16 |
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158 | 158 | #define RTEMS_EVENT_SBM_BP1_F1 RTEMS_EVENT_17 |
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159 | 159 | #define RTEMS_EVENT_SBM_BP2_F1 RTEMS_EVENT_18 |
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160 | 160 | #define RTEMS_EVENT_BURST_BP1_F0 RTEMS_EVENT_19 |
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161 | 161 | #define RTEMS_EVENT_BURST_BP2_F0 RTEMS_EVENT_20 |
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162 | 162 | #define RTEMS_EVENT_BURST_BP1_F1 RTEMS_EVENT_21 |
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163 | 163 | #define RTEMS_EVENT_BURST_BP2_F1 RTEMS_EVENT_22 |
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164 | 164 | #define RTEMS_EVENT_SWF_RESYNCH RTEMS_EVENT_23 |
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165 | 165 | |
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166 | 166 | //******************************************** |
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167 | 167 | //******************************************** |
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168 | 168 | // LFR PARAMETERS: DEFAULT, MIN AND MAX VALUES |
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169 | 169 | |
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170 | 170 | #define DEFAULT_LAST_VALID_TRANSITION_DATE 0xffffffff |
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171 | 171 | |
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172 | 172 | // COMMON |
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173 | 173 | #define DEFAULT_SY_LFR_COMMON0 0x00 |
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174 | 174 | #define DEFAULT_SY_LFR_COMMON1 0x20 // default value bw sp0 sp1 r0 r1 r2 = 1 0 0 0 0 0 |
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175 | 175 | |
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176 | 176 | // NORM |
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177 | 177 | #define DFLT_SY_LFR_N_SWF_L 2048 // nb sample |
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178 | 178 | #define DFLT_SY_LFR_N_SWF_P 300 // sec |
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179 | 179 | #define MIN_SY_LFR_N_SWF_P 22 // sec |
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180 | 180 | #define DFLT_SY_LFR_N_ASM_P 3600 // sec |
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181 | 181 | #define DFLT_SY_LFR_N_BP_P0 4 // sec |
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182 | 182 | #define DFLT_SY_LFR_N_BP_P1 20 // sec |
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183 | 183 | #define DFLT_SY_LFR_N_CWF_LONG_F3 0 // 0 => production of light continuous waveforms at f3 |
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184 | 184 | #define MIN_DELTA_SNAPSHOT 16 // sec |
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185 | 185 | |
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186 | 186 | // BURST |
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187 | 187 | #define DEFAULT_SY_LFR_B_BP_P0 1 // sec |
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188 | 188 | #define DEFAULT_SY_LFR_B_BP_P1 5 // sec |
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189 | 189 | |
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190 | 190 | // SBM1 |
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191 | 191 | #define S1_BP_P0_SCALE 0.25 |
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192 | 192 | #define DEFAULT_SY_LFR_S1_BP_P0 1 // 0.25 sec |
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193 | 193 | #define DEFAULT_SY_LFR_S1_BP_P1 1 // sec |
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194 | 194 | |
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195 | 195 | // SBM2 |
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196 | 196 | #define DEFAULT_SY_LFR_S2_BP_P0 1 // sec |
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197 | 197 | #define DEFAULT_SY_LFR_S2_BP_P1 5 // sec |
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198 | 198 | |
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199 | 199 | // ADDITIONAL PARAMETERS |
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200 | 200 | #define TIME_BETWEEN_TWO_SWF_PACKETS 30 // nb x 10 ms => 300 ms |
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201 | 201 | #define TIME_BETWEEN_TWO_CWF3_PACKETS 1000 // nb x 10 ms => 10 s |
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202 | 202 | |
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203 | 203 | // STATUS WORD |
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204 | 204 | #define DEFAULT_STATUS_WORD_BYTE0 0x0d // [0000] [1] [101] mode 4 bits / SPW enabled 1 bit / state is run 3 bits |
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205 | 205 | |
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206 | 206 | #define DEFAULT_STATUS_WORD_BYTE1 0x00 |
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207 | 207 | // TC_LFR_LOAD_FILTER_PAR |
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208 | 208 | #define MIN_PAS_FILTER_MODULUS 4 |
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209 | 209 | #define MAX_PAS_FILTER_MODULUS 8 |
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210 | 210 | #define MIN_PAS_FILTER_TBAD 0.0 |
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211 | 211 | #define MAX_PAS_FILTER_TBAD 4.0 |
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212 | 212 | #define MIN_PAS_FILTER_OFFSET 0 |
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213 | 213 | #define MAX_PAS_FILTER_OFFSET 7 |
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214 | 214 | #define MIN_PAS_FILTER_SHIFT 0.0 |
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215 | 215 | #define MAX_PAS_FILTER_SHIFT 1.0 |
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216 | #define MIN_SY_LFR_SC_RW_DELTA_F 0 | |
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217 | #define MIN_SY_LFR_RW_K 0 | |
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216 | 218 | // |
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217 | 219 | #define SY_LFR_DPU_CONNECT_TIMEOUT 100 // 100 * 10 ms = 1 s |
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218 | 220 | #define SY_LFR_DPU_CONNECT_ATTEMPT 3 |
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219 | 221 | //**************************** |
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220 | 222 | |
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221 | 223 | //***************************** |
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222 | 224 | // APB REGISTERS BASE ADDRESSES |
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223 | 225 | #define REGS_ADDR_APBUART 0x80000100 |
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224 | 226 | #define REGS_ADDR_GPTIMER 0x80000300 |
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225 | 227 | #define REGS_ADDR_GRSPW 0x80000500 |
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226 | 228 | #define APB_OFFSET_GRSPW_STATUS_REGISTER 0x04 |
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227 | 229 | #define APB_OFFSET_GRSPW_TIME_REGISTER 0x14 |
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228 | 230 | #define REGS_ADDR_TIME_MANAGEMENT 0x80000600 |
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229 | 231 | #define REGS_ADDR_GRGPIO 0x80000b00 |
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230 | 232 | |
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231 | 233 | #define REGS_ADDR_SPECTRAL_MATRIX 0x80000f00 |
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232 | 234 | #define REGS_ADDR_WAVEFORM_PICKER 0x80000f54 // PDB >= 0.1.28 |
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233 | 235 | #define APB_OFFSET_VHDL_REV 0xb0 |
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234 | 236 | #define REGS_ADDR_VHDL_VERSION 0x80000ff0 |
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235 | 237 | |
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236 | 238 | #define APBUART_CTRL_REG_MASK_DB 0xfffff7ff |
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237 | 239 | #define APBUART_CTRL_REG_MASK_TE 0x00000002 |
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238 | 240 | // scaler value = system_clock_frequency / ( baud_rate * 8 ) - 1 |
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239 | 241 | #define APBUART_SCALER_RELOAD_VALUE 0x00000050 // 25 MHz => about 38400 |
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240 | 242 | |
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241 | 243 | //********** |
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242 | 244 | // IRQ LINES |
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243 | 245 | #define IRQ_GPTIMER_WATCHDOG 9 |
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244 | 246 | #define IRQ_SPARC_GPTIMER_WATCHDOG 0x19 // see sparcv8.pdf p.76 for interrupt levels |
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245 | 247 | #define IRQ_WAVEFORM_PICKER 14 |
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246 | 248 | #define IRQ_SPARC_WAVEFORM_PICKER 0x1e // see sparcv8.pdf p.76 for interrupt levels |
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247 | 249 | #define IRQ_SPECTRAL_MATRIX 6 |
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248 | 250 | #define IRQ_SPARC_SPECTRAL_MATRIX 0x16 // see sparcv8.pdf p.76 for interrupt levels |
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249 | 251 | |
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250 | 252 | //***** |
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251 | 253 | // TIME |
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252 | 254 | #define CLKDIV_WATCHDOG (10000000 - 1) // 10.0s => 10 000 000 |
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253 | 255 | #define TIMER_WATCHDOG 1 |
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254 | 256 | #define WATCHDOG_PERIOD 100 // 1s |
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255 | 257 | #define HK_PERIOD 100 // 100 * 10ms => 1s |
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256 | 258 | #define AVGV_PERIOD 6 // 6 * 10ms => 60ms (1 / 16 = 62.5ms) |
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257 | 259 | #define SY_LFR_TIME_SYN_TIMEOUT_in_ticks 200 // 200 * 10 ms = 2 s |
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258 | 260 | #define HK_SYNC_WAIT 10 // 10 * 10 ms = 100 ms |
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259 | 261 | #define SPW_LINK_WAIT 10 // 10 * 10 ms = 100 ms |
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260 | 262 | #define TIMECODE_TIMER_TIMEOUT 120 // 120 * 10 ms = 1.2 s |
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261 | 263 | #define TIMECODE_TIMER_TIMEOUT_INIT 200 // 200 * 10 ms = 2.0 s |
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262 | 264 | #define TIMECODE_MASK 0x3f // 0011 1111 |
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263 | 265 | |
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264 | 266 | //********** |
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265 | 267 | // LPP CODES |
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266 | 268 | #define LFR_SUCCESSFUL 0 |
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267 | 269 | #define LFR_DEFAULT 1 |
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268 | 270 | #define LFR_EXE_ERROR 2 |
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271 | #define LFR_DEFAULT_ALT -1 | |
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269 | 272 | |
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270 | 273 | //****** |
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271 | 274 | // RTEMS |
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272 | 275 | #define STACK_SIZE_MULT 2 |
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273 | 276 | |
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274 | 277 | #define TASKID_AVGV 0 |
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275 | 278 | #define TASKID_RECV 1 |
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276 | 279 | #define TASKID_ACTN 2 |
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277 | 280 | #define TASKID_SPIQ 3 |
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278 | 281 | #define TASKID_LOAD 4 |
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279 | 282 | #define TASKID_AVF0 5 |
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280 | 283 | #define TASKID_SWBD 6 |
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281 | 284 | #define TASKID_WFRM 7 |
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282 | 285 | #define TASKID_DUMB 8 |
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283 | 286 | #define TASKID_HOUS 9 |
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284 | 287 | #define TASKID_PRC0 10 |
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285 | 288 | #define TASKID_CWF3 11 |
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286 | 289 | #define TASKID_CWF2 12 |
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287 | 290 | #define TASKID_CWF1 13 |
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288 | 291 | #define TASKID_SEND 14 |
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289 | 292 | #define TASKID_LINK 15 |
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290 | 293 | #define TASKID_AVF1 16 |
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291 | 294 | #define TASKID_PRC1 17 |
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292 | 295 | #define TASKID_AVF2 18 |
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293 | 296 | #define TASKID_PRC2 19 |
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294 | 297 | |
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295 | 298 | #define TASK_PRIORITY_SPIQ 5 |
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296 | 299 | #define TASK_PRIORITY_LINK 20 |
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297 | 300 | #define TASK_PRIORITY_AVGV 25 |
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298 | 301 | #define TASK_PRIORITY_HOUS 30 |
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299 | 302 | #define TASK_PRIORITY_CWF1 35 // CWF1 and CWF2 are never running together |
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300 | 303 | #define TASK_PRIORITY_CWF2 35 // |
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301 | 304 | #define TASK_PRIORITY_SWBD 37 // SWBD has a lower priority than WFRM, this is to extract the snapshot before sending it |
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302 | 305 | #define TASK_PRIORITY_WFRM 40 |
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303 | 306 | #define TASK_PRIORITY_CWF3 40 // there is a printf in this function, be careful with its priority wrt CWF1 |
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304 | 307 | #define TASK_PRIORITY_SEND 45 |
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305 | 308 | #define TASK_PRIORITY_RECV 50 |
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306 | 309 | #define TASK_PRIORITY_ACTN 50 |
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307 | 310 | #define TASK_PRIORITY_AVF0 60 |
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308 | 311 | #define TASK_PRIORITY_AVF1 70 |
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309 | 312 | #define TASK_PRIORITY_PRC0 100 |
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310 | 313 | #define TASK_PRIORITY_PRC1 100 |
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311 | 314 | #define TASK_PRIORITY_AVF2 110 |
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312 | 315 | #define TASK_PRIORITY_PRC2 110 |
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313 | 316 | #define TASK_PRIORITY_LOAD 190 |
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314 | 317 | #define TASK_PRIORITY_DUMB 200 |
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315 | 318 | |
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316 | 319 | #define MSG_QUEUE_COUNT_RECV 10 |
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317 | 320 | #define MSG_QUEUE_COUNT_SEND 50 |
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318 | 321 | #define MSG_QUEUE_COUNT_PRC0 10 |
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319 | 322 | #define MSG_QUEUE_COUNT_PRC1 10 |
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320 | 323 | #define MSG_QUEUE_COUNT_PRC2 5 |
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321 | 324 | #define MSG_QUEUE_SIZE_SEND 812 // 808 + 4 => TM_LFR_SCIENCE_BURST_BP2_F1 |
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322 | 325 | #define ACTION_MSG_SPW_IOCTL_SEND_SIZE 24 // hlen *hdr dlen *data sent options |
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323 | 326 | #define MSG_QUEUE_SIZE_PRC0 36 // two pointers, one rtems_event + 6 integers |
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324 | 327 | #define MSG_QUEUE_SIZE_PRC1 36 // two pointers, one rtems_event + 6 integers |
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325 | 328 | #define MSG_QUEUE_SIZE_PRC2 36 // two pointers, one rtems_event + 6 integers |
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326 | 329 | |
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327 | 330 | #define QUEUE_RECV 0 |
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328 | 331 | #define QUEUE_SEND 1 |
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329 | 332 | #define QUEUE_PRC0 2 |
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330 | 333 | #define QUEUE_PRC1 3 |
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331 | 334 | #define QUEUE_PRC2 4 |
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332 | 335 | |
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333 | 336 | #define CPU_USAGE_REPORT_PERIOD 6 // * 10 s = period |
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334 | 337 | |
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335 | 338 | struct param_local_str{ |
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336 | 339 | unsigned int local_sbm1_nb_cwf_sent; |
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337 | 340 | unsigned int local_sbm1_nb_cwf_max; |
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338 | 341 | unsigned int local_sbm2_nb_cwf_sent; |
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339 | 342 | unsigned int local_sbm2_nb_cwf_max; |
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340 | 343 | }; |
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341 | 344 | |
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342 | 345 | //************ |
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343 | 346 | // FBINS MASKS |
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344 | 347 | |
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345 | 348 | #define BYTES_PER_FBINS_MASK 16 |
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346 | 349 | |
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347 | 350 | typedef struct { |
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348 | 351 | unsigned char merged_fbins_mask_f0[BYTES_PER_FBINS_MASK]; |
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349 | 352 | unsigned char merged_fbins_mask_f1[BYTES_PER_FBINS_MASK]; |
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350 | 353 | unsigned char merged_fbins_mask_f2[BYTES_PER_FBINS_MASK]; |
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351 | 354 | } fbins_masks_t; |
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352 | 355 | |
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353 | 356 | #define DEFAULT_SY_LFR_PAS_FILTER_ENABLED 0 |
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354 | 357 | #define DEFAULT_SY_LFR_PAS_FILTER_MODULUS 4 |
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355 | 358 | #define DEFAULT_SY_LFR_PAS_FILTER_TBAD 1.0 |
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356 | 359 | #define DEFAULT_SY_LFR_PAS_FILTER_OFFSET 0 |
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357 | 360 | #define DEFAULT_SY_LFR_PAS_FILTER_SHIFT 0.5 |
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358 | 361 | #define DEFAULT_SY_LFR_SC_RW_DELTA_F 0.045 |
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359 | 362 | #define DEFAULT_SY_LFR_RW_K1 1. |
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360 | 363 | #define DEFAULT_SY_LFR_RW_K2 8. |
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361 | 364 | #define DEFAULT_SY_LFR_RW_K3 24. |
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362 | 365 | #define DEFAULT_SY_LFR_RW_K4 48. |
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363 | 366 | |
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364 | 367 | typedef struct{ |
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365 | 368 | unsigned char spare_sy_lfr_pas_filter_enabled; |
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366 | 369 | unsigned char sy_lfr_pas_filter_modulus; |
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367 | 370 | float sy_lfr_pas_filter_tbad; |
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368 | 371 | unsigned char sy_lfr_pas_filter_offset; |
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369 | 372 | float sy_lfr_pas_filter_shift; |
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370 | 373 | float sy_lfr_sc_rw_delta_f; |
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371 | 374 | // rw1_k |
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372 | 375 | float sy_lfr_rw1_k1; |
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373 | 376 | float sy_lfr_rw1_k2; |
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374 | 377 | float sy_lfr_rw1_k3; |
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375 | 378 | float sy_lfr_rw1_k4; |
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376 | 379 | // rw2_k |
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377 | 380 | float sy_lfr_rw2_k1; |
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378 | 381 | float sy_lfr_rw2_k2; |
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379 | 382 | float sy_lfr_rw2_k3; |
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380 | 383 | float sy_lfr_rw2_k4; |
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381 | 384 | // rw3_k |
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382 | 385 | float sy_lfr_rw3_k1; |
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383 | 386 | float sy_lfr_rw3_k2; |
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384 | 387 | float sy_lfr_rw3_k3; |
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385 | 388 | float sy_lfr_rw3_k4; |
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386 | 389 | // rw4_k |
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387 | 390 | float sy_lfr_rw4_k1; |
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388 | 391 | float sy_lfr_rw4_k2; |
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389 | 392 | float sy_lfr_rw4_k3; |
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390 | 393 | float sy_lfr_rw4_k4; |
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391 | 394 | } filterPar_t; |
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392 | 395 | |
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393 | 396 | typedef struct{ |
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394 | 397 | // rw1_f |
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395 | 398 | float cp_rpw_sc_rw1_f1; |
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396 | 399 | float cp_rpw_sc_rw1_f2; |
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397 | 400 | float cp_rpw_sc_rw1_f3; |
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398 | 401 | float cp_rpw_sc_rw1_f4; |
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399 | 402 | // rw2_f |
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400 | 403 | float cp_rpw_sc_rw2_f1; |
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401 | 404 | float cp_rpw_sc_rw2_f2; |
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402 | 405 | float cp_rpw_sc_rw2_f3; |
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403 | 406 | float cp_rpw_sc_rw2_f4; |
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404 | 407 | // rw3_f |
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405 | 408 | float cp_rpw_sc_rw3_f1; |
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406 | 409 | float cp_rpw_sc_rw3_f2; |
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407 | 410 | float cp_rpw_sc_rw3_f3; |
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408 | 411 | float cp_rpw_sc_rw3_f4; |
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409 | 412 | // rw4_f |
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410 | 413 | float cp_rpw_sc_rw4_f1; |
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411 | 414 | float cp_rpw_sc_rw4_f2; |
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412 | 415 | float cp_rpw_sc_rw4_f3; |
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413 | 416 | float cp_rpw_sc_rw4_f4; |
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414 | 417 | } rw_f_t; |
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415 | 418 | |
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416 | 419 | #define NB_ACQUISITION_DURATION 3 |
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417 | 420 | #define ACQUISITION_DURATION_F0 683 // 256 / 24576 * 65536 |
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418 | 421 | #define ACQUISITION_DURATION_F1 4096 // 256 / 4096 * 65536 |
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419 | 422 | #define ACQUISITION_DURATION_F2 65536 // 256 / 256 * 65536 |
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420 | 423 | |
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421 | 424 | #endif // FSW_PARAMS_H_INCLUDED |
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