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enum lfr_transition_type_t created
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1 1 #ifndef FSW_PARAMS_H_INCLUDED
2 2 #define FSW_PARAMS_H_INCLUDED
3 3
4 4 #include "fsw_params_processing.h"
5 5 #include "fsw_params_nb_bytes.h"
6 6 #include "tm_byte_positions.h"
7 7 #include "ccsds_types.h"
8 8
9 9 #define GRSPW_DEVICE_NAME "/dev/grspw0"
10 10 #define UART_DEVICE_NAME "/dev/console"
11 11
12 enum lfr_transition_type_t{
13 TRANSITION_NOT_SPECIFIC,
14 TRANSITION_NORM_TO_S1,
15 TRANSITION_NORM_TO_S2,
16 TRANSITION_S1_TO_NORM,
17 TRANSITION_S2_TO_NORM,
18 TRANSITION_S1_TO_S2,
19 TRANSITION_S2_TO_S1
20 };
21
12 22 typedef struct ring_node
13 23 {
14 24 struct ring_node *previous;
15 25 struct ring_node *next;
16 26 unsigned int sid;
17 27 unsigned int coarseTime;
18 28 unsigned int fineTime;
19 29 int buffer_address;
20 30 unsigned int status;
21 31 } ring_node;
22 32
23 33 //************************
24 34 // flight software version
25 35 // this parameters is handled by the Qt project options
26 36
27 37 #define NB_PACKETS_PER_GROUP_OF_CWF 8 // 8 packets containing 336 blk
28 38 #define NB_PACKETS_PER_GROUP_OF_CWF_LIGHT 4 // 4 packets containing 672 blk
29 39 #define NB_SAMPLES_PER_SNAPSHOT 2688 // 336 * 8 = 672 * 4 = 2688
30 40 #define TIME_OFFSET 2
31 41 #define TIME_OFFSET_IN_BYTES 8
32 42 //#define WAVEFORM_EXTENDED_HEADER_OFFSET 22
33 43 #define NB_BYTES_SWF_BLK (2 * 6)
34 44 #define NB_WORDS_SWF_BLK 3
35 45 #define NB_BYTES_CWF3_LIGHT_BLK 6
36 46 //#define WFRM_INDEX_OF_LAST_PACKET 6 // waveforms are transmitted in groups of 2048 blocks, 6 packets of 340 and 1 of 8
37 47 #define NB_RING_NODES_F0 3 // AT LEAST 3
38 48 #define NB_RING_NODES_F1 5 // AT LEAST 3
39 49 #define NB_RING_NODES_F2 5 // AT LEAST 3
40 50 #define NB_RING_NODES_F3 3 // AT LEAST 3
41 51
42 52 //**********
43 53 // LFR MODES
44 54 #define LFR_MODE_STANDBY 0
45 55 #define LFR_MODE_NORMAL 1
46 56 #define LFR_MODE_BURST 2
47 57 #define LFR_MODE_SBM1 3
48 58 #define LFR_MODE_SBM2 4
49 59
50 60 #define TDS_MODE_LFM 5
51 61 #define TDS_MODE_STANDBY 0
52 62 #define TDS_MODE_NORMAL 1
53 63 #define TDS_MODE_BURST 2
54 64 #define TDS_MODE_SBM1 3
55 65 #define TDS_MODE_SBM2 4
56 66
57 67 #define THR_MODE_STANDBY 0
58 68 #define THR_MODE_NORMAL 1
59 69 #define THR_MODE_BURST 2
60 70
61 71 #define RTEMS_EVENT_MODE_STANDBY RTEMS_EVENT_0
62 72 #define RTEMS_EVENT_MODE_NORMAL RTEMS_EVENT_1
63 73 #define RTEMS_EVENT_MODE_BURST RTEMS_EVENT_2
64 74 #define RTEMS_EVENT_MODE_SBM1 RTEMS_EVENT_3
65 75 #define RTEMS_EVENT_MODE_SBM2 RTEMS_EVENT_4
66 76 #define RTEMS_EVENT_MODE_NORM_S1_S2 RTEMS_EVENT_5
67 77 #define RTEMS_EVENT_NORM_BP1_F0 RTEMS_EVENT_6
68 78 #define RTEMS_EVENT_NORM_BP2_F0 RTEMS_EVENT_7
69 79 #define RTEMS_EVENT_NORM_ASM_F0 RTEMS_EVENT_8 // ASM only in NORM mode
70 80 #define RTEMS_EVENT_NORM_BP1_F1 RTEMS_EVENT_9
71 81 #define RTEMS_EVENT_NORM_BP2_F1 RTEMS_EVENT_10
72 82 #define RTEMS_EVENT_NORM_ASM_F1 RTEMS_EVENT_11 // ASM only in NORM mode
73 83 #define RTEMS_EVENT_NORM_BP1_F2 RTEMS_EVENT_12
74 84 #define RTEMS_EVENT_NORM_BP2_F2 RTEMS_EVENT_13
75 85 #define RTEMS_EVENT_NORM_ASM_F2 RTEMS_EVENT_14 // ASM only in NORM mode
76 86 #define RTEMS_EVENT_SBM_BP1_F0 RTEMS_EVENT_15
77 87 #define RTEMS_EVENT_SBM_BP2_F0 RTEMS_EVENT_16
78 88 #define RTEMS_EVENT_SBM_BP1_F1 RTEMS_EVENT_17
79 89 #define RTEMS_EVENT_SBM_BP2_F1 RTEMS_EVENT_18
80 90 #define RTEMS_EVENT_BURST_BP1_F0 RTEMS_EVENT_19
81 91 #define RTEMS_EVENT_BURST_BP2_F0 RTEMS_EVENT_20
82 92 #define RTEMS_EVENT_BURST_BP1_F1 RTEMS_EVENT_21
83 93 #define RTEMS_EVENT_BURST_BP2_F1 RTEMS_EVENT_22
84 94
85 95 //****************************
86 96 // LFR DEFAULT MODE PARAMETERS
87 97 #define DEFAULT_LAST_VALID_TRANSITION_DATE 0x00
88 98 // COMMON
89 99 #define DEFAULT_SY_LFR_COMMON0 0x00
90 100 #define DEFAULT_SY_LFR_COMMON1 0x20 // default value bw sp0 sp1 r0 r1 r2 = 1 0 0 0 0 0
91 101 // NORM
92 102 #define DFLT_SY_LFR_N_SWF_L 2048 // nb sample
93 103 #define DFLT_SY_LFR_N_SWF_P 300 // sec
94 104 #define DFLT_SY_LFR_N_ASM_P 3600 // sec
95 105 #define DFLT_SY_LFR_N_BP_P0 4 // sec
96 106 #define DFLT_SY_LFR_N_BP_P1 20 // sec
97 107 #define DFLT_SY_LFR_N_CWF_LONG_F3 0 // 0 => production of light continuous waveforms at f3
98 108 #define MIN_DELTA_SNAPSHOT 16 // sec
99 109 // BURST
100 110 #define DEFAULT_SY_LFR_B_BP_P0 1 // sec
101 111 #define DEFAULT_SY_LFR_B_BP_P1 5 // sec
102 112 // SBM1
103 113 #define DEFAULT_SY_LFR_S1_BP_P0 1 // sec
104 114 #define DEFAULT_SY_LFR_S1_BP_P1 1 // sec
105 115 // SBM2
106 116 #define DEFAULT_SY_LFR_S2_BP_P0 1 // sec
107 117 #define DEFAULT_SY_LFR_S2_BP_P1 5 // sec
108 118 // ADDITIONAL PARAMETERS
109 119 #define TIME_BETWEEN_TWO_SWF_PACKETS 30 // nb x 10 ms => 300 ms
110 120 #define TIME_BETWEEN_TWO_CWF3_PACKETS 1000 // nb x 10 ms => 10 s
111 121 // STATUS WORD
112 122 #define DEFAULT_STATUS_WORD_BYTE0 0x0d // [0000] [1] [101] mode 4 bits / SPW enabled 1 bit / state is run 3 bits
113 123 #define DEFAULT_STATUS_WORD_BYTE1 0x00
114 124 //
115 125 #define SY_LFR_DPU_CONNECT_TIMEOUT 100 // 100 * 10 ms = 1 s
116 126 #define SY_LFR_DPU_CONNECT_ATTEMPT 3
117 127 //****************************
118 128
119 129 //*****************************
120 130 // APB REGISTERS BASE ADDRESSES
121 131 #define REGS_ADDR_APBUART 0x80000100
122 132 #define REGS_ADDR_GPTIMER 0x80000300
123 133 #define REGS_ADDR_GRSPW 0x80000500
124 134 #define APB_OFFSET_GRSPW_TIME_REGISTER 0x14
125 135 #define REGS_ADDR_TIME_MANAGEMENT 0x80000600
126 136 #define REGS_ADDR_GRGPIO 0x80000b00
127 137
128 138 #define REGS_ADDR_SPECTRAL_MATRIX 0x80000f00
129 139 //#define REGS_ADDR_WAVEFORM_PICKER 0x80000f50
130 140 #define REGS_ADDR_WAVEFORM_PICKER 0x80000f54 // PDB >= 0.1.28
131 141 #define REGS_ADDR_VHDL_VERSION 0x80000ff0
132 142
133 143 #define APBUART_CTRL_REG_MASK_DB 0xfffff7ff
134 144 #define APBUART_CTRL_REG_MASK_TE 0x00000002
135 145 // scaler value = system_clock_frequency / ( baud_rate * 8 ) - 1
136 146 #define APBUART_SCALER_RELOAD_VALUE 0x00000050 // 25 MHz => about 38400
137 147
138 148 //**********
139 149 // IRQ LINES
140 150 #define IRQ_GPTIMER_WATCHDOG 9
141 151 #define IRQ_SPARC_GPTIMER_WATCHDOG 0x19 // see sparcv8.pdf p.76 for interrupt levels
142 152 #define IRQ_WAVEFORM_PICKER 14
143 153 #define IRQ_SPARC_WAVEFORM_PICKER 0x1e // see sparcv8.pdf p.76 for interrupt levels
144 154 #define IRQ_SPECTRAL_MATRIX 6
145 155 #define IRQ_SPARC_SPECTRAL_MATRIX 0x16 // see sparcv8.pdf p.76 for interrupt levels
146 156
147 157 //*****
148 158 // TIME
149 159 #define CLKDIV_WATCHDOG (1100000 - 1) // 1.1s => 1100000
150 160 #define TIMER_WATCHDOG 1
151 161 #define WATCHDOG_PERIOD 100 // 1s
152 162 #define HK_PERIOD 100 // 100 * 10ms => 1s
153 163 #define SY_LFR_TIME_SYN_TIMEOUT_in_ms 2000
154 164 #define SY_LFR_TIME_SYN_TIMEOUT_in_ticks 200 // 200 * 10 ms = 2 s
155 165
156 166 //**********
157 167 // LPP CODES
158 168 #define LFR_SUCCESSFUL 0
159 169 #define LFR_DEFAULT 1
160 170 #define LFR_EXE_ERROR 2
161 171
162 172 //******
163 173 // RTEMS
164 174 #define TASKID_RECV 1
165 175 #define TASKID_ACTN 2
166 176 #define TASKID_SPIQ 3
167 177 #define TASKID_LOAD 4
168 178 #define TASKID_AVF0 5
169 179 #define TASKID_SWBD 6
170 180 #define TASKID_WFRM 7
171 181 #define TASKID_DUMB 8
172 182 #define TASKID_HOUS 9
173 183 #define TASKID_PRC0 10
174 184 #define TASKID_CWF3 11
175 185 #define TASKID_CWF2 12
176 186 #define TASKID_CWF1 13
177 187 #define TASKID_SEND 14
178 188 #define TASKID_WTDG 15
179 189 #define TASKID_AVF1 16
180 190 #define TASKID_PRC1 17
181 191 #define TASKID_AVF2 18
182 192 #define TASKID_PRC2 19
183 193
184 194 #define TASK_PRIORITY_SPIQ 5
185 195 #define TASK_PRIORITY_WTDG 20
186 196 #define TASK_PRIORITY_HOUS 30
187 197 #define TASK_PRIORITY_CWF1 35 // CWF1 and CWF2 are never running together
188 198 #define TASK_PRIORITY_CWF2 35 //
189 199 #define TASK_PRIORITY_SWBD 37 // SWBD has a lower priority than WFRM, this is to extract the snapshot before sending it
190 200 #define TASK_PRIORITY_WFRM 40
191 201 #define TASK_PRIORITY_CWF3 40 // there is a printf in this function, be careful with its priority wrt CWF1
192 202 #define TASK_PRIORITY_SEND 45
193 203 #define TASK_PRIORITY_RECV 50
194 204 #define TASK_PRIORITY_ACTN 50
195 205 #define TASK_PRIORITY_AVF0 60
196 206 #define TASK_PRIORITY_AVF1 70
197 207 #define TASK_PRIORITY_PRC0 100
198 208 #define TASK_PRIORITY_PRC1 100
199 209 #define TASK_PRIORITY_AVF2 110
200 210 #define TASK_PRIORITY_PRC2 110
201 211 #define TASK_PRIORITY_DUMB 200
202 212 #define TASK_PRIORITY_LOAD 220
203 213
204 214 #define MSG_QUEUE_COUNT_RECV 10
205 215 #define MSG_QUEUE_COUNT_SEND 50
206 216 #define MSG_QUEUE_COUNT_PRC0 10
207 217 #define MSG_QUEUE_COUNT_PRC1 10
208 218 #define MSG_QUEUE_COUNT_PRC2 5
209 219 #define MSG_QUEUE_SIZE_SEND 812 // 808 + 4 => TM_LFR_SCIENCE_BURST_BP2_F1
210 220 #define ACTION_MSG_SPW_IOCTL_SEND_SIZE 24 // hlen *hdr dlen *data sent options
211 221 #define MSG_QUEUE_SIZE_PRC0 28 // two pointers, one rtems_event + 4 integers
212 222 #define MSG_QUEUE_SIZE_PRC1 28 // two pointers, one rtems_event + 4 integers
213 223 #define MSG_QUEUE_SIZE_PRC2 28 // two pointers, one rtems_event + 4 integers
214 224
215 225 #define QUEUE_RECV 0
216 226 #define QUEUE_SEND 1
217 227 #define QUEUE_PRC0 2
218 228 #define QUEUE_PRC1 3
219 229 #define QUEUE_PRC2 4
220 230
221 231 //*******
222 232 // MACROS
223 233 #ifdef PRINT_MESSAGES_ON_CONSOLE
224 234 #define PRINTF(x) printf(x);
225 235 #define PRINTF1(x,y) printf(x,y);
226 236 #define PRINTF2(x,y,z) printf(x,y,z);
227 237 #else
228 238 #define PRINTF(x) ;
229 239 #define PRINTF1(x,y) ;
230 240 #define PRINTF2(x,y,z) ;
231 241 #endif
232 242
233 243 #ifdef BOOT_MESSAGES
234 244 #define BOOT_PRINTF(x) printf(x);
235 245 #define BOOT_PRINTF1(x,y) printf(x,y);
236 246 #define BOOT_PRINTF2(x,y,z) printf(x,y,z);
237 247 #else
238 248 #define BOOT_PRINTF(x) ;
239 249 #define BOOT_PRINTF1(x,y) ;
240 250 #define BOOT_PRINTF2(x,y,z) ;
241 251 #endif
242 252
243 253 #ifdef DEBUG_MESSAGES
244 254 #define DEBUG_PRINTF(x) printf(x);
245 255 #define DEBUG_PRINTF1(x,y) printf(x,y);
246 256 #define DEBUG_PRINTF2(x,y,z) printf(x,y,z);
247 257 #else
248 258 #define DEBUG_PRINTF(x) ;
249 259 #define DEBUG_PRINTF1(x,y) ;
250 260 #define DEBUG_PRINTF2(x,y,z) ;
251 261 #endif
252 262
253 263 #define CPU_USAGE_REPORT_PERIOD 6 // * 10 s = period
254 264
255 265 struct param_local_str{
256 266 unsigned int local_sbm1_nb_cwf_sent;
257 267 unsigned int local_sbm1_nb_cwf_max;
258 268 unsigned int local_sbm2_nb_cwf_sent;
259 269 unsigned int local_sbm2_nb_cwf_max;
260 270 };
261 271
262 272 #endif // FSW_PARAMS_H_INCLUDED
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