@@ -18,15 +18,11 | |||||
18 | #define CCSDS_PROTOCOLE_EXTRA_BYTES 4 |
|
18 | #define CCSDS_PROTOCOLE_EXTRA_BYTES 4 | |
19 | #define CCSDS_TC_TM_PACKET_OFFSET 7 |
|
19 | #define CCSDS_TC_TM_PACKET_OFFSET 7 | |
20 | #define PROTID_RES_APP 3 |
|
20 | #define PROTID_RES_APP 3 | |
21 | #define CCSDS_TELEMETRY_HEADER_LENGTH (16+4) |
|
|||
22 | #define CCSDS_TC_HEADER_LENGTH 10 |
|
21 | #define CCSDS_TC_HEADER_LENGTH 10 | |
23 | #define CCSDS_TM_PKT_MAX_SIZE 4412 |
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|||
24 | #define CCSDS_TELECOMMAND_HEADER_LENGTH (10+4) |
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|||
25 | #define CCSDS_TC_PKT_MAX_SIZE 232 // (228+3) with 3 for Prot ID, Reserved and User App bytes, SHALL BE A MULTIPLE OF 4 |
|
22 | #define CCSDS_TC_PKT_MAX_SIZE 232 // (228+3) with 3 for Prot ID, Reserved and User App bytes, SHALL BE A MULTIPLE OF 4 | |
26 | #define CCSDS_TC_PKT_MIN_SIZE 16 |
|
23 | #define CCSDS_TC_PKT_MIN_SIZE 16 | |
27 | #define CCSDS_PROCESS_ID 76 |
|
24 | #define CCSDS_PROCESS_ID 76 | |
28 | #define CCSDS_PACKET_CATEGORY 12 |
|
25 | #define CCSDS_PACKET_CATEGORY 12 | |
29 | #define CCSDS_NODE_ADDRESS 0xfe |
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|||
30 | #define CCSDS_USER_APP 0x00 |
|
26 | #define CCSDS_USER_APP 0x00 | |
31 |
|
27 | |||
32 | #define DEFAULT_SPARE1_PUSVERSION_SPARE2 0x10 |
|
28 | #define DEFAULT_SPARE1_PUSVERSION_SPARE2 0x10 | |
@@ -34,24 +30,13 | |||||
34 | #define DEFAULT_HKBIA 0x1e // 0001 1110 |
|
30 | #define DEFAULT_HKBIA 0x1e // 0001 1110 | |
35 |
|
31 | |||
36 | // PACKET ID |
|
32 | // PACKET ID | |
37 | #define TM_PACKET_PID_DEFAULT 76 |
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|||
38 | #define TM_PACKET_PID_BURST_SBM1_SBM2 79 |
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|||
39 | #define APID_TM_TC_EXE 0x0cc1 // PID 76 CAT 1 |
|
33 | #define APID_TM_TC_EXE 0x0cc1 // PID 76 CAT 1 | |
40 | #define APID_TM_HK 0x0cc4 // PID 76 CAT 4 |
|
34 | #define APID_TM_HK 0x0cc4 // PID 76 CAT 4 | |
41 | #define APID_TM_SCIENCE_NORMAL_BURST 0x0ccc // PID 76 CAT 12 |
|
35 | #define APID_TM_SCIENCE_NORMAL_BURST 0x0ccc // PID 76 CAT 12 | |
42 | #define APID_TM_SCIENCE_SBM1_SBM2 0x0cfc // PID 79 CAT 12 |
|
36 | #define APID_TM_SCIENCE_SBM1_SBM2 0x0cfc // PID 79 CAT 12 | |
43 | #define APID_TM_PARAMETER_DUMP 0x0cc6 // PID 76 CAT 6 |
|
37 | #define APID_TM_PARAMETER_DUMP 0x0cc6 // PID 76 CAT 6 | |
44 |
|
38 | |||
45 | // PACKET CAT |
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|||
46 | #define TM_PACKET_CAT_TC_EXE 1 |
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|||
47 | #define TM_PACKET_CAT_HK 4 |
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|||
48 | #define TM_PACKET_CAT_SCIENCE 12 |
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|||
49 | #define TM_PACKET_CAT_DUMP 6 |
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|||
50 |
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||||
51 | // PACKET SEQUENCE CONTROL |
|
39 | // PACKET SEQUENCE CONTROL | |
52 | #define TM_PACKET_SEQ_CTRL_CONTINUATION 0x00 // [0000 0000] |
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|||
53 | #define TM_PACKET_SEQ_CTRL_FIRST 0x40 // [0100 0000] |
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|||
54 | #define TM_PACKET_SEQ_CTRL_LAST 0x80 // [1000 0000] |
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|||
55 | #define TM_PACKET_SEQ_CTRL_STANDALONE 0xc0 // [1100 0000] |
|
40 | #define TM_PACKET_SEQ_CTRL_STANDALONE 0xc0 // [1100 0000] | |
56 | #define TM_PACKET_SEQ_CNT_DEFAULT 0x00 // [0000 0000] |
|
41 | #define TM_PACKET_SEQ_CNT_DEFAULT 0x00 // [0000 0000] | |
57 | #define TM_PACKET_SEQ_SHIFT 8 |
|
42 | #define TM_PACKET_SEQ_SHIFT 8 | |
@@ -61,16 +46,6 | |||||
61 |
|
46 | |||
62 | // DESTINATION ID |
|
47 | // DESTINATION ID | |
63 | #define TM_DESTINATION_ID_GROUND 0 |
|
48 | #define TM_DESTINATION_ID_GROUND 0 | |
64 | #define TM_DESTINATION_ID_MISSION_TIMELINE 110 |
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|||
65 | #define TM_DESTINATION_ID_TC_SEQUENCES 111 |
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|||
66 | #define TM_DESTINATION_ID_RECOVERY_ACTION_COMMAND 112 |
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|||
67 | #define TM_DESTINATION_ID_BACKUP_MISSION_TIMELINE 113 |
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|||
68 | #define TM_DESTINATION_ID_DIRECT_CMD 120 |
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|||
69 | #define TM_DESTINATION_ID_SPARE_GRD_SRC1 121 |
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|||
70 | #define TM_DESTINATION_ID_SPARE_GRD_SRC2 122 |
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|||
71 | #define TM_DESTINATION_ID_OBCP 15 |
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|||
72 | #define TM_DESTINATION_ID_SYSTEM_CONTROL 14 |
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|||
73 | #define TM_DESTINATION_ID_AOCS 11 |
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|||
74 |
|
49 | |||
75 | //********************************************************* |
|
50 | //********************************************************* | |
76 | //*** /!\ change CCSDS_DESTINATION_ID before flight /!\ *** |
|
51 | //*** /!\ change CCSDS_DESTINATION_ID before flight /!\ *** | |
@@ -84,10 +59,6 | |||||
84 | #define CCSDS_RESERVED 0x00 |
|
59 | #define CCSDS_RESERVED 0x00 | |
85 | #define CCSDS_USER_APP 0x00 |
|
60 | #define CCSDS_USER_APP 0x00 | |
86 |
|
61 | |||
87 | #define SIZE_TM_LFR_TC_EXE_NOT_IMPLEMENTED 24 |
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|||
88 | #define SIZE_TM_LFR_TC_EXE_CORRUPTED 32 |
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|||
89 | #define SIZE_HK_PARAMETERS 112 |
|
|||
90 |
|
||||
91 | // TC TYPES |
|
62 | // TC TYPES | |
92 | #define TC_TYPE_GEN 181 |
|
63 | #define TC_TYPE_GEN 181 | |
93 | #define TC_TYPE_TIME 9 |
|
64 | #define TC_TYPE_TIME 9 | |
@@ -158,7 +129,6 | |||||
158 | #define WRONG_SRC_ID 42001 // 0xa4 0x11 |
|
129 | #define WRONG_SRC_ID 42001 // 0xa4 0x11 | |
159 | #define FUNCT_NOT_IMPL 42002 // 0xa4 0x12 |
|
130 | #define FUNCT_NOT_IMPL 42002 // 0xa4 0x12 | |
160 | #define FAIL_DETECTED 42003 // 0xa4 0x13 |
|
131 | #define FAIL_DETECTED 42003 // 0xa4 0x13 | |
161 | #define NOT_ALLOWED 42004 // 0xa4 0x14 |
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|||
162 | #define CORRUPTED 42005 // 0xa4 0x15 |
|
132 | #define CORRUPTED 42005 // 0xa4 0x15 | |
163 | #define CCSDS_TM_VALID 7 |
|
133 | #define CCSDS_TM_VALID 7 | |
164 |
|
134 | |||
@@ -250,7 +220,6 enum apid_destid{ | |||||
250 | #define SID_K_DUMP 11 |
|
220 | #define SID_K_DUMP 11 | |
251 |
|
221 | |||
252 | // HEADER_LENGTH |
|
222 | // HEADER_LENGTH | |
253 | //#define TM_HEADER_LEN 16 |
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|||
254 | #define HEADER_LENGTH_TM_LFR_SCIENCE_CWF 32 |
|
223 | #define HEADER_LENGTH_TM_LFR_SCIENCE_CWF 32 | |
255 | #define HEADER_LENGTH_TM_LFR_SCIENCE_SWF 34 |
|
224 | #define HEADER_LENGTH_TM_LFR_SCIENCE_SWF 34 | |
256 | #define HEADER_LENGTH_TM_LFR_SCIENCE_ASM 34 |
|
225 | #define HEADER_LENGTH_TM_LFR_SCIENCE_ASM 34 | |
@@ -263,7 +232,6 enum apid_destid{ | |||||
263 | #define PACKET_LENGTH_TC_EXE_CORRUPTED (32 - CCSDS_TC_TM_PACKET_OFFSET) |
|
232 | #define PACKET_LENGTH_TC_EXE_CORRUPTED (32 - CCSDS_TC_TM_PACKET_OFFSET) | |
264 | #define PACKET_LENGTH_HK (136 - CCSDS_TC_TM_PACKET_OFFSET) |
|
233 | #define PACKET_LENGTH_HK (136 - CCSDS_TC_TM_PACKET_OFFSET) | |
265 | #define PACKET_LENGTH_PARAMETER_DUMP (212 - CCSDS_TC_TM_PACKET_OFFSET) |
|
234 | #define PACKET_LENGTH_PARAMETER_DUMP (212 - CCSDS_TC_TM_PACKET_OFFSET) | |
266 | #define PACKET_LENGTH_K_DUMP (3920 - CCSDS_TC_TM_PACKET_OFFSET) |
|
|||
267 | // SCIENCE ASM |
|
235 | // SCIENCE ASM | |
268 | #define PACKET_LENGTH_TM_LFR_SCIENCE_ASM_F0_1 (3230 - CCSDS_TC_TM_PACKET_OFFSET) // 32 * 25 * 4 + 30 => 32 bins (32 + 32 + 24 ), 3 packets |
|
236 | #define PACKET_LENGTH_TM_LFR_SCIENCE_ASM_F0_1 (3230 - CCSDS_TC_TM_PACKET_OFFSET) // 32 * 25 * 4 + 30 => 32 bins (32 + 32 + 24 ), 3 packets | |
269 | #define PACKET_LENGTH_TM_LFR_SCIENCE_ASM_F0_2 (2430 - CCSDS_TC_TM_PACKET_OFFSET) // 24 * 25 * 4 + 30 => 24 bins (32 + 32 + 24 ), 3 packets |
|
237 | #define PACKET_LENGTH_TM_LFR_SCIENCE_ASM_F0_2 (2430 - CCSDS_TC_TM_PACKET_OFFSET) // 24 * 25 * 4 + 30 => 24 bins (32 + 32 + 24 ), 3 packets | |
@@ -635,9 +603,7 typedef struct { | |||||
635 | #define STATUS_WORD_LINK_STATE_BITS 0x07 // [0000 0111] |
|
603 | #define STATUS_WORD_LINK_STATE_BITS 0x07 // [0000 0111] | |
636 | #define STATUS_WORD_LINK_STATE_MASK 0xf8 // [1111 1000] |
|
604 | #define STATUS_WORD_LINK_STATE_MASK 0xf8 // [1111 1000] | |
637 | #define STATUS_WORD_LFR_MODE_SHIFT 4 |
|
605 | #define STATUS_WORD_LFR_MODE_SHIFT 4 | |
638 | #define STATUS_WORD_LFR_MODE_BITS 0xf0 // [1111 0000] |
|
|||
639 | #define STATUS_WORD_LFR_MODE_MASK 0x0f // [0000 1111] |
|
606 | #define STATUS_WORD_LFR_MODE_MASK 0x0f // [0000 1111] | |
640 | #define STATUS_WORD_0_DEFAULT 0x0d // [0000 1101] |
|
|||
641 |
|
607 | |||
642 | typedef struct { |
|
608 | typedef struct { | |
643 | unsigned char targetLogicalAddress; |
|
609 | unsigned char targetLogicalAddress; |
@@ -8,7 +8,6 | |||||
8 | #include "stdint.h" |
|
8 | #include "stdint.h" | |
9 |
|
9 | |||
10 | #define GRSPW_DEVICE_NAME "/dev/grspw0" |
|
10 | #define GRSPW_DEVICE_NAME "/dev/grspw0" | |
11 | #define UART_DEVICE_NAME "/dev/console" |
|
|||
12 |
|
11 | |||
13 | //******* |
|
12 | //******* | |
14 | // MACROS |
|
13 | // MACROS | |
@@ -46,10 +45,10 | |||||
46 | #define CONST_2048 2048 // 2^11 |
|
45 | #define CONST_2048 2048 // 2^11 | |
47 | #define CONST_512 512 // 2^9 |
|
46 | #define CONST_512 512 // 2^9 | |
48 | #define CONST_256 256 // 2^8 |
|
47 | #define CONST_256 256 // 2^8 | |
49 | #define CONST_128 128 // 2^7 |
|
48 | #ifndef UINT8_MAX | |
50 | #define UINT8_MAX 255 |
|
49 | #define UINT8_MAX 255 | |
|
50 | #endif | |||
51 |
|
51 | |||
52 | #define FLOAT_MSBYTE 0 |
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|||
53 | #define FLOAT_LSBYTE 3 |
|
52 | #define FLOAT_LSBYTE 3 | |
54 | #define BITS_PER_BYTE 8 |
|
53 | #define BITS_PER_BYTE 8 | |
55 | #define INIT_FLOAT 0. |
|
54 | #define INIT_FLOAT 0. | |
@@ -68,7 +67,6 | |||||
68 | #define SHIFT_3_BITS 3 |
|
67 | #define SHIFT_3_BITS 3 | |
69 | #define SHIFT_4_BITS 4 |
|
68 | #define SHIFT_4_BITS 4 | |
70 | #define SHIFT_5_BITS 5 |
|
69 | #define SHIFT_5_BITS 5 | |
71 | #define SHIFT_6_BITS 6 |
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|||
72 | #define SHIFT_7_BITS 7 |
|
70 | #define SHIFT_7_BITS 7 | |
73 | #define BYTE_0 0 |
|
71 | #define BYTE_0 0 | |
74 | #define BYTE_1 1 |
|
72 | #define BYTE_1 1 | |
@@ -110,7 +108,6 typedef struct ring_node | |||||
110 | #define NB_PACKETS_PER_GROUP_OF_CWF_LIGHT 4 // 4 packets containing 672 blk |
|
108 | #define NB_PACKETS_PER_GROUP_OF_CWF_LIGHT 4 // 4 packets containing 672 blk | |
111 | #define NB_SAMPLES_PER_SNAPSHOT 2688 // 336 * 8 = 672 * 4 = 2688 |
|
109 | #define NB_SAMPLES_PER_SNAPSHOT 2688 // 336 * 8 = 672 * 4 = 2688 | |
112 | #define TIME_OFFSET 2 |
|
110 | #define TIME_OFFSET 2 | |
113 | #define TIME_OFFSET_IN_BYTES 8 |
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|||
114 | #define NB_BYTES_SWF_BLK (2 * 6) |
|
111 | #define NB_BYTES_SWF_BLK (2 * 6) | |
115 | #define NB_WORDS_SWF_BLK 3 |
|
112 | #define NB_WORDS_SWF_BLK 3 | |
116 | #define NB_BYTES_CWF3_LIGHT_BLK 6 |
|
113 | #define NB_BYTES_CWF3_LIGHT_BLK 6 | |
@@ -138,10 +135,8 typedef struct ring_node | |||||
138 | #define THR_MODE_NORMAL 1 |
|
135 | #define THR_MODE_NORMAL 1 | |
139 | #define THR_MODE_BURST 2 |
|
136 | #define THR_MODE_BURST 2 | |
140 |
|
137 | |||
141 | #define RTEMS_EVENT_MODE_STANDBY RTEMS_EVENT_0 |
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|||
142 | #define RTEMS_EVENT_MODE_NORMAL RTEMS_EVENT_1 |
|
138 | #define RTEMS_EVENT_MODE_NORMAL RTEMS_EVENT_1 | |
143 | #define RTEMS_EVENT_MODE_BURST RTEMS_EVENT_2 |
|
139 | #define RTEMS_EVENT_MODE_BURST RTEMS_EVENT_2 | |
144 | #define RTEMS_EVENT_MODE_SBM1 RTEMS_EVENT_3 |
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|||
145 | #define RTEMS_EVENT_MODE_SBM2 RTEMS_EVENT_4 |
|
140 | #define RTEMS_EVENT_MODE_SBM2 RTEMS_EVENT_4 | |
146 | #define RTEMS_EVENT_MODE_NORM_S1_S2 RTEMS_EVENT_5 |
|
141 | #define RTEMS_EVENT_MODE_NORM_S1_S2 RTEMS_EVENT_5 | |
147 | #define RTEMS_EVENT_NORM_BP1_F0 RTEMS_EVENT_6 |
|
142 | #define RTEMS_EVENT_NORM_BP1_F0 RTEMS_EVENT_6 | |
@@ -182,7 +177,6 typedef struct ring_node | |||||
182 | #define DFLT_SY_LFR_N_BP_P0 4 // sec |
|
177 | #define DFLT_SY_LFR_N_BP_P0 4 // sec | |
183 | #define DFLT_SY_LFR_N_BP_P1 20 // sec |
|
178 | #define DFLT_SY_LFR_N_BP_P1 20 // sec | |
184 | #define DFLT_SY_LFR_N_CWF_LONG_F3 0 // 0 => production of light continuous waveforms at f3 |
|
179 | #define DFLT_SY_LFR_N_CWF_LONG_F3 0 // 0 => production of light continuous waveforms at f3 | |
185 | #define MIN_DELTA_SNAPSHOT 16 // sec |
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|||
186 |
|
180 | |||
187 | // BURST |
|
181 | // BURST | |
188 | #define DEFAULT_SY_LFR_B_BP_P0 1 // sec |
|
182 | #define DEFAULT_SY_LFR_B_BP_P0 1 // sec | |
@@ -197,10 +191,6 typedef struct ring_node | |||||
197 | #define DEFAULT_SY_LFR_S2_BP_P0 1 // sec |
|
191 | #define DEFAULT_SY_LFR_S2_BP_P0 1 // sec | |
198 | #define DEFAULT_SY_LFR_S2_BP_P1 5 // sec |
|
192 | #define DEFAULT_SY_LFR_S2_BP_P1 5 // sec | |
199 |
|
193 | |||
200 | // ADDITIONAL PARAMETERS |
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|||
201 | #define TIME_BETWEEN_TWO_SWF_PACKETS 30 // nb x 10 ms => 300 ms |
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|||
202 | #define TIME_BETWEEN_TWO_CWF3_PACKETS 1000 // nb x 10 ms => 10 s |
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|||
203 |
|
||||
204 | // STATUS WORD |
|
194 | // STATUS WORD | |
205 | #define DEFAULT_STATUS_WORD_BYTE0 0x0d // [0000] [1] [101] mode 4 bits / SPW enabled 1 bit / state is run 3 bits |
|
195 | #define DEFAULT_STATUS_WORD_BYTE0 0x0d // [0000] [1] [101] mode 4 bits / SPW enabled 1 bit / state is run 3 bits | |
206 |
|
196 | |||
@@ -215,7 +205,6 typedef struct ring_node | |||||
215 | #define MIN_PAS_FILTER_SHIFT 0.0 |
|
205 | #define MIN_PAS_FILTER_SHIFT 0.0 | |
216 | #define MAX_PAS_FILTER_SHIFT 1.0 |
|
206 | #define MAX_PAS_FILTER_SHIFT 1.0 | |
217 | #define MIN_SY_LFR_SC_RW_DELTA_F 0 |
|
207 | #define MIN_SY_LFR_SC_RW_DELTA_F 0 | |
218 | #define MIN_SY_LFR_RW_K 0 |
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|||
219 | #define MIN_SY_LFR_RW_F 0 |
|
208 | #define MIN_SY_LFR_RW_F 0 | |
220 | // |
|
209 | // | |
221 | #define SY_LFR_DPU_CONNECT_TIMEOUT 100 // 100 * 10 ms = 1 s |
|
210 | #define SY_LFR_DPU_CONNECT_TIMEOUT 100 // 100 * 10 ms = 1 s | |
@@ -230,7 +219,6 typedef struct ring_node | |||||
230 | #define APB_OFFSET_GRSPW_STATUS_REGISTER 0x04 |
|
219 | #define APB_OFFSET_GRSPW_STATUS_REGISTER 0x04 | |
231 | #define APB_OFFSET_GRSPW_TIME_REGISTER 0x14 |
|
220 | #define APB_OFFSET_GRSPW_TIME_REGISTER 0x14 | |
232 | #define REGS_ADDR_TIME_MANAGEMENT 0x80000600 |
|
221 | #define REGS_ADDR_TIME_MANAGEMENT 0x80000600 | |
233 | #define REGS_ADDR_GRGPIO 0x80000b00 |
|
|||
234 |
|
222 | |||
235 | #define REGS_ADDR_SPECTRAL_MATRIX 0x80000f00 |
|
223 | #define REGS_ADDR_SPECTRAL_MATRIX 0x80000f00 | |
236 | #define REGS_ADDR_WAVEFORM_PICKER 0x80000f54 // PDB >= 0.1.28 |
|
224 | #define REGS_ADDR_WAVEFORM_PICKER 0x80000f54 // PDB >= 0.1.28 | |
@@ -269,7 +257,6 typedef struct ring_node | |||||
269 | #define LFR_SUCCESSFUL 0 |
|
257 | #define LFR_SUCCESSFUL 0 | |
270 | #define LFR_DEFAULT 1 |
|
258 | #define LFR_DEFAULT 1 | |
271 | #define LFR_EXE_ERROR 2 |
|
259 | #define LFR_EXE_ERROR 2 | |
272 | #define LFR_DEFAULT_ALT -1 |
|
|||
273 |
|
260 | |||
274 | //****** |
|
261 | //****** | |
275 | // RTEMS |
|
262 | // RTEMS | |
@@ -336,9 +323,6 typedef struct ring_node | |||||
336 | #define QUEUE_PRC0 2 |
|
323 | #define QUEUE_PRC0 2 | |
337 | #define QUEUE_PRC1 3 |
|
324 | #define QUEUE_PRC1 3 | |
338 | #define QUEUE_PRC2 4 |
|
325 | #define QUEUE_PRC2 4 | |
339 | #define QUEUE_CALI 5 |
|
|||
340 |
|
||||
341 | #define CPU_USAGE_REPORT_PERIOD 6 // * 10 s = period |
|
|||
342 |
|
326 | |||
343 | struct param_local_str{ |
|
327 | struct param_local_str{ | |
344 | unsigned int local_sbm1_nb_cwf_sent; |
|
328 | unsigned int local_sbm1_nb_cwf_sent; |
@@ -71,7 +71,6 | |||||
71 | // TC_LFR_LOAD_FILTER_PAR |
|
71 | // TC_LFR_LOAD_FILTER_PAR | |
72 | #define NB_RW_K_COEFFS 16 |
|
72 | #define NB_RW_K_COEFFS 16 | |
73 | #define NB_BYTES_PER_RW_K_COEFF 4 |
|
73 | #define NB_BYTES_PER_RW_K_COEFF 4 | |
74 | #define DATAFIELD_POS_PA_RPW_SPARE8_2 0 // 8 bits |
|
|||
75 | #define DATAFIELD_POS_SY_LFR_PAS_FILTER_ENABLED 1 // 8 bits |
|
74 | #define DATAFIELD_POS_SY_LFR_PAS_FILTER_ENABLED 1 // 8 bits | |
76 | #define DATAFIELD_POS_SY_LFR_PAS_FILTER_MODULUS 2 // 8 bits |
|
75 | #define DATAFIELD_POS_SY_LFR_PAS_FILTER_MODULUS 2 // 8 bits | |
77 | #define DATAFIELD_POS_SY_LFR_PAS_FILTER_TBAD 3 // 32 bits |
|
76 | #define DATAFIELD_POS_SY_LFR_PAS_FILTER_TBAD 3 // 32 bits |
@@ -8,7 +8,6 | |||||
8 |
|
8 | |||
9 | #define NB_SM_PER_S_F0 96 |
|
9 | #define NB_SM_PER_S_F0 96 | |
10 | #define NB_SM_PER_S_F1 16 |
|
10 | #define NB_SM_PER_S_F1 16 | |
11 | #define NB_SM_PER_S_F2 1 |
|
|||
12 | #define NB_SM_PER_S1_BP_P0 24 |
|
11 | #define NB_SM_PER_S1_BP_P0 24 | |
13 |
|
12 | |||
14 | #define ASM_COMP_B1B2 1 |
|
13 | #define ASM_COMP_B1B2 1 | |
@@ -31,10 +30,6 | |||||
31 | #define NB_BINS_PER_SM 128 |
|
30 | #define NB_BINS_PER_SM 128 | |
32 | #define NB_VALUES_PER_SM 25 |
|
31 | #define NB_VALUES_PER_SM 25 | |
33 | #define TOTAL_SIZE_SM 3200 // 25 * 128 = 0xC80 |
|
32 | #define TOTAL_SIZE_SM 3200 // 25 * 128 = 0xC80 | |
34 | #define TOTAL_SIZE_NORM_BP1_F0 99 // 11 * 9 = 99 |
|
|||
35 | #define TOTAL_SIZE_NORM_BP1_F1 117 // 13 * 9 = 117 |
|
|||
36 | #define TOTAL_SIZE_NORM_BP1_F2 108 // 12 * 9 = 108 |
|
|||
37 | #define TOTAL_SIZE_SBM1_BP1_F0 198 // 22 * 9 = 198 |
|
|||
38 | // F0 |
|
33 | // F0 | |
39 | #define NB_RING_NODES_SM_F0 20 // AT LEAST 8 due to the way the averaging is done |
|
34 | #define NB_RING_NODES_SM_F0 20 // AT LEAST 8 due to the way the averaging is done | |
40 | #define NB_RING_NODES_ASM_BURST_SBM_F0 10 // AT LEAST 3 |
|
35 | #define NB_RING_NODES_ASM_BURST_SBM_F0 10 // AT LEAST 3 | |
@@ -50,21 +45,18 | |||||
50 | #define NB_RING_NODES_ASM_NORM_F2 3 // AT LEAST 3 |
|
45 | #define NB_RING_NODES_ASM_NORM_F2 3 // AT LEAST 3 | |
51 | #define NB_RING_NODES_ASM_F2 3 // AT LEAST 3 |
|
46 | #define NB_RING_NODES_ASM_F2 3 // AT LEAST 3 | |
52 | // |
|
47 | // | |
53 | #define NB_BINS_PER_ASM_F0 88 |
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54 | #define NB_BINS_PER_PKT_ASM_F0_1 32 |
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48 | #define NB_BINS_PER_PKT_ASM_F0_1 32 | |
55 | #define NB_BINS_PER_PKT_ASM_F0_2 24 |
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49 | #define NB_BINS_PER_PKT_ASM_F0_2 24 | |
56 | #define DLEN_ASM_F0_PKT_1 3200 // 32 * 25 * 4, 25 components per matrix, 4 bytes per float |
|
50 | #define DLEN_ASM_F0_PKT_1 3200 // 32 * 25 * 4, 25 components per matrix, 4 bytes per float | |
57 | #define DLEN_ASM_F0_PKT_2 2400 // 24 * 25 * 4, 25 components per matrix, 4 bytes per float |
|
51 | #define DLEN_ASM_F0_PKT_2 2400 // 24 * 25 * 4, 25 components per matrix, 4 bytes per float | |
58 | #define ASM_F0_INDICE_START 16 // 17 - 1, (-1) due to the VHDL behaviour |
|
52 | #define ASM_F0_INDICE_START 16 // 17 - 1, (-1) due to the VHDL behaviour | |
59 | // |
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53 | // | |
60 | #define NB_BINS_PER_ASM_F1 104 |
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61 | #define NB_BINS_PER_PKT_ASM_F1_1 36 |
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54 | #define NB_BINS_PER_PKT_ASM_F1_1 36 | |
62 | #define NB_BINS_PER_PKT_ASM_F1_2 32 |
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55 | #define NB_BINS_PER_PKT_ASM_F1_2 32 | |
63 | #define DLEN_ASM_F1_PKT_1 3600 // 36 * 25 * 4, 25 components per matrix, 4 bytes per float |
|
56 | #define DLEN_ASM_F1_PKT_1 3600 // 36 * 25 * 4, 25 components per matrix, 4 bytes per float | |
64 | #define DLEN_ASM_F1_PKT_2 3200 // 32 * 25 * 4, 25 components per matrix, 4 bytes per float |
|
57 | #define DLEN_ASM_F1_PKT_2 3200 // 32 * 25 * 4, 25 components per matrix, 4 bytes per float | |
65 | #define ASM_F1_INDICE_START 5 // 6 - 1, (-1) due to the VHDL behaviour |
|
58 | #define ASM_F1_INDICE_START 5 // 6 - 1, (-1) due to the VHDL behaviour | |
66 | // |
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59 | // | |
67 | #define NB_BINS_PER_ASM_F2 96 |
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68 | #define NB_BINS_PER_PKT_ASM_F2 32 |
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60 | #define NB_BINS_PER_PKT_ASM_F2 32 | |
69 | #define DLEN_ASM_F2_PKT 3200 // 32 * 25 * 4, 25 components per matrix, 4 bytes per float |
|
61 | #define DLEN_ASM_F2_PKT 3200 // 32 * 25 * 4, 25 components per matrix, 4 bytes per float | |
70 | #define ASM_F2_INDICE_START 6 // 7 - 1, (-1) due to the VHDL behaviour |
|
62 | #define ASM_F2_INDICE_START 6 // 7 - 1, (-1) due to the VHDL behaviour | |
@@ -77,26 +69,18 | |||||
77 | #define NB_BINS_COMPRESSED_SM 36 // 11 + 12 + 13 |
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69 | #define NB_BINS_COMPRESSED_SM 36 // 11 + 12 + 13 | |
78 | #define NB_BINS_COMPRESSED_SM_SBM_F0 22 |
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70 | #define NB_BINS_COMPRESSED_SM_SBM_F0 22 | |
79 | #define NB_BINS_COMPRESSED_SM_SBM_F1 26 |
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71 | #define NB_BINS_COMPRESSED_SM_SBM_F1 26 | |
80 | #define NB_BINS_COMPRESSED_SM_SBM_F2 24 |
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81 | // |
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82 | #define NB_BYTES_PER_BP1 9 |
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83 | #define NB_BYTES_PER_BP2 30 |
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84 | // |
|
72 | // | |
85 | #define NB_BINS_TO_AVERAGE_ASM_F0 8 |
|
73 | #define NB_BINS_TO_AVERAGE_ASM_F0 8 | |
86 | #define NB_BINS_TO_AVERAGE_ASM_F1 8 |
|
74 | #define NB_BINS_TO_AVERAGE_ASM_F1 8 | |
87 | #define NB_BINS_TO_AVERAGE_ASM_F2 8 |
|
75 | #define NB_BINS_TO_AVERAGE_ASM_F2 8 | |
88 | #define NB_BINS_TO_AVERAGE_ASM_SBM_F0 4 |
|
76 | #define NB_BINS_TO_AVERAGE_ASM_SBM_F0 4 | |
89 | #define NB_BINS_TO_AVERAGE_ASM_SBM_F1 4 |
|
77 | #define NB_BINS_TO_AVERAGE_ASM_SBM_F1 4 | |
90 | #define NB_BINS_TO_AVERAGE_ASM_SBM_F2 4 |
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91 | // |
|
78 | // | |
92 | #define TOTAL_SIZE_COMPRESSED_ASM_NORM_F0 275 // 11 * 25 WORDS |
|
79 | #define TOTAL_SIZE_COMPRESSED_ASM_NORM_F0 275 // 11 * 25 WORDS | |
93 | #define TOTAL_SIZE_COMPRESSED_ASM_NORM_F1 325 // 13 * 25 WORDS |
|
80 | #define TOTAL_SIZE_COMPRESSED_ASM_NORM_F1 325 // 13 * 25 WORDS | |
94 | #define TOTAL_SIZE_COMPRESSED_ASM_NORM_F2 300 // 12 * 25 WORDS |
|
81 | #define TOTAL_SIZE_COMPRESSED_ASM_NORM_F2 300 // 12 * 25 WORDS | |
95 | #define TOTAL_SIZE_COMPRESSED_ASM_SBM_F0 550 // 22 * 25 WORDS |
|
82 | #define TOTAL_SIZE_COMPRESSED_ASM_SBM_F0 550 // 22 * 25 WORDS | |
96 | #define TOTAL_SIZE_COMPRESSED_ASM_SBM_F1 650 // 26 * 25 WORDS |
|
83 | #define TOTAL_SIZE_COMPRESSED_ASM_SBM_F1 650 // 26 * 25 WORDS | |
97 | #define TOTAL_SIZE_BP1_NORM_F0 99 // 9 * 11 UNSIGNED CHAR |
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98 | #define TOTAL_SIZE_BP2_NORM_F0 330 // 30 * 11 UNSIGNED CHAR |
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99 | #define TOTAL_SIZE_BP1_SBM_F0 198 // 9 * 22 UNSIGNED CHAR |
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100 | // GENERAL |
|
84 | // GENERAL | |
101 | #define NB_SM_BEFORE_AVF0_F1 8 // must be 8 due to the SM_average() function |
|
85 | #define NB_SM_BEFORE_AVF0_F1 8 // must be 8 due to the SM_average() function | |
102 | #define NB_SM_BEFORE_AVF2 1 // must be 1 due to the SM_average_f2() function |
|
86 | #define NB_SM_BEFORE_AVF2 1 // must be 1 due to the SM_average_f2() function |
@@ -1,14 +1,7 | |||||
1 | #ifndef TM_BYTE_POSITIONS_H |
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1 | #ifndef TM_BYTE_POSITIONS_H | |
2 | #define TM_BYTE_POSITIONS_H |
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2 | #define TM_BYTE_POSITIONS_H | |
3 |
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3 | |||
4 | #define BYTE_POS_CP_LFR_MODE 11 |
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5 |
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6 | // TC_LFR_LOAD_NORMAL_PAR |
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4 | // TC_LFR_LOAD_NORMAL_PAR | |
7 | #define BYTE_POS_SY_LFR_N_SWF_L 0 |
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8 | #define BYTE_POS_SY_LFR_N_SWF_P 2 |
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9 | #define BYTE_POS_SY_LFR_N_ASM_P 4 |
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10 | #define BYTE_POS_SY_LFR_N_BP_P0 6 |
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11 | #define BYTE_POS_SY_LFR_N_BP_P1 7 |
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12 | #define BYTE_POS_SY_LFR_N_CWF_LONG_F3 8 |
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5 | #define BYTE_POS_SY_LFR_N_CWF_LONG_F3 8 | |
13 |
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6 | |||
14 | // TM_LFR_HK |
|
7 | // TM_LFR_HK |
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