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MOved RTEMS config in fsw_params.h
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1 1 #ifndef FSW_PARAMS_H_INCLUDED
2 2 #define FSW_PARAMS_H_INCLUDED
3 3
4 4 #include "fsw_params_processing.h"
5 5 #include "fsw_params_nb_bytes.h"
6 6 #include "tm_byte_positions.h"
7 7 #include "ccsds_types.h"
8 8 #include "stdint.h"
9 9
10 /*
11 * RTEMS CONFIG
12 *
13 */
10 14 #define GRSPW_DEVICE_NAME "/dev/grspw0"
11 15
16 #define CONFIGURE_APPLICATION_NEEDS_CONSOLE_DRIVER
17 #define CONFIGURE_APPLICATION_NEEDS_CLOCK_DRIVER
18
19 #define CONFIGURE_MAXIMUM_TASKS 23 // number of tasks concurrently active including INIT
20 #define CONFIGURE_RTEMS_INIT_TASKS_TABLE
21 #define CONFIGURE_EXTRA_TASK_STACKS (3 * RTEMS_MINIMUM_STACK_SIZE)
22 #define CONFIGURE_LIBIO_MAXIMUM_FILE_DESCRIPTORS 32
23 #define CONFIGURE_INIT_TASK_PRIORITY 1 // instead of 100
24 #define CONFIGURE_INIT_TASK_MODE (RTEMS_DEFAULT_MODES | RTEMS_NO_PREEMPT)
25 #define CONFIGURE_INIT_TASK_ATTRIBUTES (RTEMS_DEFAULT_ATTRIBUTES | RTEMS_FLOATING_POINT)
26 #define CONFIGURE_MAXIMUM_DRIVERS 16
27 #define CONFIGURE_MAXIMUM_PERIODS 6 // [hous] [load] [avgv]
28 #define CONFIGURE_MAXIMUM_TIMERS 6 // [spiq] [link] [spacewire_reset_link]
29 #define CONFIGURE_MAXIMUM_MESSAGE_QUEUES 5
30 #ifdef PRINT_STACK_REPORT
31 #define CONFIGURE_STACK_CHECKER_ENABLED
32 #endif
33
34
12 35 //*******
13 36 // MACROS
14 37 #ifdef PRINT_MESSAGES_ON_CONSOLE
15 38 #define PRINTF(x) printf(x);
16 39 #define PRINTF1(x,y) printf(x,y);
17 40 #define PRINTF2(x,y,z) printf(x,y,z);
18 41 #else
19 42 #define PRINTF(x) ;
20 43 #define PRINTF1(x,y) ;
21 44 #define PRINTF2(x,y,z) ;
22 45 #endif
23 46
24 47 #ifdef BOOT_MESSAGES
25 48 #define BOOT_PRINTF(x) printf(x);
26 49 #define BOOT_PRINTF1(x,y) printf(x,y);
27 50 #define BOOT_PRINTF2(x,y,z) printf(x,y,z);
28 51 #else
29 52 #define BOOT_PRINTF(x) ;
30 53 #define BOOT_PRINTF1(x,y) ;
31 54 #define BOOT_PRINTF2(x,y,z) ;
32 55 #endif
33 56
34 57 #ifdef DEBUG_MESSAGES
35 58 #define DEBUG_PRINTF(x) printf(x);
36 59 #define DEBUG_PRINTF1(x,y) printf(x,y);
37 60 #define DEBUG_PRINTF2(x,y,z) printf(x,y,z);
38 61 #else
39 62 #define DEBUG_PRINTF(x) ;
40 63 #define DEBUG_PRINTF1(x,y) ;
41 64 #define DEBUG_PRINTF2(x,y,z) ;
42 65 #endif
43 66
44 67 #define CONST_65536 65536 // 2^16
45 68 #define CONST_2048 2048 // 2^11
46 69 #define CONST_512 512 // 2^9
47 70 #define CONST_256 256 // 2^8
48 71 #ifndef UINT8_MAX
49 72 #define UINT8_MAX 255
50 73 #endif
51 74
52 75 #define FLOAT_LSBYTE 3
53 76 #define BITS_PER_BYTE 8
54 77 #define INIT_FLOAT 0.
55 78 #define INIT_CHAR 0x00
56 79 #define INIT_INT 0
57 80 #define INT8_ALL_F 0xff
58 81 #define INT16_ALL_F 0xffff
59 82 #define INT32_ALL_F 0xffffffff
60 83 #define INT32_ALL_0 0x00000000
61 84 #define SHIFT_1_BYTE 8
62 85 #define SHIFT_2_BYTES 16
63 86 #define SHIFT_3_BYTES 24
64 87 #define SHIFT_4_BYTES 32
65 88 #define SHIFT_5_BYTES 40
66 89 #define SHIFT_2_BITS 2
67 90 #define SHIFT_3_BITS 3
68 91 #define SHIFT_4_BITS 4
69 92 #define SHIFT_5_BITS 5
70 93 #define SHIFT_7_BITS 7
71 94 #define BYTE_0 0
72 95 #define BYTE_1 1
73 96 #define BYTE_2 2
74 97 #define BYTE_3 3
75 98 #define BYTE_4 4
76 99 #define BYTE_5 5
77 100 #define BYTE_6 6
78 101 #define BYTE_7 7
79 102 #define BYTE0_MASK 0xff00
80 103 #define BYTE1_MASK 0x00ff
81 104
82 105 enum lfr_transition_type_t{
83 106 TRANSITION_NOT_SPECIFIC,
84 107 TRANSITION_NORM_TO_S1,
85 108 TRANSITION_NORM_TO_S2,
86 109 TRANSITION_S1_TO_NORM,
87 110 TRANSITION_S2_TO_NORM,
88 111 TRANSITION_S1_TO_S2,
89 112 TRANSITION_S2_TO_S1
90 113 };
91 114
92 115 typedef struct ring_node
93 116 {
94 117 struct ring_node *previous;
95 118 struct ring_node *next;
96 119 unsigned int sid;
97 120 unsigned int coarseTime;
98 121 unsigned int fineTime;
99 122 int buffer_address;
100 123 unsigned int status;
101 124 } ring_node;
102 125
103 126 //************************
104 127 // flight software version
105 128 // this parameters is handled by the Qt project options
106 129
107 130 #define NB_PACKETS_PER_GROUP_OF_CWF 8 // 8 packets containing 336 blk
108 131 #define NB_PACKETS_PER_GROUP_OF_CWF_LIGHT 4 // 4 packets containing 672 blk
109 132 #define NB_SAMPLES_PER_SNAPSHOT 2688 // 336 * 8 = 672 * 4 = 2688
110 133 #define TIME_OFFSET 2
111 134 #define NB_BYTES_SWF_BLK (2 * 6)
112 135 #define NB_WORDS_SWF_BLK 3
113 136 #define NB_BYTES_CWF3_LIGHT_BLK 6
114 137 #define NB_RING_NODES_F0 3 // AT LEAST 3
115 138 #define NB_RING_NODES_F1 5 // AT LEAST 3
116 139 #define NB_RING_NODES_F2 5 // AT LEAST 3
117 140 #define NB_RING_NODES_F3 3 // AT LEAST 3
118 141
119 142 //**********
120 143 // LFR MODES
121 144 #define LFR_MODE_STANDBY 0
122 145 #define LFR_MODE_NORMAL 1
123 146 #define LFR_MODE_BURST 2
124 147 #define LFR_MODE_SBM1 3
125 148 #define LFR_MODE_SBM2 4
126 149
127 150 #define TDS_MODE_LFM 5
128 151 #define TDS_MODE_STANDBY 0
129 152 #define TDS_MODE_NORMAL 1
130 153 #define TDS_MODE_BURST 2
131 154 #define TDS_MODE_SBM1 3
132 155 #define TDS_MODE_SBM2 4
133 156
134 157 #define THR_MODE_STANDBY 0
135 158 #define THR_MODE_NORMAL 1
136 159 #define THR_MODE_BURST 2
137 160
138 161 #define RTEMS_EVENT_MODE_NORMAL RTEMS_EVENT_1
139 162 #define RTEMS_EVENT_MODE_BURST RTEMS_EVENT_2
140 163 #define RTEMS_EVENT_MODE_SBM2 RTEMS_EVENT_4
141 164 #define RTEMS_EVENT_MODE_NORM_S1_S2 RTEMS_EVENT_5
142 165 #define RTEMS_EVENT_NORM_BP1_F0 RTEMS_EVENT_6
143 166 #define RTEMS_EVENT_NORM_BP2_F0 RTEMS_EVENT_7
144 167 #define RTEMS_EVENT_NORM_ASM_F0 RTEMS_EVENT_8 // ASM only in NORM mode
145 168 #define RTEMS_EVENT_NORM_BP1_F1 RTEMS_EVENT_9
146 169 #define RTEMS_EVENT_NORM_BP2_F1 RTEMS_EVENT_10
147 170 #define RTEMS_EVENT_NORM_ASM_F1 RTEMS_EVENT_11 // ASM only in NORM mode
148 171 #define RTEMS_EVENT_NORM_BP1_F2 RTEMS_EVENT_12
149 172 #define RTEMS_EVENT_NORM_BP2_F2 RTEMS_EVENT_13
150 173 #define RTEMS_EVENT_NORM_ASM_F2 RTEMS_EVENT_14 // ASM only in NORM mode
151 174 #define RTEMS_EVENT_SBM_BP1_F0 RTEMS_EVENT_15
152 175 #define RTEMS_EVENT_SBM_BP2_F0 RTEMS_EVENT_16
153 176 #define RTEMS_EVENT_SBM_BP1_F1 RTEMS_EVENT_17
154 177 #define RTEMS_EVENT_SBM_BP2_F1 RTEMS_EVENT_18
155 178 #define RTEMS_EVENT_BURST_BP1_F0 RTEMS_EVENT_19
156 179 #define RTEMS_EVENT_BURST_BP2_F0 RTEMS_EVENT_20
157 180 #define RTEMS_EVENT_BURST_BP1_F1 RTEMS_EVENT_21
158 181 #define RTEMS_EVENT_BURST_BP2_F1 RTEMS_EVENT_22
159 182 #define RTEMS_EVENT_SWF_RESYNCH RTEMS_EVENT_23
160 183 #define RTEMS_EVENT_CAL_SWEEP_WAKE RTEMS_EVENT_24
161 184
162 185 //********************************************
163 186 //********************************************
164 187 // LFR PARAMETERS: DEFAULT, MIN AND MAX VALUES
165 188
166 189 #define DEFAULT_LAST_VALID_TRANSITION_DATE 0xffffffff
167 190
168 191 // COMMON
169 192 #define DEFAULT_SY_LFR_COMMON0 0x00
170 193 #define DEFAULT_SY_LFR_COMMON1 0x20 // default value bw sp0 sp1 r0 r1 r2 = 1 0 0 0 0 0
171 194
172 195 // NORM
173 196 #define DFLT_SY_LFR_N_SWF_L 2048 // nb sample
174 197 #define DFLT_SY_LFR_N_SWF_P 300 // sec
175 198 #define MIN_SY_LFR_N_SWF_P 22 // sec
176 199 #define DFLT_SY_LFR_N_ASM_P 3600 // sec
177 200 #define DFLT_SY_LFR_N_BP_P0 4 // sec
178 201 #define DFLT_SY_LFR_N_BP_P1 20 // sec
179 202 #define DFLT_SY_LFR_N_CWF_LONG_F3 0 // 0 => production of light continuous waveforms at f3
180 203
181 204 // BURST
182 205 #define DEFAULT_SY_LFR_B_BP_P0 1 // sec
183 206 #define DEFAULT_SY_LFR_B_BP_P1 5 // sec
184 207
185 208 // SBM1
186 209 #define S1_BP_P0_SCALE 0.25
187 210 #define DEFAULT_SY_LFR_S1_BP_P0 1 // 0.25 sec
188 211 #define DEFAULT_SY_LFR_S1_BP_P1 1 // sec
189 212
190 213 // SBM2
191 214 #define DEFAULT_SY_LFR_S2_BP_P0 1 // sec
192 215 #define DEFAULT_SY_LFR_S2_BP_P1 5 // sec
193 216
194 217 // STATUS WORD
195 218 #define DEFAULT_STATUS_WORD_BYTE0 0x0d // [0000] [1] [101] mode 4 bits / SPW enabled 1 bit / state is run 3 bits
196 219
197 220 #define DEFAULT_STATUS_WORD_BYTE1 0x00
198 221 // TC_LFR_LOAD_FILTER_PAR
199 222 #define MIN_PAS_FILTER_MODULUS 4
200 223 #define MAX_PAS_FILTER_MODULUS 8
201 224 #define MIN_PAS_FILTER_TBAD 0.0
202 225 #define MAX_PAS_FILTER_TBAD 4.0
203 226 #define MIN_PAS_FILTER_OFFSET 0
204 227 #define MAX_PAS_FILTER_OFFSET 7
205 228 #define MIN_PAS_FILTER_SHIFT 0.0
206 229 #define MAX_PAS_FILTER_SHIFT 1.0
207 230 #define MIN_SY_LFR_SC_RW_DELTA_F 0
208 231 #define MIN_SY_LFR_RW_F 0
209 232 //
210 233 #define SY_LFR_DPU_CONNECT_TIMEOUT 100 // 100 * 10 ms = 1 s
211 234 #define SY_LFR_DPU_CONNECT_ATTEMPT 3
212 235 //****************************
213 236
214 237 //*****************************
215 238 // APB REGISTERS BASE ADDRESSES
216 239 #define REGS_ADDR_APBUART 0x80000100
217 240 #define REGS_ADDR_GPTIMER 0x80000300
218 241 #define REGS_ADDR_GRSPW 0x80000500
219 242 #define APB_OFFSET_GRSPW_STATUS_REGISTER 0x04
220 243 #define APB_OFFSET_GRSPW_TIME_REGISTER 0x14
221 244 #define REGS_ADDR_TIME_MANAGEMENT 0x80000600
222 245
223 246 #define REGS_ADDR_SPECTRAL_MATRIX 0x80000f00
224 247 #define REGS_ADDR_WAVEFORM_PICKER 0x80000f54 // PDB >= 0.1.28
225 248 #define APB_OFFSET_VHDL_REV 0xb0
226 249 #define REGS_ADDR_VHDL_VERSION 0x80000ff0
227 250
228 251 #define APBUART_CTRL_REG_MASK_TE 0x00000002
229 252 // scaler value = system_clock_frequency / ( baud_rate * 8 ) - 1
230 253 #define APBUART_SCALER_RELOAD_VALUE 0x00000050 // 25 MHz => about 38400
231 254
232 255 //**********
233 256 // IRQ LINES
234 257 #define IRQ_GPTIMER_WATCHDOG 9
235 258 #define IRQ_SPARC_GPTIMER_WATCHDOG 0x19 // see sparcv8.pdf p.76 for interrupt levels
236 259 #define IRQ_WAVEFORM_PICKER 14
237 260 #define IRQ_SPARC_WAVEFORM_PICKER 0x1e // see sparcv8.pdf p.76 for interrupt levels
238 261 #define IRQ_SPECTRAL_MATRIX 6
239 262 #define IRQ_SPARC_SPECTRAL_MATRIX 0x16 // see sparcv8.pdf p.76 for interrupt levels
240 263
241 264 //*****
242 265 // TIME
243 266 #define CLKDIV_WATCHDOG (10000000 - 1) // 10.0s => 10 000 000
244 267 #define TIMER_WATCHDOG 1
245 268 #define WATCHDOG_PERIOD 100 // 1s
246 269 #define HK_PERIOD 100 // 100 * 10ms => 1s
247 270 #define AVGV_PERIOD 6 // 6 * 10ms => 60ms (1 / 16 = 62.5ms)
248 271 #define SY_LFR_TIME_SYN_TIMEOUT_in_ticks 200 // 200 * 10 ms = 2 s
249 272 #define HK_SYNC_WAIT 10 // 10 * 10 ms = 100 ms
250 273 #define SPW_LINK_WAIT 10 // 10 * 10 ms = 100 ms
251 274 #define TIMECODE_TIMER_TIMEOUT 120 // 120 * 10 ms = 1.2 s
252 275 #define TIMECODE_TIMER_TIMEOUT_INIT 200 // 200 * 10 ms = 2.0 s
253 276 #define TIMECODE_MASK 0x3f // 0011 1111
254 277
255 278 //**********
256 279 // LPP CODES
257 280 #define LFR_SUCCESSFUL 0
258 281 #define LFR_DEFAULT 1
259 282 #define LFR_EXE_ERROR 2
260 283
261 284 //******
262 285 // RTEMS
263 286 #define STACK_SIZE_MULT 2
264 287
265 288 #define TASKID_AVGV 0
266 289 #define TASKID_RECV 1
267 290 #define TASKID_ACTN 2
268 291 #define TASKID_SPIQ 3
269 292 #define TASKID_LOAD 4
270 293 #define TASKID_AVF0 5
271 294 #define TASKID_SWBD 6
272 295 #define TASKID_WFRM 7
273 296 #define TASKID_DUMB 8
274 297 #define TASKID_HOUS 9
275 298 #define TASKID_PRC0 10
276 299 #define TASKID_CWF3 11
277 300 #define TASKID_CWF2 12
278 301 #define TASKID_CWF1 13
279 302 #define TASKID_SEND 14
280 303 #define TASKID_LINK 15
281 304 #define TASKID_AVF1 16
282 305 #define TASKID_PRC1 17
283 306 #define TASKID_AVF2 18
284 307 #define TASKID_PRC2 19
285 308 #define TASKID_SCRB 20
286 309 #define TASKID_CALI 21
287 310
288 311 #define TASK_PRIORITY_SPIQ 5
289 312 #define TASK_PRIORITY_LINK 20
290 313 #define TASK_PRIORITY_AVGV 25
291 314 #define TASK_PRIORITY_HOUS 30
292 315 #define TASK_PRIORITY_CWF1 35 // CWF1 and CWF2 are never running together
293 316 #define TASK_PRIORITY_CWF2 35 //
294 317 #define TASK_PRIORITY_SWBD 37 // SWBD has a lower priority than WFRM, this is to extract the snapshot before sending it
295 318 #define TASK_PRIORITY_WFRM 40
296 319 #define TASK_PRIORITY_CWF3 40 // there is a printf in this function, be careful with its priority wrt CWF1
297 320 #define TASK_PRIORITY_SEND 45
298 321 #define TASK_PRIORITY_RECV 50
299 322 #define TASK_PRIORITY_CALI 50
300 323 #define TASK_PRIORITY_ACTN 50
301 324 #define TASK_PRIORITY_AVF0 60
302 325 #define TASK_PRIORITY_AVF1 70
303 326 #define TASK_PRIORITY_PRC0 100
304 327 #define TASK_PRIORITY_PRC1 100
305 328 #define TASK_PRIORITY_AVF2 110
306 329 #define TASK_PRIORITY_PRC2 110
307 330 #define TASK_PRIORITY_LOAD 190
308 331 #define TASK_PRIORITY_DUMB 200
309 332 #define TASK_PRIORITY_SCRB 210
310 333
311 334 #define MSG_QUEUE_COUNT_RECV 10
312 335 #define MSG_QUEUE_COUNT_SEND 50
313 336 #define MSG_QUEUE_COUNT_PRC0 10
314 337 #define MSG_QUEUE_COUNT_PRC1 10
315 338 #define MSG_QUEUE_COUNT_PRC2 5
316 339 #define MSG_QUEUE_SIZE_SEND 812 // 808 + 4 => TM_LFR_SCIENCE_BURST_BP2_F1
317 340 #define MSG_QUEUE_SIZE_PRC0 36 // two pointers, one rtems_event + 6 integers
318 341 #define MSG_QUEUE_SIZE_PRC1 36 // two pointers, one rtems_event + 6 integers
319 342 #define MSG_QUEUE_SIZE_PRC2 36 // two pointers, one rtems_event + 6 integers
320 343
321 344 #define QUEUE_RECV 0
322 345 #define QUEUE_SEND 1
323 346 #define QUEUE_PRC0 2
324 347 #define QUEUE_PRC1 3
325 348 #define QUEUE_PRC2 4
326 349
327 350 struct param_local_str{
328 351 unsigned int local_sbm1_nb_cwf_sent;
329 352 unsigned int local_sbm1_nb_cwf_max;
330 353 unsigned int local_sbm2_nb_cwf_sent;
331 354 unsigned int local_sbm2_nb_cwf_max;
332 355 };
333 356
334 357 //************
335 358 // FBINS MASKS
336 359
337 360 #define BYTES_PER_FBINS_MASK 16
338 361
339 362 typedef struct {
340 363 unsigned char merged_fbins_mask_f0[BYTES_PER_FBINS_MASK];
341 364 unsigned char merged_fbins_mask_f1[BYTES_PER_FBINS_MASK];
342 365 unsigned char merged_fbins_mask_f2[BYTES_PER_FBINS_MASK];
343 366 } fbins_masks_t;
344 367
345 368 #define DEFAULT_SY_LFR_PAS_FILTER_ENABLED 0
346 369 #define DEFAULT_SY_LFR_PAS_FILTER_MODULUS 4
347 370 #define DEFAULT_SY_LFR_PAS_FILTER_TBAD 1.0f
348 371 #define DEFAULT_SY_LFR_PAS_FILTER_OFFSET 0
349 372 #define DEFAULT_SY_LFR_PAS_FILTER_SHIFT 0.5f
350 373 #define DEFAULT_MODULUS 262144 // 65536 * 4
351 374 #define DEFAULT_TBAD 65536 // 65536
352 375 #define DEFAULT_OFFSET 0 // 65536 * 0
353 376 #define DEFAULT_SHIFT 32768 // 65536 / 2
354 377 #define DEFAULT_SY_LFR_SC_RW_DELTA_F 0.045f
355 378 #define DEFAULT_SY_LFR_RW_K1 1.f
356 379 #define DEFAULT_SY_LFR_RW_K2 8.f
357 380 #define DEFAULT_SY_LFR_RW_K3 24.f
358 381 #define DEFAULT_SY_LFR_RW_K4 48.f
359 382
360 383 typedef struct{
361 384 unsigned char spare_sy_lfr_pas_filter_enabled;
362 385 float sy_lfr_pas_filter_tbad;
363 386 float sy_lfr_pas_filter_shift;
364 387 uint64_t modulus_in_finetime;
365 388 uint64_t tbad_in_finetime;
366 389 uint64_t offset_in_finetime;
367 390 uint64_t shift_in_finetime;
368 391 float sy_lfr_sc_rw_delta_f;
369 392 // rw1_k
370 393 float sy_lfr_rw1_k1;
371 394 float sy_lfr_rw1_k2;
372 395 float sy_lfr_rw1_k3;
373 396 float sy_lfr_rw1_k4;
374 397 // rw2_k
375 398 float sy_lfr_rw2_k1;
376 399 float sy_lfr_rw2_k2;
377 400 float sy_lfr_rw2_k3;
378 401 float sy_lfr_rw2_k4;
379 402 // rw3_k
380 403 float sy_lfr_rw3_k1;
381 404 float sy_lfr_rw3_k2;
382 405 float sy_lfr_rw3_k3;
383 406 float sy_lfr_rw3_k4;
384 407 // rw4_k
385 408 float sy_lfr_rw4_k1;
386 409 float sy_lfr_rw4_k2;
387 410 float sy_lfr_rw4_k3;
388 411 float sy_lfr_rw4_k4;
389 412 } filterPar_t;
390 413
391 414 typedef struct{
392 415 // rw1_f
393 416 float cp_rpw_sc_rw1_f1;
394 417 float cp_rpw_sc_rw1_f2;
395 418 float cp_rpw_sc_rw1_f3;
396 419 float cp_rpw_sc_rw1_f4;
397 420 // rw2_f
398 421 float cp_rpw_sc_rw2_f1;
399 422 float cp_rpw_sc_rw2_f2;
400 423 float cp_rpw_sc_rw2_f3;
401 424 float cp_rpw_sc_rw2_f4;
402 425 // rw3_f
403 426 float cp_rpw_sc_rw3_f1;
404 427 float cp_rpw_sc_rw3_f2;
405 428 float cp_rpw_sc_rw3_f3;
406 429 float cp_rpw_sc_rw3_f4;
407 430 // rw4_f
408 431 float cp_rpw_sc_rw4_f1;
409 432 float cp_rpw_sc_rw4_f2;
410 433 float cp_rpw_sc_rw4_f3;
411 434 float cp_rpw_sc_rw4_f4;
412 435 } rw_f_t;
413 436
414 437 #define MATRIX_IS_POLLUTED 0
415 438 #define MATRIX_IS_NOT_POLLUTED 1
416 439 #define ACQUISITION_DURATION_F0 683 // 256 / 24576 * 65536
417 440 #define ACQUISITION_DURATION_F1 4096 // 256 / 4096 * 65536
418 441 #define ACQUISITION_DURATION_F2 65536 // 256 / 256 * 65536
419 442 #define HALF_ACQUISITION_DURATION_F0 341 // 256 / 24576 * 65536 / 2
420 443 #define HALF_ACQUISITION_DURATION_F1 2048 // 256 / 4096 * 65536 / 2
421 444 #define HALF_ACQUISITION_DURATION_F2 32768 // 256 / 256 * 65536 / 2
422 445
423 446 #endif // FSW_PARAMS_H_INCLUDED
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