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HG_REPOSITORIES » LPP » INSTRUMENTATION » USERS » JEANDET » SciQLOPCore

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			`r2:c7f53bda4647`		Basic serial variable creation and update This is a really basic implementation, this should help to develop the full VariableController pipeline. Added debug header to allow a custom behavior between debug and production, using SCIQLOP_ERROR macro will blow on debug but will have a different behavior in production code. This will allow to highlight any unexpected behavior without flooding stdout. Signed-off-by: Alexis Jeandet <alexis.jeandet@member.fsf.org>	Fri, 10 Aug 2018 13:05:09	jeandet		0
			`r1:d51953af4db3`		Added SynchronizationGroup2 tests and documentation Signed-off-by: Alexis Jeandet <alexis.jeandet@member.fsf.org>	Tue, 07 Aug 2018 14:49:18	jeandet		0
			`r0:86b06c4cec3c`		First init from SciQLop Core module The goal is to write a new variable controller Signed-off-by: Alexis Jeandet <alexis.jeandet@member.fsf.org>	Tue, 07 Aug 2018 13:17:12	jeandet		0

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