		Commit message	Age	Author	Refs
	`r97:6e0139d937f6`	Sync	Fri, 14 Feb 2014 06:22:10	paul	VHDLib206	0
	`r96:bf0185565c5e`	.hgsub added to the repository	Thu, 13 Feb 2014 08:30:53	paul	VHDLib206	0
	`r95:2543157c542c`	Sync	Thu, 13 Feb 2014 08:28:16	paul	VHDLib206	0
	`r94:399cb300a264`	Minor changes	Fri, 07 Feb 2014 12:56:25	paul	VHDLib206	0
	`r93:ffd04db5cce0`	Minor changes	Thu, 06 Feb 2014 14:46:28	paul	VHDLib206	0
	`r92:7c50b5fd63ee`	ICD 2.0 The FPGA version is written in the HK packets SWF packets compliant with the ICD 2048 BLK = 6 * 304 + 224	Tue, 28 Jan 2014 09:58:36	paul	VHDLib206	0
	`r91:6af3303996c6`	VHDL_DEV implemented. The code is compatible with: 1) the 206 bitstream 2) the new bitstream when VHDL_DEV is set	Fri, 24 Jan 2014 06:18:38	paul	VHDLib206	0
	`r90:b0bdcde41112`	Integration of the VHDL_DEV option Select the option to test the new VHDL design	Thu, 23 Jan 2014 05:52:42	paul	VHDLib206	0
	`r89:4ddc79d344bf`	Minor changes	Tue, 21 Jan 2014 12:48:02	paul	nov2013	0
	`r88:bf8352344672`	N = 2352 instead of 2048	Tue, 21 Jan 2014 12:08:28	paul	VHDLib206	0

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