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R3 updates. TC handlers added for the new telecommands:...
R3 updates. TC handlers added for the new telecommands: TC_LFR_LOAD_KCOEFFICIENTS TC_LFR_DUMP_KCOEFFICIENTD TC_LFR_LOAD_FBINS_MASK

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r187:87f7d2226935 VHDL_0_1_28
r192:a0b224a4fc7c VHDL_0_1_28
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GscMemoryLPP.hpp
62 lines | 1.5 KiB | text/x-c++hdr | CppLexer
#ifndef GSCMEMORY_HPP_
#define GSCMEMORY_HPP_
#ifndef LEON3
#define LEON3
#endif
static unsigned int getCacheControlRegister(){
#ifdef LEON3
unsigned int cacheControlRegister = 0;
__asm__ __volatile__("lda [%%g0] 2, %0" : "=r"(cacheControlRegister) : );
return cacheControlRegister;
#endif
}
static void setCacheControlRegister(unsigned int cacheControlRegister)
{
#ifdef LEON3
__asm__ __volatile__("sta %0, [%%g0] 2" : : "r"(cacheControlRegister));
#endif
}
/**
* Flush the data cache and the instruction cache.
*
* @return
*/
static inline void flushCache() {
asm("flush");
}
static void enableInstructionCache() {
#ifdef LEON3
unsigned int cacheControlRegister;
cacheControlRegister = getCacheControlRegister();
cacheControlRegister = (cacheControlRegister | 0x3);
setCacheControlRegister(cacheControlRegister);
#endif
}
static void enableDataCache() {
#ifdef LEON3
unsigned int cacheControlRegister;
cacheControlRegister = getCacheControlRegister();
cacheControlRegister = (cacheControlRegister | 0xc);
setCacheControlRegister(cacheControlRegister);
#endif
}
static void enableInstructionBurstFetch() {
#ifdef LEON3
unsigned int cacheControlRegister;
cacheControlRegister = getCacheControlRegister();
// set the bit IB to 1
cacheControlRegister = (cacheControlRegister | 0x10000);
setCacheControlRegister(cacheControlRegister);
#endif
}
#endif /* GSCMEMORY_HPP_ */