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/** General usage functions and RTEMS tasks.
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*
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* @file
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* @author P. LEROY
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*
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*/
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#include "fsw_misc.h"
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void configure_timer(gptimer_regs_t *gptimer_regs, unsigned char timer, unsigned int clock_divider,
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unsigned char interrupt_level, rtems_isr (*timer_isr)() )
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{
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/** This function configures a GPTIMER timer instantiated in the VHDL design.
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*
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* @param gptimer_regs points to the APB registers of the GPTIMER IP core.
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* @param timer is the number of the timer in the IP core (several timers can be instantiated).
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* @param clock_divider is the divider of the 1 MHz clock that will be configured.
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* @param interrupt_level is the interrupt level that the timer drives.
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* @param timer_isr is the interrupt subroutine that will be attached to the IRQ driven by the timer.
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*
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* Interrupt levels are described in the SPARC documentation sparcv8.pdf p.76
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*
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*/
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rtems_status_code status;
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rtems_isr_entry old_isr_handler;
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gptimer_regs->timer[timer].ctrl = 0x00; // reset the control register
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status = rtems_interrupt_catch( timer_isr, interrupt_level, &old_isr_handler) ; // see sparcv8.pdf p.76 for interrupt levels
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if (status!=RTEMS_SUCCESSFUL)
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{
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PRINTF("in configure_timer *** ERR rtems_interrupt_catch\n")
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}
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timer_set_clock_divider( gptimer_regs, timer, clock_divider);
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}
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void timer_start(gptimer_regs_t *gptimer_regs, unsigned char timer)
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{
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/** This function starts a GPTIMER timer.
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*
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* @param gptimer_regs points to the APB registers of the GPTIMER IP core.
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* @param timer is the number of the timer in the IP core (several timers can be instantiated).
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*
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*/
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gptimer_regs->timer[timer].ctrl = gptimer_regs->timer[timer].ctrl | 0x00000010; // clear pending IRQ if any
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gptimer_regs->timer[timer].ctrl = gptimer_regs->timer[timer].ctrl | 0x00000004; // LD load value from the reload register
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gptimer_regs->timer[timer].ctrl = gptimer_regs->timer[timer].ctrl | 0x00000001; // EN enable the timer
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gptimer_regs->timer[timer].ctrl = gptimer_regs->timer[timer].ctrl | 0x00000002; // RS restart
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gptimer_regs->timer[timer].ctrl = gptimer_regs->timer[timer].ctrl | 0x00000008; // IE interrupt enable
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}
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void timer_stop(gptimer_regs_t *gptimer_regs, unsigned char timer)
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{
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/** This function stops a GPTIMER timer.
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*
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* @param gptimer_regs points to the APB registers of the GPTIMER IP core.
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* @param timer is the number of the timer in the IP core (several timers can be instantiated).
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*
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*/
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gptimer_regs->timer[timer].ctrl = gptimer_regs->timer[timer].ctrl & 0xfffffffe; // EN enable the timer
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gptimer_regs->timer[timer].ctrl = gptimer_regs->timer[timer].ctrl & 0xffffffef; // IE interrupt enable
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gptimer_regs->timer[timer].ctrl = gptimer_regs->timer[timer].ctrl | 0x00000010; // clear pending IRQ if any
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}
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void timer_set_clock_divider(gptimer_regs_t *gptimer_regs, unsigned char timer, unsigned int clock_divider)
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{
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/** This function sets the clock divider of a GPTIMER timer.
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*
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* @param gptimer_regs points to the APB registers of the GPTIMER IP core.
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* @param timer is the number of the timer in the IP core (several timers can be instantiated).
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* @param clock_divider is the divider of the 1 MHz clock that will be configured.
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*
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*/
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gptimer_regs->timer[timer].reload = clock_divider; // base clock frequency is 1 MHz
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}
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int send_console_outputs_on_apbuart_port( void ) // Send the console outputs on the apbuart port
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{
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struct apbuart_regs_str *apbuart_regs = (struct apbuart_regs_str *) REGS_ADDR_APBUART;
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apbuart_regs->ctrl = APBUART_CTRL_REG_MASK_TE;
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return 0;
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}
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int enable_apbuart_transmitter( void ) // set the bit 1, TE Transmitter Enable to 1 in the APBUART control register
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{
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struct apbuart_regs_str *apbuart_regs = (struct apbuart_regs_str *) REGS_ADDR_APBUART;
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apbuart_regs->ctrl = apbuart_regs->ctrl | APBUART_CTRL_REG_MASK_TE;
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return 0;
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}
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void set_apbuart_scaler_reload_register(unsigned int regs, unsigned int value)
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{
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/** This function sets the scaler reload register of the apbuart module
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*
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* @param regs is the address of the apbuart registers in memory
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* @param value is the value that will be stored in the scaler register
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*
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* The value shall be set by the software to get data on the serial interface.
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*
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*/
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struct apbuart_regs_str *apbuart_regs = (struct apbuart_regs_str *) regs;
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apbuart_regs->scaler = value;
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BOOT_PRINTF1("OK *** apbuart port scaler reload register set to 0x%x\n", value)
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}
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//************
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// RTEMS TASKS
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rtems_task stat_task(rtems_task_argument argument)
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{
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int i;
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int j;
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i = 0;
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j = 0;
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BOOT_PRINTF("in STAT *** \n")
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while(1){
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rtems_task_wake_after(1000);
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PRINTF1("%d\n", j)
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if (i == CPU_USAGE_REPORT_PERIOD) {
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// #ifdef PRINT_TASK_STATISTICS
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// rtems_cpu_usage_report();
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// rtems_cpu_usage_reset();
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// #endif
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i = 0;
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}
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else i++;
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j++;
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}
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}
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rtems_task dumb_task( rtems_task_argument unused )
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{
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/** This RTEMS taks is used to print messages without affecting the general behaviour of the software.
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*
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* @param unused is the starting argument of the RTEMS task
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*
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* The DUMB taks waits for RTEMS events and print messages depending on the incoming events.
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*
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*/
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unsigned int i;
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unsigned int intEventOut;
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unsigned int coarse_time = 0;
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unsigned int fine_time = 0;
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rtems_event_set event_out;
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char *DumbMessages[12] = {"in DUMB *** default", // RTEMS_EVENT_0
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"in DUMB *** timecode_irq_handler", // RTEMS_EVENT_1
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"in DUMB *** f3 buffer changed", // RTEMS_EVENT_2
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"in DUMB *** in SMIQ *** Error sending event to AVF0", // RTEMS_EVENT_3
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"in DUMB *** spectral_matrices_isr *** Error sending event to SMIQ", // RTEMS_EVENT_4
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"in DUMB *** waveforms_simulator_isr", // RTEMS_EVENT_5
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"ERR HK", // RTEMS_EVENT_6
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"ready for dump", // RTEMS_EVENT_7
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"VHDL ERR *** spectral matrix", // RTEMS_EVENT_8
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"tick", // RTEMS_EVENT_9
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"VHDL ERR *** waveform picker", // RTEMS_EVENT_10
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"VHDL ERR *** unexpected ready matrix values" // RTEMS_EVENT_11
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};
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BOOT_PRINTF("in DUMB *** \n")
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while(1){
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rtems_event_receive(RTEMS_EVENT_0 | RTEMS_EVENT_1 | RTEMS_EVENT_2 | RTEMS_EVENT_3
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| RTEMS_EVENT_4 | RTEMS_EVENT_5 | RTEMS_EVENT_6 | RTEMS_EVENT_7
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| RTEMS_EVENT_8 | RTEMS_EVENT_9,
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RTEMS_WAIT | RTEMS_EVENT_ANY, RTEMS_NO_TIMEOUT, &event_out); // wait for an RTEMS_EVENT
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intEventOut = (unsigned int) event_out;
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for ( i=0; i<32; i++)
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{
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if ( ((intEventOut >> i) & 0x0001) != 0)
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{
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coarse_time = time_management_regs->coarse_time;
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fine_time = time_management_regs->fine_time;
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printf("in DUMB *** coarse: %x, fine: %x, %s\n", coarse_time, fine_time, DumbMessages[i]);
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if (i==8)
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{
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}
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if (i==10)
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{
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}
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}
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}
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}
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}
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//*****************************
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// init housekeeping parameters
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void increment_seq_counter( unsigned short *packetSequenceControl )
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{
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/** This function increment the sequence counter psased in argument.
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*
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* The increment does not affect the grouping flag. In case of an overflow, the counter is reset to 0.
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*
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*/
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unsigned short segmentation_grouping_flag;
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unsigned short sequence_cnt;
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segmentation_grouping_flag = TM_PACKET_SEQ_CTRL_STANDALONE << 8; // keep bits 7 downto 6
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sequence_cnt = (*packetSequenceControl) & 0x3fff; // [0011 1111 1111 1111]
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if ( sequence_cnt < SEQ_CNT_MAX)
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{
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sequence_cnt = sequence_cnt + 1;
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}
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else
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{
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sequence_cnt = 0;
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}
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*packetSequenceControl = segmentation_grouping_flag | sequence_cnt ;
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}
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void getTime( unsigned char *time)
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{
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/** This function write the current local time in the time buffer passed in argument.
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*
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*/
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time[0] = (unsigned char) (time_management_regs->coarse_time>>24);
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time[1] = (unsigned char) (time_management_regs->coarse_time>>16);
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time[2] = (unsigned char) (time_management_regs->coarse_time>>8);
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time[3] = (unsigned char) (time_management_regs->coarse_time);
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time[4] = (unsigned char) (time_management_regs->fine_time>>8);
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time[5] = (unsigned char) (time_management_regs->fine_time);
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}
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unsigned long long int getTimeAsUnsignedLongLongInt( )
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{
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/** This function write the current local time in the time buffer passed in argument.
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*
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*/
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unsigned long long int time;
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time = ( (unsigned long long int) (time_management_regs->coarse_time & 0x7fffffff) << 16 )
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+ time_management_regs->fine_time;
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return time;
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}
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