##// END OF EJS Templates
TM_LFR_SCIENCE_NORMA_ASM_ packets modified, 32 bits values instead of 16 bits...
TM_LFR_SCIENCE_NORMA_ASM_ packets modified, 32 bits values instead of 16 bits resetCacheControlRegister function added txHdrSize changed (34 instead of 32)

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r191:88d58b8c0419 VHDL_0_1_28
r196:48fc5efcfe9b R3
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LFRControlPlugin_reload_timegen.py
12 lines | 290 B | text/x-python | PythonLexer
/ python_scripts / LFRControlPlugin_reload_timegen.py
# LOAD FSW USING LINK 1
SpwPlugin0.StarDundeeSelectLinkNumber( 2 )
dsu3plugin0.openFile("/opt/DEV_PLE/timegen-qt/bin/timegen")
dsu3plugin0.loadFile()
dsu3plugin0.run()
# START SENDING TIMECODES AT 1 Hz
SpwPlugin0.StarDundeeStartTimecodes( 1 )
SpwPlugin0.StarDundeeSelectLinkNumber( 1 )