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#ifndef GSCMEMORY_HPP_
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#define GSCMEMORY_HPP_
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#ifndef LEON3
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#define LEON3
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#endif
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#define REGS_ADDR_PLUGANDPLAY 0xFFFFF000
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#define ASR16_REG_ADDRESS 0x90400040 // Ancillary State Register 16 = Register protection control register (FT only)
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#define DEVICEID_LEON3 0x003
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#define DEVICEID_LEON3FT 0x053
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#define VENDORID_GAISLER 0x01
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// CCR
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#define POS_FT 19
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//
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#define POS_ITE 12
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#define COUNTER_FIELD_ITE 0x00003000 // 0000 0000 0000 0000 0011 0000 0000 0000
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#define COUNTER_MASK_ITE 0xffffcfff // 1111 1111 1111 1111 1100 1111 1111 1111
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#define POS_IDE 10
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#define COUNTER_FIELD_IDE 0x00000c00 // 0000 0000 0000 0000 0000 1100 0000 0000
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#define COUNTER_MASK_IDE 0xfffff3ff // 1111 1111 1111 1111 1111 0011 1111 1111
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//
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#define POS_DTE 8
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#define COUNTER_FIELD_DTE 0x00000300 // 0000 0000 0000 0000 0000 0011 0000 0000
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#define COUNTER_MASK_DTE 0xfffffcff // 1111 1111 1111 1111 1111 1100 1111 1111
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#define POS_DDE 6
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#define COUNTER_FIELD_DDE 0x000000c0 // 0000 0000 0000 0000 0000 0000 1100 0000
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#define COUNTER_MASK_DDE 0xffffff3f // 1111 1111 1111 1111 1111 1111 0011 1111
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// ASR16
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#define POS_FPFTID 30
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#define POS_FPRF 27
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#define POS_FDI 16 // FP RF protection enable/disable
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#define POS_IUFTID 14
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#define POS_IURF 11
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#define POS_IDI 0 // IU RF protection enable/disable
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#define COUNTER_FIELD_FPRF 0x38000000 // 0011 1000 0000 0000 0000 0000 0000 0000
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#define COUNTER_MASK_FPRF 0xc7ffffff // 1100 0111 1111 1111 1111 1111 1111 1111
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#define COUNTER_FIELD_IURF 0x00003800 // 0000 0000 0000 0000 0011 1000 0000 0000
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#define COUNTER_MASK_IURF 0xffffc7ff // 1111 1111 1111 1111 1100 0111 1111 1111
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volatile unsigned int *asr16Ptr = (volatile unsigned int *) ASR16_REG_ADDRESS;
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#ifdef ENABLE_DEAD_CODE
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static inline void flushCache()
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{
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/**
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* Flush the data cache and the instruction cache.
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*
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* @param void
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*
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* @return void
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*/
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asm("flush");
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}
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#endif
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//***************************
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// CCR Cache control register
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static unsigned int CCR_getValue()
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{
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unsigned int cacheControlRegister = 0;
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__asm__ __volatile__("lda [%%g0] 2, %0" : "=r"(cacheControlRegister) : );
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return cacheControlRegister;
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}
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static void CCR_setValue(unsigned int cacheControlRegister)
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{
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__asm__ __volatile__("sta %0, [%%g0] 2" : : "r"(cacheControlRegister));
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}
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static void CCR_resetCacheControlRegister()
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{
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unsigned int cacheControlRegister;
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cacheControlRegister = 0x00;
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CCR_setValue(cacheControlRegister);
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}
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static void CCR_enableInstructionCache()
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{
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// [1:0] Instruction Cache state (ICS)
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// Indicates the current data cache state according to the following: X0 = disabled, 01 = frozen, 11 = enabled.
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unsigned int cacheControlRegister;
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cacheControlRegister = CCR_getValue();
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cacheControlRegister = (cacheControlRegister | 0x3);
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CCR_setValue(cacheControlRegister);
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}
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static void CCR_enableDataCache()
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{
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// [3:2] Data Cache state (DCS)
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// Indicates the current data cache state according to the following: X0 = disabled, 01 = frozen, 11 = enabled.
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unsigned int cacheControlRegister;
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cacheControlRegister = CCR_getValue();
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cacheControlRegister = (cacheControlRegister | 0xc);
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CCR_setValue(cacheControlRegister);
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}
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static void CCR_enableInstructionBurstFetch()
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{
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// [16] Instruction burst fetch (IB). This bit enables burst fill during instruction fetch.
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unsigned int cacheControlRegister;
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cacheControlRegister = CCR_getValue();
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// set the bit IB to 1
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cacheControlRegister = (cacheControlRegister | 0x10000);
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CCR_setValue(cacheControlRegister);
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}
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void CCR_getInstructionAndDataErrorCounters( unsigned int* instructionErrorCounter, unsigned int* dataErrorCounter )
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{
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// [13:12] Instruction Tag Errors (ITE) - Number of detected parity errors in the instruction tag cache.
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// Only available if fault-tolerance is enabled (FT field in this register is non-zero).
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// [11:10] Instruction Data Errors (IDE) - Number of detected parity errors in the instruction data cache.
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// Only available if fault-tolerance is enabled (FT field in this register is non-zero).
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unsigned int cacheControlRegister;
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unsigned int iTE;
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unsigned int iDE;
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unsigned int dTE;
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unsigned int dDE;
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cacheControlRegister = CCR_getValue();
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iTE = (cacheControlRegister & COUNTER_FIELD_ITE) >> POS_ITE;
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iDE = (cacheControlRegister & COUNTER_FIELD_IDE) >> POS_IDE;
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dTE = (cacheControlRegister & COUNTER_FIELD_DTE) >> POS_DTE;
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dDE = (cacheControlRegister & COUNTER_FIELD_DDE) >> POS_DDE;
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*instructionErrorCounter = iTE + iDE;
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*dataErrorCounter = dTE + dDE;
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// reset counters
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cacheControlRegister = cacheControlRegister
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& COUNTER_FIELD_ITE
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& COUNTER_FIELD_IDE
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& COUNTER_FIELD_DTE
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& COUNTER_FIELD_DDE;
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CCR_setValue(cacheControlRegister);
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}
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//*******************************************
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// ASR16 Register protection control register
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static void ASR16_resetRegisterProtectionControlRegister()
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{
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*asr16Ptr = 0x00;
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}
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void ASR16_get_FPRF_IURF_ErrorCounters( unsigned int* fprfErrorCounter, unsigned int* iurfErrorCounter)
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{
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/** This function is used to retrieve the integer unit register file error counter and the floating point unit
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* register file error counter
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*
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* @return void
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*
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* [29:27] FP RF error counter - Number of detected parity errors in the FP register file.
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* [13:11] IU RF error counter - Number of detected parity errors in the IU register file.
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*
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*/
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unsigned int asr16;
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asr16 = *asr16Ptr;
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*fprfErrorCounter = ( asr16 & COUNTER_FIELD_FPRF ) >> POS_FPRF;
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*iurfErrorCounter = ( asr16 & COUNTER_FIELD_IURF ) >> POS_IURF;
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// reset the counter to 0
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asr16 = asr16
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& COUNTER_MASK_FPRF
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& COUNTER_FIELD_IURF;
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*asr16Ptr = asr16;
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}
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static void faultTolerantScheme()
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{
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// [20:19] FT scheme (FT) - “00” = no FT, “01” = 4-bit checking implemented
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unsigned int cacheControlRegister;
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unsigned int *plugAndPlayRegister;
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unsigned int vendorId;
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unsigned int deviceId;
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plugAndPlayRegister = (unsigned int*) REGS_ADDR_PLUGANDPLAY;
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vendorId = ( (*plugAndPlayRegister) & 0xff000000 ) >> 24;
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deviceId = ( (*plugAndPlayRegister) & 0x00fff000 ) >> 12;
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cacheControlRegister = CCR_getValue();
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if( (vendorId == VENDORID_GAISLER) & (deviceId ==DEVICEID_LEON3FT) )
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{
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PRINTF("in faultTolerantScheme *** Leon3FT detected\n");
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PRINTF2(" *** vendorID = 0x%x, deviceId = 0x%x\n", vendorId, deviceId);
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PRINTF1("ASR16 IU RF protection, bit 0 (IDI) is: 0x%x (0 => protection enabled)\n",
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(*asr16Ptr >> POS_IDI) & 1);
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PRINTF1("ASR16 FP RF protection, bit 16 (FDI) is: 0x%x (0 => protection enabled)\n",
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(*asr16Ptr >> POS_FDI) & 1);
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PRINTF1("ASR16 IU FT ID bits [15:14] is: 0x%x (2 => 8-bit parity without restart)\n",
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(*asr16Ptr >> POS_IUFTID) & 0x3);
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PRINTF1("ASR16 FP FT ID bits [31:30] is: 0x%x (1 => 4-bit parity with restart)\n",
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(*asr16Ptr >> POS_FPFTID) & 0x03);
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PRINTF1("CCR FT bits [20:19] are: 0x%x (1 => 4-bit parity with restart)\n",
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(cacheControlRegister >> POS_FT) & 0x3 );
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// CCR The FFT bits are just read, the FT scheme is set to “01” = 4-bit checking implemented by default
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// ASR16 Ancillary State Register configuration (Register protection control register)
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// IU RF protection is set by default, bit 0 IDI = 0
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// FP RF protection is set by default, bit 16 FDI = 0
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}
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else
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{
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PRINTF("in faultTolerantScheme *** Leon3FT not detected\n");
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PRINTF2(" *** vendorID = 0x%x, deviceId = 0x%x\n", vendorId, deviceId);
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}
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}
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#endif /* GSCMEMORY_HPP_ */
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