##// END OF EJS Templates
Bug 978 Mauvais nombre de FFT retiré lors du filtrage PAS
paul -
r350:d301b368f883 R3++ draft
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@@ -1,2 +1,2
1 3081d1f9bb20b2b64a192585337a292a9804e0c5 LFR_basic-parameters
1 3081d1f9bb20b2b64a192585337a292a9804e0c5 LFR_basic-parameters
2 21ada91882790323b08a38518ed1af5a36fa4deb header/lfr_common_headers
2 f97721719ddb7e088956d5fd3cffb0f9587a041b header/lfr_common_headers
@@ -1,802 +1,830
1 /** Functions related to data processing.
1 /** Functions related to data processing.
2 *
2 *
3 * @file
3 * @file
4 * @author P. LEROY
4 * @author P. LEROY
5 *
5 *
6 * These function are related to data processing, i.e. spectral matrices averaging and basic parameters computation.
6 * These function are related to data processing, i.e. spectral matrices averaging and basic parameters computation.
7 *
7 *
8 */
8 */
9
9
10 #include "fsw_processing.h"
10 #include "fsw_processing.h"
11 #include "fsw_processing_globals.c"
11 #include "fsw_processing_globals.c"
12 #include "fsw_init.h"
12 #include "fsw_init.h"
13
13
14 unsigned int nb_sm_f0 = 0;
14 unsigned int nb_sm_f0 = 0;
15 unsigned int nb_sm_f0_aux_f1= 0;
15 unsigned int nb_sm_f0_aux_f1= 0;
16 unsigned int nb_sm_f1 = 0;
16 unsigned int nb_sm_f1 = 0;
17 unsigned int nb_sm_f0_aux_f2= 0;
17 unsigned int nb_sm_f0_aux_f2= 0;
18
18
19 typedef enum restartState_t
19 typedef enum restartState_t
20 {
20 {
21 WAIT_FOR_F2,
21 WAIT_FOR_F2,
22 WAIT_FOR_F1,
22 WAIT_FOR_F1,
23 WAIT_FOR_F0
23 WAIT_FOR_F0
24 } restartState;
24 } restartState;
25
25
26 //************************
26 //************************
27 // spectral matrices rings
27 // spectral matrices rings
28 ring_node sm_ring_f0[ NB_RING_NODES_SM_F0 ] = {0};
28 ring_node sm_ring_f0[ NB_RING_NODES_SM_F0 ] = {0};
29 ring_node sm_ring_f1[ NB_RING_NODES_SM_F1 ] = {0};
29 ring_node sm_ring_f1[ NB_RING_NODES_SM_F1 ] = {0};
30 ring_node sm_ring_f2[ NB_RING_NODES_SM_F2 ] = {0};
30 ring_node sm_ring_f2[ NB_RING_NODES_SM_F2 ] = {0};
31 ring_node *current_ring_node_sm_f0 = NULL;
31 ring_node *current_ring_node_sm_f0 = NULL;
32 ring_node *current_ring_node_sm_f1 = NULL;
32 ring_node *current_ring_node_sm_f1 = NULL;
33 ring_node *current_ring_node_sm_f2 = NULL;
33 ring_node *current_ring_node_sm_f2 = NULL;
34 ring_node *ring_node_for_averaging_sm_f0= NULL;
34 ring_node *ring_node_for_averaging_sm_f0= NULL;
35 ring_node *ring_node_for_averaging_sm_f1= NULL;
35 ring_node *ring_node_for_averaging_sm_f1= NULL;
36 ring_node *ring_node_for_averaging_sm_f2= NULL;
36 ring_node *ring_node_for_averaging_sm_f2= NULL;
37
37
38 //
38 //
39 ring_node * getRingNodeForAveraging( unsigned char frequencyChannel)
39 ring_node * getRingNodeForAveraging( unsigned char frequencyChannel)
40 {
40 {
41 ring_node *node;
41 ring_node *node;
42
42
43 node = NULL;
43 node = NULL;
44 switch ( frequencyChannel ) {
44 switch ( frequencyChannel ) {
45 case CHANNELF0:
45 case CHANNELF0:
46 node = ring_node_for_averaging_sm_f0;
46 node = ring_node_for_averaging_sm_f0;
47 break;
47 break;
48 case CHANNELF1:
48 case CHANNELF1:
49 node = ring_node_for_averaging_sm_f1;
49 node = ring_node_for_averaging_sm_f1;
50 break;
50 break;
51 case CHANNELF2:
51 case CHANNELF2:
52 node = ring_node_for_averaging_sm_f2;
52 node = ring_node_for_averaging_sm_f2;
53 break;
53 break;
54 default:
54 default:
55 break;
55 break;
56 }
56 }
57
57
58 return node;
58 return node;
59 }
59 }
60
60
61 //***********************************************************
61 //***********************************************************
62 // Interrupt Service Routine for spectral matrices processing
62 // Interrupt Service Routine for spectral matrices processing
63
63
64 void spectral_matrices_isr_f0( int statusReg )
64 void spectral_matrices_isr_f0( int statusReg )
65 {
65 {
66 unsigned char status;
66 unsigned char status;
67 rtems_status_code status_code;
67 rtems_status_code status_code;
68 ring_node *full_ring_node;
68 ring_node *full_ring_node;
69
69
70 status = (unsigned char) (statusReg & BITS_STATUS_F0); // [0011] get the status_ready_matrix_f0_x bits
70 status = (unsigned char) (statusReg & BITS_STATUS_F0); // [0011] get the status_ready_matrix_f0_x bits
71
71
72 switch(status)
72 switch(status)
73 {
73 {
74 case 0:
74 case 0:
75 break;
75 break;
76 case BIT_READY_0_1:
76 case BIT_READY_0_1:
77 // UNEXPECTED VALUE
77 // UNEXPECTED VALUE
78 spectral_matrix_regs->status = BIT_READY_0_1; // [0011]
78 spectral_matrix_regs->status = BIT_READY_0_1; // [0011]
79 status_code = rtems_event_send( Task_id[TASKID_DUMB], RTEMS_EVENT_11 );
79 status_code = rtems_event_send( Task_id[TASKID_DUMB], RTEMS_EVENT_11 );
80 break;
80 break;
81 case BIT_READY_0:
81 case BIT_READY_0:
82 full_ring_node = current_ring_node_sm_f0->previous;
82 full_ring_node = current_ring_node_sm_f0->previous;
83 full_ring_node->coarseTime = spectral_matrix_regs->f0_0_coarse_time;
83 full_ring_node->coarseTime = spectral_matrix_regs->f0_0_coarse_time;
84 full_ring_node->fineTime = spectral_matrix_regs->f0_0_fine_time;
84 full_ring_node->fineTime = spectral_matrix_regs->f0_0_fine_time;
85 current_ring_node_sm_f0 = current_ring_node_sm_f0->next;
85 current_ring_node_sm_f0 = current_ring_node_sm_f0->next;
86 spectral_matrix_regs->f0_0_address = current_ring_node_sm_f0->buffer_address;
86 spectral_matrix_regs->f0_0_address = current_ring_node_sm_f0->buffer_address;
87 // if there are enough ring nodes ready, wake up an AVFx task
87 // if there are enough ring nodes ready, wake up an AVFx task
88 nb_sm_f0 = nb_sm_f0 + 1;
88 nb_sm_f0 = nb_sm_f0 + 1;
89 if (nb_sm_f0 == NB_SM_BEFORE_AVF0_F1)
89 if (nb_sm_f0 == NB_SM_BEFORE_AVF0_F1)
90 {
90 {
91 ring_node_for_averaging_sm_f0 = full_ring_node;
91 ring_node_for_averaging_sm_f0 = full_ring_node;
92 if (rtems_event_send( Task_id[TASKID_AVF0], RTEMS_EVENT_0 ) != RTEMS_SUCCESSFUL)
92 if (rtems_event_send( Task_id[TASKID_AVF0], RTEMS_EVENT_0 ) != RTEMS_SUCCESSFUL)
93 {
93 {
94 status_code = rtems_event_send( Task_id[TASKID_DUMB], RTEMS_EVENT_3 );
94 status_code = rtems_event_send( Task_id[TASKID_DUMB], RTEMS_EVENT_3 );
95 }
95 }
96 nb_sm_f0 = 0;
96 nb_sm_f0 = 0;
97 }
97 }
98 spectral_matrix_regs->status = BIT_READY_0; // [0000 0001]
98 spectral_matrix_regs->status = BIT_READY_0; // [0000 0001]
99 break;
99 break;
100 case BIT_READY_1:
100 case BIT_READY_1:
101 full_ring_node = current_ring_node_sm_f0->previous;
101 full_ring_node = current_ring_node_sm_f0->previous;
102 full_ring_node->coarseTime = spectral_matrix_regs->f0_1_coarse_time;
102 full_ring_node->coarseTime = spectral_matrix_regs->f0_1_coarse_time;
103 full_ring_node->fineTime = spectral_matrix_regs->f0_1_fine_time;
103 full_ring_node->fineTime = spectral_matrix_regs->f0_1_fine_time;
104 current_ring_node_sm_f0 = current_ring_node_sm_f0->next;
104 current_ring_node_sm_f0 = current_ring_node_sm_f0->next;
105 spectral_matrix_regs->f0_1_address = current_ring_node_sm_f0->buffer_address;
105 spectral_matrix_regs->f0_1_address = current_ring_node_sm_f0->buffer_address;
106 // if there are enough ring nodes ready, wake up an AVFx task
106 // if there are enough ring nodes ready, wake up an AVFx task
107 nb_sm_f0 = nb_sm_f0 + 1;
107 nb_sm_f0 = nb_sm_f0 + 1;
108 if (nb_sm_f0 == NB_SM_BEFORE_AVF0_F1)
108 if (nb_sm_f0 == NB_SM_BEFORE_AVF0_F1)
109 {
109 {
110 ring_node_for_averaging_sm_f0 = full_ring_node;
110 ring_node_for_averaging_sm_f0 = full_ring_node;
111 if (rtems_event_send( Task_id[TASKID_AVF0], RTEMS_EVENT_0 ) != RTEMS_SUCCESSFUL)
111 if (rtems_event_send( Task_id[TASKID_AVF0], RTEMS_EVENT_0 ) != RTEMS_SUCCESSFUL)
112 {
112 {
113 status_code = rtems_event_send( Task_id[TASKID_DUMB], RTEMS_EVENT_3 );
113 status_code = rtems_event_send( Task_id[TASKID_DUMB], RTEMS_EVENT_3 );
114 }
114 }
115 nb_sm_f0 = 0;
115 nb_sm_f0 = 0;
116 }
116 }
117 spectral_matrix_regs->status = BIT_READY_1; // [0000 0010]
117 spectral_matrix_regs->status = BIT_READY_1; // [0000 0010]
118 break;
118 break;
119 default:
119 default:
120 break;
120 break;
121 }
121 }
122 }
122 }
123
123
124 void spectral_matrices_isr_f1( int statusReg )
124 void spectral_matrices_isr_f1( int statusReg )
125 {
125 {
126 rtems_status_code status_code;
126 rtems_status_code status_code;
127 unsigned char status;
127 unsigned char status;
128 ring_node *full_ring_node;
128 ring_node *full_ring_node;
129
129
130 status = (unsigned char) ((statusReg & BITS_STATUS_F1) >> SHIFT_2_BITS); // [1100] get the status_ready_matrix_f1_x bits
130 status = (unsigned char) ((statusReg & BITS_STATUS_F1) >> SHIFT_2_BITS); // [1100] get the status_ready_matrix_f1_x bits
131
131
132 switch(status)
132 switch(status)
133 {
133 {
134 case 0:
134 case 0:
135 break;
135 break;
136 case BIT_READY_0_1:
136 case BIT_READY_0_1:
137 // UNEXPECTED VALUE
137 // UNEXPECTED VALUE
138 spectral_matrix_regs->status = BITS_STATUS_F1; // [1100]
138 spectral_matrix_regs->status = BITS_STATUS_F1; // [1100]
139 status_code = rtems_event_send( Task_id[TASKID_DUMB], RTEMS_EVENT_11 );
139 status_code = rtems_event_send( Task_id[TASKID_DUMB], RTEMS_EVENT_11 );
140 break;
140 break;
141 case BIT_READY_0:
141 case BIT_READY_0:
142 full_ring_node = current_ring_node_sm_f1->previous;
142 full_ring_node = current_ring_node_sm_f1->previous;
143 full_ring_node->coarseTime = spectral_matrix_regs->f1_0_coarse_time;
143 full_ring_node->coarseTime = spectral_matrix_regs->f1_0_coarse_time;
144 full_ring_node->fineTime = spectral_matrix_regs->f1_0_fine_time;
144 full_ring_node->fineTime = spectral_matrix_regs->f1_0_fine_time;
145 current_ring_node_sm_f1 = current_ring_node_sm_f1->next;
145 current_ring_node_sm_f1 = current_ring_node_sm_f1->next;
146 spectral_matrix_regs->f1_0_address = current_ring_node_sm_f1->buffer_address;
146 spectral_matrix_regs->f1_0_address = current_ring_node_sm_f1->buffer_address;
147 // if there are enough ring nodes ready, wake up an AVFx task
147 // if there are enough ring nodes ready, wake up an AVFx task
148 nb_sm_f1 = nb_sm_f1 + 1;
148 nb_sm_f1 = nb_sm_f1 + 1;
149 if (nb_sm_f1 == NB_SM_BEFORE_AVF0_F1)
149 if (nb_sm_f1 == NB_SM_BEFORE_AVF0_F1)
150 {
150 {
151 ring_node_for_averaging_sm_f1 = full_ring_node;
151 ring_node_for_averaging_sm_f1 = full_ring_node;
152 if (rtems_event_send( Task_id[TASKID_AVF1], RTEMS_EVENT_0 ) != RTEMS_SUCCESSFUL)
152 if (rtems_event_send( Task_id[TASKID_AVF1], RTEMS_EVENT_0 ) != RTEMS_SUCCESSFUL)
153 {
153 {
154 status_code = rtems_event_send( Task_id[TASKID_DUMB], RTEMS_EVENT_3 );
154 status_code = rtems_event_send( Task_id[TASKID_DUMB], RTEMS_EVENT_3 );
155 }
155 }
156 nb_sm_f1 = 0;
156 nb_sm_f1 = 0;
157 }
157 }
158 spectral_matrix_regs->status = BIT_STATUS_F1_0; // [0000 0100]
158 spectral_matrix_regs->status = BIT_STATUS_F1_0; // [0000 0100]
159 break;
159 break;
160 case BIT_READY_1:
160 case BIT_READY_1:
161 full_ring_node = current_ring_node_sm_f1->previous;
161 full_ring_node = current_ring_node_sm_f1->previous;
162 full_ring_node->coarseTime = spectral_matrix_regs->f1_1_coarse_time;
162 full_ring_node->coarseTime = spectral_matrix_regs->f1_1_coarse_time;
163 full_ring_node->fineTime = spectral_matrix_regs->f1_1_fine_time;
163 full_ring_node->fineTime = spectral_matrix_regs->f1_1_fine_time;
164 current_ring_node_sm_f1 = current_ring_node_sm_f1->next;
164 current_ring_node_sm_f1 = current_ring_node_sm_f1->next;
165 spectral_matrix_regs->f1_1_address = current_ring_node_sm_f1->buffer_address;
165 spectral_matrix_regs->f1_1_address = current_ring_node_sm_f1->buffer_address;
166 // if there are enough ring nodes ready, wake up an AVFx task
166 // if there are enough ring nodes ready, wake up an AVFx task
167 nb_sm_f1 = nb_sm_f1 + 1;
167 nb_sm_f1 = nb_sm_f1 + 1;
168 if (nb_sm_f1 == NB_SM_BEFORE_AVF0_F1)
168 if (nb_sm_f1 == NB_SM_BEFORE_AVF0_F1)
169 {
169 {
170 ring_node_for_averaging_sm_f1 = full_ring_node;
170 ring_node_for_averaging_sm_f1 = full_ring_node;
171 if (rtems_event_send( Task_id[TASKID_AVF1], RTEMS_EVENT_0 ) != RTEMS_SUCCESSFUL)
171 if (rtems_event_send( Task_id[TASKID_AVF1], RTEMS_EVENT_0 ) != RTEMS_SUCCESSFUL)
172 {
172 {
173 status_code = rtems_event_send( Task_id[TASKID_DUMB], RTEMS_EVENT_3 );
173 status_code = rtems_event_send( Task_id[TASKID_DUMB], RTEMS_EVENT_3 );
174 }
174 }
175 nb_sm_f1 = 0;
175 nb_sm_f1 = 0;
176 }
176 }
177 spectral_matrix_regs->status = BIT_STATUS_F1_1; // [1000 0000]
177 spectral_matrix_regs->status = BIT_STATUS_F1_1; // [1000 0000]
178 break;
178 break;
179 default:
179 default:
180 break;
180 break;
181 }
181 }
182 }
182 }
183
183
184 void spectral_matrices_isr_f2( int statusReg )
184 void spectral_matrices_isr_f2( int statusReg )
185 {
185 {
186 unsigned char status;
186 unsigned char status;
187 rtems_status_code status_code;
187 rtems_status_code status_code;
188
188
189 status = (unsigned char) ((statusReg & BITS_STATUS_F2) >> SHIFT_4_BITS); // [0011 0000] get the status_ready_matrix_f2_x bits
189 status = (unsigned char) ((statusReg & BITS_STATUS_F2) >> SHIFT_4_BITS); // [0011 0000] get the status_ready_matrix_f2_x bits
190
190
191 switch(status)
191 switch(status)
192 {
192 {
193 case 0:
193 case 0:
194 break;
194 break;
195 case BIT_READY_0_1:
195 case BIT_READY_0_1:
196 // UNEXPECTED VALUE
196 // UNEXPECTED VALUE
197 spectral_matrix_regs->status = BITS_STATUS_F2; // [0011 0000]
197 spectral_matrix_regs->status = BITS_STATUS_F2; // [0011 0000]
198 status_code = rtems_event_send( Task_id[TASKID_DUMB], RTEMS_EVENT_11 );
198 status_code = rtems_event_send( Task_id[TASKID_DUMB], RTEMS_EVENT_11 );
199 break;
199 break;
200 case BIT_READY_0:
200 case BIT_READY_0:
201 ring_node_for_averaging_sm_f2 = current_ring_node_sm_f2->previous;
201 ring_node_for_averaging_sm_f2 = current_ring_node_sm_f2->previous;
202 current_ring_node_sm_f2 = current_ring_node_sm_f2->next;
202 current_ring_node_sm_f2 = current_ring_node_sm_f2->next;
203 ring_node_for_averaging_sm_f2->coarseTime = spectral_matrix_regs->f2_0_coarse_time;
203 ring_node_for_averaging_sm_f2->coarseTime = spectral_matrix_regs->f2_0_coarse_time;
204 ring_node_for_averaging_sm_f2->fineTime = spectral_matrix_regs->f2_0_fine_time;
204 ring_node_for_averaging_sm_f2->fineTime = spectral_matrix_regs->f2_0_fine_time;
205 spectral_matrix_regs->f2_0_address = current_ring_node_sm_f2->buffer_address;
205 spectral_matrix_regs->f2_0_address = current_ring_node_sm_f2->buffer_address;
206 spectral_matrix_regs->status = BIT_STATUS_F2_0; // [0001 0000]
206 spectral_matrix_regs->status = BIT_STATUS_F2_0; // [0001 0000]
207 if (rtems_event_send( Task_id[TASKID_AVF2], RTEMS_EVENT_0 ) != RTEMS_SUCCESSFUL)
207 if (rtems_event_send( Task_id[TASKID_AVF2], RTEMS_EVENT_0 ) != RTEMS_SUCCESSFUL)
208 {
208 {
209 status_code = rtems_event_send( Task_id[TASKID_DUMB], RTEMS_EVENT_3 );
209 status_code = rtems_event_send( Task_id[TASKID_DUMB], RTEMS_EVENT_3 );
210 }
210 }
211 break;
211 break;
212 case BIT_READY_1:
212 case BIT_READY_1:
213 ring_node_for_averaging_sm_f2 = current_ring_node_sm_f2->previous;
213 ring_node_for_averaging_sm_f2 = current_ring_node_sm_f2->previous;
214 current_ring_node_sm_f2 = current_ring_node_sm_f2->next;
214 current_ring_node_sm_f2 = current_ring_node_sm_f2->next;
215 ring_node_for_averaging_sm_f2->coarseTime = spectral_matrix_regs->f2_1_coarse_time;
215 ring_node_for_averaging_sm_f2->coarseTime = spectral_matrix_regs->f2_1_coarse_time;
216 ring_node_for_averaging_sm_f2->fineTime = spectral_matrix_regs->f2_1_fine_time;
216 ring_node_for_averaging_sm_f2->fineTime = spectral_matrix_regs->f2_1_fine_time;
217 spectral_matrix_regs->f2_1_address = current_ring_node_sm_f2->buffer_address;
217 spectral_matrix_regs->f2_1_address = current_ring_node_sm_f2->buffer_address;
218 spectral_matrix_regs->status = BIT_STATUS_F2_1; // [0010 0000]
218 spectral_matrix_regs->status = BIT_STATUS_F2_1; // [0010 0000]
219 if (rtems_event_send( Task_id[TASKID_AVF2], RTEMS_EVENT_0 ) != RTEMS_SUCCESSFUL)
219 if (rtems_event_send( Task_id[TASKID_AVF2], RTEMS_EVENT_0 ) != RTEMS_SUCCESSFUL)
220 {
220 {
221 status_code = rtems_event_send( Task_id[TASKID_DUMB], RTEMS_EVENT_3 );
221 status_code = rtems_event_send( Task_id[TASKID_DUMB], RTEMS_EVENT_3 );
222 }
222 }
223 break;
223 break;
224 default:
224 default:
225 break;
225 break;
226 }
226 }
227 }
227 }
228
228
229 void spectral_matrix_isr_error_handler( int statusReg )
229 void spectral_matrix_isr_error_handler( int statusReg )
230 {
230 {
231 // STATUS REGISTER
231 // STATUS REGISTER
232 // input_fifo_write(2) *** input_fifo_write(1) *** input_fifo_write(0)
232 // input_fifo_write(2) *** input_fifo_write(1) *** input_fifo_write(0)
233 // 10 9 8
233 // 10 9 8
234 // buffer_full ** [bad_component_err] ** f2_1 ** f2_0 ** f1_1 ** f1_0 ** f0_1 ** f0_0
234 // buffer_full ** [bad_component_err] ** f2_1 ** f2_0 ** f1_1 ** f1_0 ** f0_1 ** f0_0
235 // 7 6 5 4 3 2 1 0
235 // 7 6 5 4 3 2 1 0
236 // [bad_component_err] not defined in the last version of the VHDL code
236 // [bad_component_err] not defined in the last version of the VHDL code
237
237
238 rtems_status_code status_code;
238 rtems_status_code status_code;
239
239
240 //***************************************************
240 //***************************************************
241 // the ASM status register is copied in the HK packet
241 // the ASM status register is copied in the HK packet
242 housekeeping_packet.hk_lfr_vhdl_aa_sm = (unsigned char) ((statusReg & BITS_HK_AA_SM) >> SHIFT_7_BITS); // [0111 1000 0000]
242 housekeeping_packet.hk_lfr_vhdl_aa_sm = (unsigned char) ((statusReg & BITS_HK_AA_SM) >> SHIFT_7_BITS); // [0111 1000 0000]
243
243
244 if (statusReg & BITS_SM_ERR) // [0111 1100 0000]
244 if (statusReg & BITS_SM_ERR) // [0111 1100 0000]
245 {
245 {
246 status_code = rtems_event_send( Task_id[TASKID_DUMB], RTEMS_EVENT_8 );
246 status_code = rtems_event_send( Task_id[TASKID_DUMB], RTEMS_EVENT_8 );
247 }
247 }
248
248
249 spectral_matrix_regs->status = spectral_matrix_regs->status & BITS_SM_ERR;
249 spectral_matrix_regs->status = spectral_matrix_regs->status & BITS_SM_ERR;
250
250
251 }
251 }
252
252
253 rtems_isr spectral_matrices_isr( rtems_vector_number vector )
253 rtems_isr spectral_matrices_isr( rtems_vector_number vector )
254 {
254 {
255 // STATUS REGISTER
255 // STATUS REGISTER
256 // input_fifo_write(2) *** input_fifo_write(1) *** input_fifo_write(0)
256 // input_fifo_write(2) *** input_fifo_write(1) *** input_fifo_write(0)
257 // 10 9 8
257 // 10 9 8
258 // buffer_full ** bad_component_err ** f2_1 ** f2_0 ** f1_1 ** f1_0 ** f0_1 ** f0_0
258 // buffer_full ** bad_component_err ** f2_1 ** f2_0 ** f1_1 ** f1_0 ** f0_1 ** f0_0
259 // 7 6 5 4 3 2 1 0
259 // 7 6 5 4 3 2 1 0
260
260
261 int statusReg;
261 int statusReg;
262
262
263 static restartState state = WAIT_FOR_F2;
263 static restartState state = WAIT_FOR_F2;
264
264
265 statusReg = spectral_matrix_regs->status;
265 statusReg = spectral_matrix_regs->status;
266
266
267 if (thisIsAnASMRestart == 0)
267 if (thisIsAnASMRestart == 0)
268 { // this is not a restart sequence, process incoming matrices normally
268 { // this is not a restart sequence, process incoming matrices normally
269 spectral_matrices_isr_f0( statusReg );
269 spectral_matrices_isr_f0( statusReg );
270
270
271 spectral_matrices_isr_f1( statusReg );
271 spectral_matrices_isr_f1( statusReg );
272
272
273 spectral_matrices_isr_f2( statusReg );
273 spectral_matrices_isr_f2( statusReg );
274 }
274 }
275 else
275 else
276 { // a restart sequence has to be launched
276 { // a restart sequence has to be launched
277 switch (state) {
277 switch (state) {
278 case WAIT_FOR_F2:
278 case WAIT_FOR_F2:
279 if ((statusReg & BITS_STATUS_F2) != INIT_CHAR) // [0011 0000] check the status_ready_matrix_f2_x bits
279 if ((statusReg & BITS_STATUS_F2) != INIT_CHAR) // [0011 0000] check the status_ready_matrix_f2_x bits
280 {
280 {
281 state = WAIT_FOR_F1;
281 state = WAIT_FOR_F1;
282 }
282 }
283 break;
283 break;
284 case WAIT_FOR_F1:
284 case WAIT_FOR_F1:
285 if ((statusReg & BITS_STATUS_F1) != INIT_CHAR) // [0000 1100] check the status_ready_matrix_f1_x bits
285 if ((statusReg & BITS_STATUS_F1) != INIT_CHAR) // [0000 1100] check the status_ready_matrix_f1_x bits
286 {
286 {
287 state = WAIT_FOR_F0;
287 state = WAIT_FOR_F0;
288 }
288 }
289 break;
289 break;
290 case WAIT_FOR_F0:
290 case WAIT_FOR_F0:
291 if ((statusReg & BITS_STATUS_F0) != INIT_CHAR) // [0000 0011] check the status_ready_matrix_f0_x bits
291 if ((statusReg & BITS_STATUS_F0) != INIT_CHAR) // [0000 0011] check the status_ready_matrix_f0_x bits
292 {
292 {
293 state = WAIT_FOR_F2;
293 state = WAIT_FOR_F2;
294 thisIsAnASMRestart = 0;
294 thisIsAnASMRestart = 0;
295 }
295 }
296 break;
296 break;
297 default:
297 default:
298 break;
298 break;
299 }
299 }
300 reset_sm_status();
300 reset_sm_status();
301 }
301 }
302
302
303 spectral_matrix_isr_error_handler( statusReg );
303 spectral_matrix_isr_error_handler( statusReg );
304
304
305 }
305 }
306
306
307 //******************
307 //******************
308 // Spectral Matrices
308 // Spectral Matrices
309
309
310 void reset_nb_sm( void )
310 void reset_nb_sm( void )
311 {
311 {
312 nb_sm_f0 = 0;
312 nb_sm_f0 = 0;
313 nb_sm_f0_aux_f1 = 0;
313 nb_sm_f0_aux_f1 = 0;
314 nb_sm_f0_aux_f2 = 0;
314 nb_sm_f0_aux_f2 = 0;
315
315
316 nb_sm_f1 = 0;
316 nb_sm_f1 = 0;
317 }
317 }
318
318
319 void SM_init_rings( void )
319 void SM_init_rings( void )
320 {
320 {
321 init_ring( sm_ring_f0, NB_RING_NODES_SM_F0, sm_f0, TOTAL_SIZE_SM );
321 init_ring( sm_ring_f0, NB_RING_NODES_SM_F0, sm_f0, TOTAL_SIZE_SM );
322 init_ring( sm_ring_f1, NB_RING_NODES_SM_F1, sm_f1, TOTAL_SIZE_SM );
322 init_ring( sm_ring_f1, NB_RING_NODES_SM_F1, sm_f1, TOTAL_SIZE_SM );
323 init_ring( sm_ring_f2, NB_RING_NODES_SM_F2, sm_f2, TOTAL_SIZE_SM );
323 init_ring( sm_ring_f2, NB_RING_NODES_SM_F2, sm_f2, TOTAL_SIZE_SM );
324
324
325 DEBUG_PRINTF1("sm_ring_f0 @%x\n", (unsigned int) sm_ring_f0)
325 DEBUG_PRINTF1("sm_ring_f0 @%x\n", (unsigned int) sm_ring_f0)
326 DEBUG_PRINTF1("sm_ring_f1 @%x\n", (unsigned int) sm_ring_f1)
326 DEBUG_PRINTF1("sm_ring_f1 @%x\n", (unsigned int) sm_ring_f1)
327 DEBUG_PRINTF1("sm_ring_f2 @%x\n", (unsigned int) sm_ring_f2)
327 DEBUG_PRINTF1("sm_ring_f2 @%x\n", (unsigned int) sm_ring_f2)
328 DEBUG_PRINTF1("sm_f0 @%x\n", (unsigned int) sm_f0)
328 DEBUG_PRINTF1("sm_f0 @%x\n", (unsigned int) sm_f0)
329 DEBUG_PRINTF1("sm_f1 @%x\n", (unsigned int) sm_f1)
329 DEBUG_PRINTF1("sm_f1 @%x\n", (unsigned int) sm_f1)
330 DEBUG_PRINTF1("sm_f2 @%x\n", (unsigned int) sm_f2)
330 DEBUG_PRINTF1("sm_f2 @%x\n", (unsigned int) sm_f2)
331 }
331 }
332
332
333 void ASM_generic_init_ring( ring_node_asm *ring, unsigned char nbNodes )
333 void ASM_generic_init_ring( ring_node_asm *ring, unsigned char nbNodes )
334 {
334 {
335 unsigned char i;
335 unsigned char i;
336
336
337 ring[ nbNodes - 1 ].next
337 ring[ nbNodes - 1 ].next
338 = (ring_node_asm*) &ring[ 0 ];
338 = (ring_node_asm*) &ring[ 0 ];
339
339
340 for(i=0; i<nbNodes-1; i++)
340 for(i=0; i<nbNodes-1; i++)
341 {
341 {
342 ring[ i ].next = (ring_node_asm*) &ring[ i + 1 ];
342 ring[ i ].next = (ring_node_asm*) &ring[ i + 1 ];
343 }
343 }
344 }
344 }
345
345
346 void SM_reset_current_ring_nodes( void )
346 void SM_reset_current_ring_nodes( void )
347 {
347 {
348 current_ring_node_sm_f0 = sm_ring_f0[0].next;
348 current_ring_node_sm_f0 = sm_ring_f0[0].next;
349 current_ring_node_sm_f1 = sm_ring_f1[0].next;
349 current_ring_node_sm_f1 = sm_ring_f1[0].next;
350 current_ring_node_sm_f2 = sm_ring_f2[0].next;
350 current_ring_node_sm_f2 = sm_ring_f2[0].next;
351
351
352 ring_node_for_averaging_sm_f0 = NULL;
352 ring_node_for_averaging_sm_f0 = NULL;
353 ring_node_for_averaging_sm_f1 = NULL;
353 ring_node_for_averaging_sm_f1 = NULL;
354 ring_node_for_averaging_sm_f2 = NULL;
354 ring_node_for_averaging_sm_f2 = NULL;
355 }
355 }
356
356
357 //*****************
357 //*****************
358 // Basic Parameters
358 // Basic Parameters
359
359
360 void BP_init_header( bp_packet *packet,
360 void BP_init_header( bp_packet *packet,
361 unsigned int apid, unsigned char sid,
361 unsigned int apid, unsigned char sid,
362 unsigned int packetLength, unsigned char blkNr )
362 unsigned int packetLength, unsigned char blkNr )
363 {
363 {
364 packet->targetLogicalAddress = CCSDS_DESTINATION_ID;
364 packet->targetLogicalAddress = CCSDS_DESTINATION_ID;
365 packet->protocolIdentifier = CCSDS_PROTOCOLE_ID;
365 packet->protocolIdentifier = CCSDS_PROTOCOLE_ID;
366 packet->reserved = INIT_CHAR;
366 packet->reserved = INIT_CHAR;
367 packet->userApplication = CCSDS_USER_APP;
367 packet->userApplication = CCSDS_USER_APP;
368 packet->packetID[0] = (unsigned char) (apid >> SHIFT_1_BYTE);
368 packet->packetID[0] = (unsigned char) (apid >> SHIFT_1_BYTE);
369 packet->packetID[1] = (unsigned char) (apid);
369 packet->packetID[1] = (unsigned char) (apid);
370 packet->packetSequenceControl[0] = TM_PACKET_SEQ_CTRL_STANDALONE;
370 packet->packetSequenceControl[0] = TM_PACKET_SEQ_CTRL_STANDALONE;
371 packet->packetSequenceControl[1] = INIT_CHAR;
371 packet->packetSequenceControl[1] = INIT_CHAR;
372 packet->packetLength[0] = (unsigned char) (packetLength >> SHIFT_1_BYTE);
372 packet->packetLength[0] = (unsigned char) (packetLength >> SHIFT_1_BYTE);
373 packet->packetLength[1] = (unsigned char) (packetLength);
373 packet->packetLength[1] = (unsigned char) (packetLength);
374 // DATA FIELD HEADER
374 // DATA FIELD HEADER
375 packet->spare1_pusVersion_spare2 = SPARE1_PUSVERSION_SPARE2;
375 packet->spare1_pusVersion_spare2 = SPARE1_PUSVERSION_SPARE2;
376 packet->serviceType = TM_TYPE_LFR_SCIENCE; // service type
376 packet->serviceType = TM_TYPE_LFR_SCIENCE; // service type
377 packet->serviceSubType = TM_SUBTYPE_LFR_SCIENCE_3; // service subtype
377 packet->serviceSubType = TM_SUBTYPE_LFR_SCIENCE_3; // service subtype
378 packet->destinationID = TM_DESTINATION_ID_GROUND;
378 packet->destinationID = TM_DESTINATION_ID_GROUND;
379 packet->time[BYTE_0] = INIT_CHAR;
379 packet->time[BYTE_0] = INIT_CHAR;
380 packet->time[BYTE_1] = INIT_CHAR;
380 packet->time[BYTE_1] = INIT_CHAR;
381 packet->time[BYTE_2] = INIT_CHAR;
381 packet->time[BYTE_2] = INIT_CHAR;
382 packet->time[BYTE_3] = INIT_CHAR;
382 packet->time[BYTE_3] = INIT_CHAR;
383 packet->time[BYTE_4] = INIT_CHAR;
383 packet->time[BYTE_4] = INIT_CHAR;
384 packet->time[BYTE_5] = INIT_CHAR;
384 packet->time[BYTE_5] = INIT_CHAR;
385 // AUXILIARY DATA HEADER
385 // AUXILIARY DATA HEADER
386 packet->sid = sid;
386 packet->sid = sid;
387 packet->pa_bia_status_info = INIT_CHAR;
387 packet->pa_bia_status_info = INIT_CHAR;
388 packet->sy_lfr_common_parameters_spare = INIT_CHAR;
388 packet->sy_lfr_common_parameters_spare = INIT_CHAR;
389 packet->sy_lfr_common_parameters = INIT_CHAR;
389 packet->sy_lfr_common_parameters = INIT_CHAR;
390 packet->acquisitionTime[BYTE_0] = INIT_CHAR;
390 packet->acquisitionTime[BYTE_0] = INIT_CHAR;
391 packet->acquisitionTime[BYTE_1] = INIT_CHAR;
391 packet->acquisitionTime[BYTE_1] = INIT_CHAR;
392 packet->acquisitionTime[BYTE_2] = INIT_CHAR;
392 packet->acquisitionTime[BYTE_2] = INIT_CHAR;
393 packet->acquisitionTime[BYTE_3] = INIT_CHAR;
393 packet->acquisitionTime[BYTE_3] = INIT_CHAR;
394 packet->acquisitionTime[BYTE_4] = INIT_CHAR;
394 packet->acquisitionTime[BYTE_4] = INIT_CHAR;
395 packet->acquisitionTime[BYTE_5] = INIT_CHAR;
395 packet->acquisitionTime[BYTE_5] = INIT_CHAR;
396 packet->pa_lfr_bp_blk_nr[0] = INIT_CHAR; // BLK_NR MSB
396 packet->pa_lfr_bp_blk_nr[0] = INIT_CHAR; // BLK_NR MSB
397 packet->pa_lfr_bp_blk_nr[1] = blkNr; // BLK_NR LSB
397 packet->pa_lfr_bp_blk_nr[1] = blkNr; // BLK_NR LSB
398 }
398 }
399
399
400 void BP_init_header_with_spare( bp_packet_with_spare *packet,
400 void BP_init_header_with_spare( bp_packet_with_spare *packet,
401 unsigned int apid, unsigned char sid,
401 unsigned int apid, unsigned char sid,
402 unsigned int packetLength , unsigned char blkNr)
402 unsigned int packetLength , unsigned char blkNr)
403 {
403 {
404 packet->targetLogicalAddress = CCSDS_DESTINATION_ID;
404 packet->targetLogicalAddress = CCSDS_DESTINATION_ID;
405 packet->protocolIdentifier = CCSDS_PROTOCOLE_ID;
405 packet->protocolIdentifier = CCSDS_PROTOCOLE_ID;
406 packet->reserved = INIT_CHAR;
406 packet->reserved = INIT_CHAR;
407 packet->userApplication = CCSDS_USER_APP;
407 packet->userApplication = CCSDS_USER_APP;
408 packet->packetID[0] = (unsigned char) (apid >> SHIFT_1_BYTE);
408 packet->packetID[0] = (unsigned char) (apid >> SHIFT_1_BYTE);
409 packet->packetID[1] = (unsigned char) (apid);
409 packet->packetID[1] = (unsigned char) (apid);
410 packet->packetSequenceControl[0] = TM_PACKET_SEQ_CTRL_STANDALONE;
410 packet->packetSequenceControl[0] = TM_PACKET_SEQ_CTRL_STANDALONE;
411 packet->packetSequenceControl[1] = INIT_CHAR;
411 packet->packetSequenceControl[1] = INIT_CHAR;
412 packet->packetLength[0] = (unsigned char) (packetLength >> SHIFT_1_BYTE);
412 packet->packetLength[0] = (unsigned char) (packetLength >> SHIFT_1_BYTE);
413 packet->packetLength[1] = (unsigned char) (packetLength);
413 packet->packetLength[1] = (unsigned char) (packetLength);
414 // DATA FIELD HEADER
414 // DATA FIELD HEADER
415 packet->spare1_pusVersion_spare2 = SPARE1_PUSVERSION_SPARE2;
415 packet->spare1_pusVersion_spare2 = SPARE1_PUSVERSION_SPARE2;
416 packet->serviceType = TM_TYPE_LFR_SCIENCE; // service type
416 packet->serviceType = TM_TYPE_LFR_SCIENCE; // service type
417 packet->serviceSubType = TM_SUBTYPE_LFR_SCIENCE_3; // service subtype
417 packet->serviceSubType = TM_SUBTYPE_LFR_SCIENCE_3; // service subtype
418 packet->destinationID = TM_DESTINATION_ID_GROUND;
418 packet->destinationID = TM_DESTINATION_ID_GROUND;
419 // AUXILIARY DATA HEADER
419 // AUXILIARY DATA HEADER
420 packet->sid = sid;
420 packet->sid = sid;
421 packet->pa_bia_status_info = INIT_CHAR;
421 packet->pa_bia_status_info = INIT_CHAR;
422 packet->sy_lfr_common_parameters_spare = INIT_CHAR;
422 packet->sy_lfr_common_parameters_spare = INIT_CHAR;
423 packet->sy_lfr_common_parameters = INIT_CHAR;
423 packet->sy_lfr_common_parameters = INIT_CHAR;
424 packet->time[BYTE_0] = INIT_CHAR;
424 packet->time[BYTE_0] = INIT_CHAR;
425 packet->time[BYTE_1] = INIT_CHAR;
425 packet->time[BYTE_1] = INIT_CHAR;
426 packet->time[BYTE_2] = INIT_CHAR;
426 packet->time[BYTE_2] = INIT_CHAR;
427 packet->time[BYTE_3] = INIT_CHAR;
427 packet->time[BYTE_3] = INIT_CHAR;
428 packet->time[BYTE_4] = INIT_CHAR;
428 packet->time[BYTE_4] = INIT_CHAR;
429 packet->time[BYTE_5] = INIT_CHAR;
429 packet->time[BYTE_5] = INIT_CHAR;
430 packet->source_data_spare = INIT_CHAR;
430 packet->source_data_spare = INIT_CHAR;
431 packet->pa_lfr_bp_blk_nr[0] = INIT_CHAR; // BLK_NR MSB
431 packet->pa_lfr_bp_blk_nr[0] = INIT_CHAR; // BLK_NR MSB
432 packet->pa_lfr_bp_blk_nr[1] = blkNr; // BLK_NR LSB
432 packet->pa_lfr_bp_blk_nr[1] = blkNr; // BLK_NR LSB
433 }
433 }
434
434
435 void BP_send(char *data, rtems_id queue_id, unsigned int nbBytesToSend, unsigned int sid )
435 void BP_send(char *data, rtems_id queue_id, unsigned int nbBytesToSend, unsigned int sid )
436 {
436 {
437 rtems_status_code status;
437 rtems_status_code status;
438
438
439 // SEND PACKET
439 // SEND PACKET
440 status = rtems_message_queue_send( queue_id, data, nbBytesToSend);
440 status = rtems_message_queue_send( queue_id, data, nbBytesToSend);
441 if (status != RTEMS_SUCCESSFUL)
441 if (status != RTEMS_SUCCESSFUL)
442 {
442 {
443 PRINTF1("ERR *** in BP_send *** ERR %d\n", (int) status)
443 PRINTF1("ERR *** in BP_send *** ERR %d\n", (int) status)
444 }
444 }
445 }
445 }
446
446
447 void BP_send_s1_s2(char *data, rtems_id queue_id, unsigned int nbBytesToSend, unsigned int sid )
447 void BP_send_s1_s2(char *data, rtems_id queue_id, unsigned int nbBytesToSend, unsigned int sid )
448 {
448 {
449 /** This function is used to send the BP paquets when needed.
449 /** This function is used to send the BP paquets when needed.
450 *
450 *
451 * @param transitionCoarseTime is the requested transition time contained in the TC_LFR_ENTER_MODE
451 * @param transitionCoarseTime is the requested transition time contained in the TC_LFR_ENTER_MODE
452 *
452 *
453 * @return void
453 * @return void
454 *
454 *
455 * SBM1 and SBM2 paquets are sent depending on the type of the LFR mode transition.
455 * SBM1 and SBM2 paquets are sent depending on the type of the LFR mode transition.
456 * BURST paquets are sent everytime.
456 * BURST paquets are sent everytime.
457 *
457 *
458 */
458 */
459
459
460 rtems_status_code status;
460 rtems_status_code status;
461
461
462 // SEND PACKET
462 // SEND PACKET
463 // before lastValidTransitionDate, the data are drops even if they are ready
463 // before lastValidTransitionDate, the data are drops even if they are ready
464 // this guarantees that no SBM packets will be received before the requested enter mode time
464 // this guarantees that no SBM packets will be received before the requested enter mode time
465 if ( time_management_regs->coarse_time >= lastValidEnterModeTime)
465 if ( time_management_regs->coarse_time >= lastValidEnterModeTime)
466 {
466 {
467 status = rtems_message_queue_send( queue_id, data, nbBytesToSend);
467 status = rtems_message_queue_send( queue_id, data, nbBytesToSend);
468 if (status != RTEMS_SUCCESSFUL)
468 if (status != RTEMS_SUCCESSFUL)
469 {
469 {
470 PRINTF1("ERR *** in BP_send *** ERR %d\n", (int) status)
470 PRINTF1("ERR *** in BP_send *** ERR %d\n", (int) status)
471 }
471 }
472 }
472 }
473 }
473 }
474
474
475 //******************
475 //******************
476 // general functions
476 // general functions
477
477
478 void reset_sm_status( void )
478 void reset_sm_status( void )
479 {
479 {
480 // error
480 // error
481 // 10 --------------- 9 ---------------- 8 ---------------- 7 ---------
481 // 10 --------------- 9 ---------------- 8 ---------------- 7 ---------
482 // input_fif0_write_2 input_fifo_write_1 input_fifo_write_0 buffer_full
482 // input_fif0_write_2 input_fifo_write_1 input_fifo_write_0 buffer_full
483 // ---------- 5 -- 4 -- 3 -- 2 -- 1 -- 0 --
483 // ---------- 5 -- 4 -- 3 -- 2 -- 1 -- 0 --
484 // ready bits f2_1 f2_0 f1_1 f1_1 f0_1 f0_0
484 // ready bits f2_1 f2_0 f1_1 f1_1 f0_1 f0_0
485
485
486 spectral_matrix_regs->status = BITS_STATUS_REG; // [0111 1111 1111]
486 spectral_matrix_regs->status = BITS_STATUS_REG; // [0111 1111 1111]
487 }
487 }
488
488
489 void reset_spectral_matrix_regs( void )
489 void reset_spectral_matrix_regs( void )
490 {
490 {
491 /** This function resets the spectral matrices module registers.
491 /** This function resets the spectral matrices module registers.
492 *
492 *
493 * The registers affected by this function are located at the following offset addresses:
493 * The registers affected by this function are located at the following offset addresses:
494 *
494 *
495 * - 0x00 config
495 * - 0x00 config
496 * - 0x04 status
496 * - 0x04 status
497 * - 0x08 matrixF0_Address0
497 * - 0x08 matrixF0_Address0
498 * - 0x10 matrixFO_Address1
498 * - 0x10 matrixFO_Address1
499 * - 0x14 matrixF1_Address
499 * - 0x14 matrixF1_Address
500 * - 0x18 matrixF2_Address
500 * - 0x18 matrixF2_Address
501 *
501 *
502 */
502 */
503
503
504 set_sm_irq_onError( 0 );
504 set_sm_irq_onError( 0 );
505
505
506 set_sm_irq_onNewMatrix( 0 );
506 set_sm_irq_onNewMatrix( 0 );
507
507
508 reset_sm_status();
508 reset_sm_status();
509
509
510 // F1
510 // F1
511 spectral_matrix_regs->f0_0_address = current_ring_node_sm_f0->previous->buffer_address;
511 spectral_matrix_regs->f0_0_address = current_ring_node_sm_f0->previous->buffer_address;
512 spectral_matrix_regs->f0_1_address = current_ring_node_sm_f0->buffer_address;
512 spectral_matrix_regs->f0_1_address = current_ring_node_sm_f0->buffer_address;
513 // F2
513 // F2
514 spectral_matrix_regs->f1_0_address = current_ring_node_sm_f1->previous->buffer_address;
514 spectral_matrix_regs->f1_0_address = current_ring_node_sm_f1->previous->buffer_address;
515 spectral_matrix_regs->f1_1_address = current_ring_node_sm_f1->buffer_address;
515 spectral_matrix_regs->f1_1_address = current_ring_node_sm_f1->buffer_address;
516 // F3
516 // F3
517 spectral_matrix_regs->f2_0_address = current_ring_node_sm_f2->previous->buffer_address;
517 spectral_matrix_regs->f2_0_address = current_ring_node_sm_f2->previous->buffer_address;
518 spectral_matrix_regs->f2_1_address = current_ring_node_sm_f2->buffer_address;
518 spectral_matrix_regs->f2_1_address = current_ring_node_sm_f2->buffer_address;
519
519
520 spectral_matrix_regs->matrix_length = DEFAULT_MATRIX_LENGTH; // 25 * 128 / 16 = 200 = 0xc8
520 spectral_matrix_regs->matrix_length = DEFAULT_MATRIX_LENGTH; // 25 * 128 / 16 = 200 = 0xc8
521 }
521 }
522
522
523 void set_time( unsigned char *time, unsigned char * timeInBuffer )
523 void set_time( unsigned char *time, unsigned char * timeInBuffer )
524 {
524 {
525 time[BYTE_0] = timeInBuffer[BYTE_0];
525 time[BYTE_0] = timeInBuffer[BYTE_0];
526 time[BYTE_1] = timeInBuffer[BYTE_1];
526 time[BYTE_1] = timeInBuffer[BYTE_1];
527 time[BYTE_2] = timeInBuffer[BYTE_2];
527 time[BYTE_2] = timeInBuffer[BYTE_2];
528 time[BYTE_3] = timeInBuffer[BYTE_3];
528 time[BYTE_3] = timeInBuffer[BYTE_3];
529 time[BYTE_4] = timeInBuffer[BYTE_6];
529 time[BYTE_4] = timeInBuffer[BYTE_6];
530 time[BYTE_5] = timeInBuffer[BYTE_7];
530 time[BYTE_5] = timeInBuffer[BYTE_7];
531 }
531 }
532
532
533 unsigned long long int get_acquisition_time( unsigned char *timePtr )
533 unsigned long long int get_acquisition_time( unsigned char *timePtr )
534 {
534 {
535 unsigned long long int acquisitionTimeAslong;
535 unsigned long long int acquisitionTimeAslong;
536 acquisitionTimeAslong = INIT_CHAR;
536 acquisitionTimeAslong = INIT_CHAR;
537 acquisitionTimeAslong =
537 acquisitionTimeAslong =
538 ( (unsigned long long int) (timePtr[BYTE_0] & SYNC_BIT_MASK) << SHIFT_5_BYTES ) // [0111 1111] mask the synchronization bit
538 ( (unsigned long long int) (timePtr[BYTE_0] & SYNC_BIT_MASK) << SHIFT_5_BYTES ) // [0111 1111] mask the synchronization bit
539 + ( (unsigned long long int) timePtr[BYTE_1] << SHIFT_4_BYTES )
539 + ( (unsigned long long int) timePtr[BYTE_1] << SHIFT_4_BYTES )
540 + ( (unsigned long long int) timePtr[BYTE_2] << SHIFT_3_BYTES )
540 + ( (unsigned long long int) timePtr[BYTE_2] << SHIFT_3_BYTES )
541 + ( (unsigned long long int) timePtr[BYTE_3] << SHIFT_2_BYTES )
541 + ( (unsigned long long int) timePtr[BYTE_3] << SHIFT_2_BYTES )
542 + ( (unsigned long long int) timePtr[BYTE_6] << SHIFT_1_BYTE )
542 + ( (unsigned long long int) timePtr[BYTE_6] << SHIFT_1_BYTE )
543 + ( (unsigned long long int) timePtr[BYTE_7] );
543 + ( (unsigned long long int) timePtr[BYTE_7] );
544 return acquisitionTimeAslong;
544 return acquisitionTimeAslong;
545 }
545 }
546
546
547 unsigned char getSID( rtems_event_set event )
547 unsigned char getSID( rtems_event_set event )
548 {
548 {
549 unsigned char sid;
549 unsigned char sid;
550
550
551 rtems_event_set eventSetBURST;
551 rtems_event_set eventSetBURST;
552 rtems_event_set eventSetSBM;
552 rtems_event_set eventSetSBM;
553
553
554 sid = 0;
554 sid = 0;
555
555
556 //******
556 //******
557 // BURST
557 // BURST
558 eventSetBURST = RTEMS_EVENT_BURST_BP1_F0
558 eventSetBURST = RTEMS_EVENT_BURST_BP1_F0
559 | RTEMS_EVENT_BURST_BP1_F1
559 | RTEMS_EVENT_BURST_BP1_F1
560 | RTEMS_EVENT_BURST_BP2_F0
560 | RTEMS_EVENT_BURST_BP2_F0
561 | RTEMS_EVENT_BURST_BP2_F1;
561 | RTEMS_EVENT_BURST_BP2_F1;
562
562
563 //****
563 //****
564 // SBM
564 // SBM
565 eventSetSBM = RTEMS_EVENT_SBM_BP1_F0
565 eventSetSBM = RTEMS_EVENT_SBM_BP1_F0
566 | RTEMS_EVENT_SBM_BP1_F1
566 | RTEMS_EVENT_SBM_BP1_F1
567 | RTEMS_EVENT_SBM_BP2_F0
567 | RTEMS_EVENT_SBM_BP2_F0
568 | RTEMS_EVENT_SBM_BP2_F1;
568 | RTEMS_EVENT_SBM_BP2_F1;
569
569
570 if (event & eventSetBURST)
570 if (event & eventSetBURST)
571 {
571 {
572 sid = SID_BURST_BP1_F0;
572 sid = SID_BURST_BP1_F0;
573 }
573 }
574 else if (event & eventSetSBM)
574 else if (event & eventSetSBM)
575 {
575 {
576 sid = SID_SBM1_BP1_F0;
576 sid = SID_SBM1_BP1_F0;
577 }
577 }
578 else
578 else
579 {
579 {
580 sid = 0;
580 sid = 0;
581 }
581 }
582
582
583 return sid;
583 return sid;
584 }
584 }
585
585
586 void extractReImVectors( float *inputASM, float *outputASM, unsigned int asmComponent )
586 void extractReImVectors( float *inputASM, float *outputASM, unsigned int asmComponent )
587 {
587 {
588 unsigned int i;
588 unsigned int i;
589 float re;