##// END OF EJS Templates
Snapshot resynchro rewritten, drift is measured one snapshot in two...
paul -
r253:cc5f75e74b54 R3a
parent child
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@@ -1,192 +1,192
1 #ifndef GSCMEMORY_HPP_
1 #ifndef GSCMEMORY_HPP_
2 #define GSCMEMORY_HPP_
2 #define GSCMEMORY_HPP_
3
3
4 #ifndef LEON3
4 #ifndef LEON3
5 #define LEON3
5 #define LEON3
6 #endif
6 #endif
7
7
8 #define REGS_ADDR_PLUGANDPLAY 0xFFFFF000
8 #define REGS_ADDR_PLUGANDPLAY 0xFFFFF000
9 #define ASR16_REG_ADDRESS 0x90400040 // Ancillary State Register 16 = Register protection control register (FT only)
9 #define ASR16_REG_ADDRESS 0x90400040 // Ancillary State Register 16 = Register protection control register (FT only)
10
10
11 #define DEVICEID_LEON3 0x003
11 #define DEVICEID_LEON3 0x003
12 #define DEVICEID_LEON3FT 0x053
12 #define DEVICEID_LEON3FT 0x053
13 #define VENDORID_GAISLER 0x01
13 #define VENDORID_GAISLER 0x01
14
14
15 // CCR
15 // CCR
16 #define POS_ITE 12
16 #define POS_ITE 12
17 #define COUNTER_FIELD_ITE 0x00003000 // 0000 0000 0000 0000 0011 0000 0000 0000
17 #define COUNTER_FIELD_ITE 0x00003000 // 0000 0000 0000 0000 0011 0000 0000 0000
18 #define COUNTER_MASK_ITE 0xffffcfff // 1111 1111 1111 1111 1100 1111 1111 1111
18 #define COUNTER_MASK_ITE 0xffffcfff // 1111 1111 1111 1111 1100 1111 1111 1111
19 #define POS_IDE 10
19 #define POS_IDE 10
20 #define COUNTER_FIELD_IDE 0x00000c00 // 0000 0000 0000 0000 0000 1100 0000 0000
20 #define COUNTER_FIELD_IDE 0x00000c00 // 0000 0000 0000 0000 0000 1100 0000 0000
21 #define COUNTER_MASK_IDE 0xfffff3ff // 1111 1111 1111 1111 1111 0011 1111 1111
21 #define COUNTER_MASK_IDE 0xfffff3ff // 1111 1111 1111 1111 1111 0011 1111 1111
22 //
22 //
23 #define POS_DTE 8
23 #define POS_DTE 8
24 #define COUNTER_FIELD_DTE 0x00000300 // 0000 0000 0000 0000 0000 0011 0000 0000
24 #define COUNTER_FIELD_DTE 0x00000300 // 0000 0000 0000 0000 0000 0011 0000 0000
25 #define COUNTER_MASK_DTE 0xfffffcff // 1111 1111 1111 1111 1111 1100 1111 1111
25 #define COUNTER_MASK_DTE 0xfffffcff // 1111 1111 1111 1111 1111 1100 1111 1111
26 #define POS_DDE 6
26 #define POS_DDE 6
27 #define COUNTER_FIELD_DDE 0x000000c0 // 0000 0000 0000 0000 0000 0000 1100 0000
27 #define COUNTER_FIELD_DDE 0x000000c0 // 0000 0000 0000 0000 0000 0000 1100 0000
28 #define COUNTER_MASK_DDE 0xffffff3f // 1111 1111 1111 1111 1111 1111 0011 1111
28 #define COUNTER_MASK_DDE 0xffffff3f // 1111 1111 1111 1111 1111 1111 0011 1111
29
29
30 // ASR16
30 // ASR16
31 #define POS_FPRF 27
31 #define POS_FPRF 27
32 #define COUNTER_FIELD_FPRF 0x38000000 // 0011 1000 0000 0000 0000 0000 0000 0000
32 #define COUNTER_FIELD_FPRF 0x38000000 // 0011 1000 0000 0000 0000 0000 0000 0000
33 #define COUNTER_MASK_FPRF 0xc7ffffff // 1100 0111 1111 1111 1111 1111 1111 1111
33 #define COUNTER_MASK_FPRF 0xc7ffffff // 1100 0111 1111 1111 1111 1111 1111 1111
34 #define POS_IURF 11
34 #define POS_IURF 11
35 #define COUNTER_FIELD_IURF 0x00003800 // 0000 0000 0000 0000 0011 1000 0000 0000
35 #define COUNTER_FIELD_IURF 0x00003800 // 0000 0000 0000 0000 0011 1000 0000 0000
36 #define COUNTER_MASK_IURF 0xffffc7ff // 1111 1111 1111 1111 1100 0111 1111 1111
36 #define COUNTER_MASK_IURF 0xffffc7ff // 1111 1111 1111 1111 1100 0111 1111 1111
37
37
38 volatile unsigned int *asr16Ptr = (volatile unsigned int *) ASR16_REG_ADDRESS;
38 volatile unsigned int *asr16Ptr = (volatile unsigned int *) ASR16_REG_ADDRESS;
39
39
40 static inline void flushCache()
40 static inline void flushCache()
41 {
41 {
42 /**
42 /**
43 * Flush the data cache and the instruction cache.
43 * Flush the data cache and the instruction cache.
44 *
44 *
45 * @param void
45 * @param void
46 *
46 *
47 * @return void
47 * @return void
48 */
48 */
49
49
50 asm("flush");
50 asm("flush");
51 }
51 }
52
52
53 //***************************
53 //***************************
54 // CCR Cache control register
54 // CCR Cache control register
55
55
56 static unsigned int CCR_getValue()
56 static unsigned int CCR_getValue()
57 {
57 {
58 unsigned int cacheControlRegister = 0;
58 unsigned int cacheControlRegister = 0;
59 __asm__ __volatile__("lda [%%g0] 2, %0" : "=r"(cacheControlRegister) : );
59 __asm__ __volatile__("lda [%%g0] 2, %0" : "=r"(cacheControlRegister) : );
60 return cacheControlRegister;
60 return cacheControlRegister;
61 }
61 }
62
62
63 static void CCR_setValue(unsigned int cacheControlRegister)
63 static void CCR_setValue(unsigned int cacheControlRegister)
64 {
64 {
65 __asm__ __volatile__("sta %0, [%%g0] 2" : : "r"(cacheControlRegister));
65 __asm__ __volatile__("sta %0, [%%g0] 2" : : "r"(cacheControlRegister));
66 }
66 }
67
67
68 static void CCR_resetCacheControlRegister()
68 static void CCR_resetCacheControlRegister()
69 {
69 {
70 unsigned int cacheControlRegister;
70 unsigned int cacheControlRegister;
71 cacheControlRegister = 0x00;
71 cacheControlRegister = 0x00;
72 CCR_setValue(cacheControlRegister);
72 CCR_setValue(cacheControlRegister);
73 }
73 }
74
74
75 static void CCR_enableInstructionCache()
75 static void CCR_enableInstructionCache()
76 {
76 {
77 // [1:0] Instruction Cache state (ICS)
77 // [1:0] Instruction Cache state (ICS)
78 // Indicates the current data cache state according to the following: X0 = disabled, 01 = frozen, 11 = enabled.
78 // Indicates the current data cache state according to the following: X0 = disabled, 01 = frozen, 11 = enabled.
79 unsigned int cacheControlRegister;
79 unsigned int cacheControlRegister;
80 cacheControlRegister = CCR_getValue();
80 cacheControlRegister = CCR_getValue();
81 cacheControlRegister = (cacheControlRegister | 0x3);
81 cacheControlRegister = (cacheControlRegister | 0x3);
82 CCR_setValue(cacheControlRegister);
82 CCR_setValue(cacheControlRegister);
83 }
83 }
84
84
85 static void CCR_enableDataCache()
85 static void CCR_enableDataCache()
86 {
86 {
87 // [3:2] Data Cache state (DCS)
87 // [3:2] Data Cache state (DCS)
88 // Indicates the current data cache state according to the following: X0 = disabled, 01 = frozen, 11 = enabled.
88 // Indicates the current data cache state according to the following: X0 = disabled, 01 = frozen, 11 = enabled.
89 unsigned int cacheControlRegister;
89 unsigned int cacheControlRegister;
90 cacheControlRegister = CCR_getValue();
90 cacheControlRegister = CCR_getValue();
91 cacheControlRegister = (cacheControlRegister | 0xc);
91 cacheControlRegister = (cacheControlRegister | 0xc);
92 CCR_setValue(cacheControlRegister);
92 CCR_setValue(cacheControlRegister);
93 }
93 }
94
94
95 static void CCR_faultTolerantScheme()
95 static void CCR_faultTolerantScheme()
96 {
96 {
97 // [20:19] FT scheme (FT) - “00” = no FT, “01” = 4-bit checking implemented
97 // [20:19] FT scheme (FT) - “00” = no FT, “01” = 4-bit checking implemented
98 unsigned int cacheControlRegister;
98 unsigned int cacheControlRegister;
99 unsigned int *plugAndPlayRegister;
99 unsigned int *plugAndPlayRegister;
100 unsigned int vendorId;
100 unsigned int vendorId;
101 unsigned int deviceId;
101 unsigned int deviceId;
102
102
103 plugAndPlayRegister = (unsigned int*) REGS_ADDR_PLUGANDPLAY;
103 plugAndPlayRegister = (unsigned int*) REGS_ADDR_PLUGANDPLAY;
104 vendorId = ( (*plugAndPlayRegister) & 0xff000000 ) >> 24;
104 vendorId = ( (*plugAndPlayRegister) & 0xff000000 ) >> 24;
105 deviceId = ( (*plugAndPlayRegister) & 0x00fff000 ) >> 12;
105 deviceId = ( (*plugAndPlayRegister) & 0x00fff000 ) >> 12;
106
106
107 if( (vendorId == VENDORID_GAISLER) & (deviceId ==DEVICEID_LEON3FT) )
107 if( (vendorId == VENDORID_GAISLER) & (deviceId ==DEVICEID_LEON3FT) )
108 {
108 {
109 PRINTF("in faultTolerantScheme *** Leon3FT detected, configure the CCR FT bits");
109 PRINTF("in faultTolerantScheme *** Leon3FT detected, configure the CCR FT bits\n");
110 cacheControlRegister = CCR_getValue();
110 cacheControlRegister = CCR_getValue();
111 cacheControlRegister = (cacheControlRegister | 0xc);
111 cacheControlRegister = (cacheControlRegister | 0xc);
112 CCR_setValue(cacheControlRegister);
112 CCR_setValue(cacheControlRegister);
113 }
113 }
114 else
114 else
115 {
115 {
116 PRINTF("in faultTolerantScheme *** not a Leon3FT, no need to configure the CCR FT bits\n");
116 PRINTF("in faultTolerantScheme *** not a Leon3FT, no need to configure the CCR FT bits\n");
117 PRINTF2(" *** vendorID = 0x%x, deviceId = 0x%x\n", vendorId, deviceId);
117 PRINTF2(" *** vendorID = 0x%x, deviceId = 0x%x\n", vendorId, deviceId);
118 }
118 }
119 }
119 }
120
120
121 static void CCR_enableInstructionBurstFetch()
121 static void CCR_enableInstructionBurstFetch()
122 {
122 {
123 // [16] Instruction burst fetch (IB). This bit enables burst fill during instruction fetch.
123 // [16] Instruction burst fetch (IB). This bit enables burst fill during instruction fetch.
124 unsigned int cacheControlRegister;
124 unsigned int cacheControlRegister;
125 cacheControlRegister = CCR_getValue();
125 cacheControlRegister = CCR_getValue();
126 // set the bit IB to 1
126 // set the bit IB to 1
127 cacheControlRegister = (cacheControlRegister | 0x10000);
127 cacheControlRegister = (cacheControlRegister | 0x10000);
128 CCR_setValue(cacheControlRegister);
128 CCR_setValue(cacheControlRegister);
129 }
129 }
130
130
131 static void CCR_getInstructionAndDataErrorCounters( unsigned int* instructionErrorCounter, unsigned int* dataErrorCounter )
131 static void CCR_getInstructionAndDataErrorCounters( unsigned int* instructionErrorCounter, unsigned int* dataErrorCounter )
132 {
132 {
133 // [13:12] Instruction Tag Errors (ITE) - Number of detected parity errors in the instruction tag cache.
133 // [13:12] Instruction Tag Errors (ITE) - Number of detected parity errors in the instruction tag cache.
134 // Only available if fault-tolerance is enabled (FT field in this register is non-zero).
134 // Only available if fault-tolerance is enabled (FT field in this register is non-zero).
135 // [11:10] Instruction Data Errors (IDE) - Number of detected parity errors in the instruction data cache.
135 // [11:10] Instruction Data Errors (IDE) - Number of detected parity errors in the instruction data cache.
136 // Only available if fault-tolerance is enabled (FT field in this register is non-zero).
136 // Only available if fault-tolerance is enabled (FT field in this register is non-zero).
137
137
138 unsigned int cacheControlRegister;
138 unsigned int cacheControlRegister;
139 unsigned int iTE;
139 unsigned int iTE;
140 unsigned int iDE;
140 unsigned int iDE;
141 unsigned int dTE;
141 unsigned int dTE;
142 unsigned int dDE;
142 unsigned int dDE;
143
143
144 cacheControlRegister = CCR_getValue();
144 cacheControlRegister = CCR_getValue();
145 iTE = (cacheControlRegister & COUNTER_FIELD_ITE) >> POS_ITE;
145 iTE = (cacheControlRegister & COUNTER_FIELD_ITE) >> POS_ITE;
146 iDE = (cacheControlRegister & COUNTER_FIELD_IDE) >> POS_IDE;
146 iDE = (cacheControlRegister & COUNTER_FIELD_IDE) >> POS_IDE;
147 dTE = (cacheControlRegister & COUNTER_FIELD_DTE) >> POS_DTE;
147 dTE = (cacheControlRegister & COUNTER_FIELD_DTE) >> POS_DTE;
148 dDE = (cacheControlRegister & COUNTER_FIELD_DDE) >> POS_DDE;
148 dDE = (cacheControlRegister & COUNTER_FIELD_DDE) >> POS_DDE;
149
149
150 *instructionErrorCounter = iTE + iDE;
150 *instructionErrorCounter = iTE + iDE;
151 *dataErrorCounter = dTE + dDE;
151 *dataErrorCounter = dTE + dDE;
152
152
153 // reset counters
153 // reset counters
154 cacheControlRegister = cacheControlRegister
154 cacheControlRegister = cacheControlRegister
155 & COUNTER_FIELD_ITE
155 & COUNTER_FIELD_ITE
156 & COUNTER_FIELD_IDE
156 & COUNTER_FIELD_IDE
157 & COUNTER_FIELD_DTE
157 & COUNTER_FIELD_DTE
158 & COUNTER_FIELD_DDE;
158 & COUNTER_FIELD_DDE;
159
159
160 CCR_setValue(cacheControlRegister);
160 CCR_setValue(cacheControlRegister);
161 }
161 }
162
162
163 //*******************************************
163 //*******************************************
164 // ASR16 Register protection control register
164 // ASR16 Register protection control register
165
165
166 static unsigned int ASR16_get_FPRF_IURF_ErrorCounters( unsigned int* fprfErrorCounter, unsigned int* iurfErrorCounter)
166 static void ASR16_get_FPRF_IURF_ErrorCounters( unsigned int* fprfErrorCounter, unsigned int* iurfErrorCounter)
167 {
167 {
168 /** This function is used to retrieve the integer unit register file error counter and the floating point unit
168 /** This function is used to retrieve the integer unit register file error counter and the floating point unit
169 * register file error counter
169 * register file error counter
170 *
170 *
171 * @return void
171 * @return void
172 *
172 *
173 * [29:27] FP RF error counter - Number of detected parity errors in the FP register file.
173 * [29:27] FP RF error counter - Number of detected parity errors in the FP register file.
174 * [13:11] IU RF error counter - Number of detected parity errors in the IU register file.
174 * [13:11] IU RF error counter - Number of detected parity errors in the IU register file.
175 *
175 *
176 */
176 */
177
177
178 unsigned int asr16;
178 unsigned int asr16;
179
179
180 asr16 = *asr16Ptr;
180 asr16 = *asr16Ptr;
181 *fprfErrorCounter = ( asr16 & COUNTER_FIELD_FPRF ) >> POS_FPRF;
181 *fprfErrorCounter = ( asr16 & COUNTER_FIELD_FPRF ) >> POS_FPRF;
182 *iurfErrorCounter = ( asr16 & COUNTER_FIELD_IURF ) >> POS_IURF;
182 *iurfErrorCounter = ( asr16 & COUNTER_FIELD_IURF ) >> POS_IURF;
183
183
184 // reset the counter to 0
184 // reset the counter to 0
185 asr16 = asr16Ptr
185 asr16 = asr16
186 & COUNTER_MASK_FPRF
186 & COUNTER_MASK_FPRF
187 & COUNTER_FIELD_IURF;
187 & COUNTER_FIELD_IURF;
188
188
189 *asr16Ptr = asr16;
189 *asr16Ptr = asr16;
190 }
190 }
191
191
192 #endif /* GSCMEMORY_HPP_ */
192 #endif /* GSCMEMORY_HPP_ */
@@ -1,56 +1,56
1 #ifndef FSW_SPACEWIRE_H_INCLUDED
1 #ifndef FSW_SPACEWIRE_H_INCLUDED
2 #define FSW_SPACEWIRE_H_INCLUDED
2 #define FSW_SPACEWIRE_H_INCLUDED
3
3
4 #include <rtems.h>
4 #include <rtems.h>
5 #include <grspw.h>
5 #include <grspw.h>
6
6
7 #include <fcntl.h> // for O_RDWR
7 #include <fcntl.h> // for O_RDWR
8 #include <unistd.h> // for the read call
8 #include <unistd.h> // for the read call
9 #include <sys/ioctl.h> // for the ioctl call
9 #include <sys/ioctl.h> // for the ioctl call
10 #include <errno.h>
10 #include <errno.h>
11
11
12 #include "fsw_params.h"
12 #include "fsw_params.h"
13 #include "tc_handler.h"
13 #include "tc_handler.h"
14 #include "fsw_init.h"
14 #include "fsw_init.h"
15
15
16 extern spw_stats spacewire_stats;
16 extern spw_stats spacewire_stats;
17 extern spw_stats spacewire_stats_backup;
17 extern spw_stats spacewire_stats_backup;
18 extern rtems_name timecode_timer_name;
18 extern rtems_name timecode_timer_name;
19 extern rtems_id timecode_timer_id;
19 extern rtems_id timecode_timer_id;
20
20
21 // RTEMS TASK
21 // RTEMS TASK
22 rtems_task spiq_task( rtems_task_argument argument );
22 rtems_task spiq_task( rtems_task_argument argument );
23 rtems_task recv_task( rtems_task_argument unused );
23 rtems_task recv_task( rtems_task_argument unused );
24 rtems_task send_task( rtems_task_argument argument );
24 rtems_task send_task( rtems_task_argument argument );
25 rtems_task wtdg_task( rtems_task_argument argument );
25 rtems_task wtdg_task( rtems_task_argument argument );
26
26
27 int spacewire_open_link( void );
27 int spacewire_open_link( void );
28 int spacewire_start_link( int fd );
28 int spacewire_start_link( int fd );
29 int spacewire_stop_and_start_link( int fd );
29 int spacewire_stop_and_start_link( int fd );
30 int spacewire_configure_link(int fd );
30 int spacewire_configure_link(int fd );
31 int spacewire_reset_link( void );
31 int spacewire_several_connect_attemps( void );
32 void spacewire_set_NP( unsigned char val, unsigned int regAddr ); // No Port force
32 void spacewire_set_NP( unsigned char val, unsigned int regAddr ); // No Port force
33 void spacewire_set_RE( unsigned char val, unsigned int regAddr ); // RMAP Enable
33 void spacewire_set_RE( unsigned char val, unsigned int regAddr ); // RMAP Enable
34 void spacewire_compute_stats_offsets( void );
34 void spacewire_compute_stats_offsets( void );
35 void spacewire_update_statistics( void );
35 void spacewire_update_statistics( void );
36 void increase_unsigned_char_counter( unsigned char *counter );
36 void increase_unsigned_char_counter( unsigned char *counter );
37
37
38 void init_header_cwf( Header_TM_LFR_SCIENCE_CWF_t *header );
38 void init_header_cwf( Header_TM_LFR_SCIENCE_CWF_t *header );
39 void init_header_swf( Header_TM_LFR_SCIENCE_SWF_t *header );
39 void init_header_swf( Header_TM_LFR_SCIENCE_SWF_t *header );
40 void init_header_asm( Header_TM_LFR_SCIENCE_ASM_t *header );
40 void init_header_asm( Header_TM_LFR_SCIENCE_ASM_t *header );
41 int spw_send_waveform_CWF( ring_node *ring_node_to_send, Header_TM_LFR_SCIENCE_CWF_t *header );
41 int spw_send_waveform_CWF( ring_node *ring_node_to_send, Header_TM_LFR_SCIENCE_CWF_t *header );
42 int spw_send_waveform_SWF( ring_node *ring_node_to_send, Header_TM_LFR_SCIENCE_SWF_t *header );
42 int spw_send_waveform_SWF( ring_node *ring_node_to_send, Header_TM_LFR_SCIENCE_SWF_t *header );
43 int spw_send_waveform_CWF3_light( ring_node *ring_node_to_send, Header_TM_LFR_SCIENCE_CWF_t *header );
43 int spw_send_waveform_CWF3_light( ring_node *ring_node_to_send, Header_TM_LFR_SCIENCE_CWF_t *header );
44 void spw_send_asm_f0( ring_node *ring_node_to_send, Header_TM_LFR_SCIENCE_ASM_t *header );
44 void spw_send_asm_f0( ring_node *ring_node_to_send, Header_TM_LFR_SCIENCE_ASM_t *header );
45 void spw_send_asm_f1( ring_node *ring_node_to_send, Header_TM_LFR_SCIENCE_ASM_t *header );
45 void spw_send_asm_f1( ring_node *ring_node_to_send, Header_TM_LFR_SCIENCE_ASM_t *header );
46 void spw_send_asm_f2( ring_node *ring_node_to_send, Header_TM_LFR_SCIENCE_ASM_t *header );
46 void spw_send_asm_f2( ring_node *ring_node_to_send, Header_TM_LFR_SCIENCE_ASM_t *header );
47 void spw_send_k_dump( ring_node *ring_node_to_send );
47 void spw_send_k_dump( ring_node *ring_node_to_send );
48
48
49 rtems_timer_service_routine timecode_timer_routine( rtems_id timer_id, void *user_data );
49 rtems_timer_service_routine timecode_timer_routine( rtems_id timer_id, void *user_data );
50 unsigned int check_timecode_and_previous_timecode_coherency(unsigned char currentTimecodeCtr);
50 unsigned int check_timecode_and_previous_timecode_coherency(unsigned char currentTimecodeCtr);
51 unsigned int check_timecode_and_internal_time_coherency(unsigned char timecode, unsigned char internalTime);
51 unsigned int check_timecode_and_internal_time_coherency(unsigned char timecode, unsigned char internalTime);
52 void timecode_irq_handler( void *pDev, void *regs, int minor, unsigned int tc );
52 void timecode_irq_handler( void *pDev, void *regs, int minor, unsigned int tc );
53
53
54 void (*grspw_timecode_callback) ( void *pDev, void *regs, int minor, unsigned int tc );
54 void (*grspw_timecode_callback) ( void *pDev, void *regs, int minor, unsigned int tc );
55
55
56 #endif // FSW_SPACEWIRE_H_INCLUDED
56 #endif // FSW_SPACEWIRE_H_INCLUDED
@@ -1,14 +1,14
1 # LOAD FSW USING LINK 1
1 # LOAD FSW USING LINK 1
2 SpwPlugin0.StarDundeeSelectLinkNumber( 1 )
2 SpwPlugin0.StarDundeeSelectLinkNumber( 1 )
3
3
4 dsu3plugin0.openFile("/opt/DEV_PLE/FSW-qt/bin/fsw")
4 dsu3plugin0.openFile("/opt/DEV_PLE/FSW-qt/bin/fsw")
5 #dsu3plugin0.openFile("/opt/LFR/LFR-FSW/2.0.2.3/fsw")
5 #dsu3plugin0.openFile("/opt/LFR/LFR-FSW/2.0.2.3/fsw")
6 dsu3plugin0.loadFile()
6 dsu3plugin0.loadFile()
7
7
8 dsu3plugin0.run()
8 dsu3plugin0.run()
9
9
10 # START SENDING TIMECODES AT 1 Hz
10 # START SENDING TIMECODES AT 1 Hz
11 SpwPlugin0.StarDundeeStartTimecodes( 1 )
11 #SpwPlugin0.StarDundeeStartTimecodes( 1 )
12
12
13 # it is possible to change the time code frequency
13 # it is possible to change the time code frequency
14 #RMAPPlugin0.changeTimecodeFrequency(2)
14 #RMAPPlugin0.changeTimecodeFrequency(2)
@@ -1,910 +1,909
1 /** This is the RTEMS initialization module.
1 /** This is the RTEMS initialization module.
2 *
2 *
3 * @file
3 * @file
4 * @author P. LEROY
4 * @author P. LEROY
5 *
5 *
6 * This module contains two very different information:
6 * This module contains two very different information:
7 * - specific instructions to configure the compilation of the RTEMS executive
7 * - specific instructions to configure the compilation of the RTEMS executive
8 * - functions related to the fligth softwre initialization, especially the INIT RTEMS task
8 * - functions related to the fligth softwre initialization, especially the INIT RTEMS task
9 *
9 *
10 */
10 */
11
11
12 //*************************
12 //*************************
13 // GPL reminder to be added
13 // GPL reminder to be added
14 //*************************
14 //*************************
15
15
16 #include <rtems.h>
16 #include <rtems.h>
17
17
18 /* configuration information */
18 /* configuration information */
19
19
20 #define CONFIGURE_INIT
20 #define CONFIGURE_INIT
21
21
22 #include <bsp.h> /* for device driver prototypes */
22 #include <bsp.h> /* for device driver prototypes */
23
23
24 /* configuration information */
24 /* configuration information */
25
25
26 #define CONFIGURE_APPLICATION_NEEDS_CONSOLE_DRIVER
26 #define CONFIGURE_APPLICATION_NEEDS_CONSOLE_DRIVER
27 #define CONFIGURE_APPLICATION_NEEDS_CLOCK_DRIVER
27 #define CONFIGURE_APPLICATION_NEEDS_CLOCK_DRIVER
28
28
29 #define CONFIGURE_MAXIMUM_TASKS 20
29 #define CONFIGURE_MAXIMUM_TASKS 20
30 #define CONFIGURE_RTEMS_INIT_TASKS_TABLE
30 #define CONFIGURE_RTEMS_INIT_TASKS_TABLE
31 #define CONFIGURE_EXTRA_TASK_STACKS (3 * RTEMS_MINIMUM_STACK_SIZE)
31 #define CONFIGURE_EXTRA_TASK_STACKS (3 * RTEMS_MINIMUM_STACK_SIZE)
32 #define CONFIGURE_LIBIO_MAXIMUM_FILE_DESCRIPTORS 32
32 #define CONFIGURE_LIBIO_MAXIMUM_FILE_DESCRIPTORS 32
33 #define CONFIGURE_INIT_TASK_PRIORITY 1 // instead of 100
33 #define CONFIGURE_INIT_TASK_PRIORITY 1 // instead of 100
34 #define CONFIGURE_INIT_TASK_MODE (RTEMS_DEFAULT_MODES | RTEMS_NO_PREEMPT)
34 #define CONFIGURE_INIT_TASK_MODE (RTEMS_DEFAULT_MODES | RTEMS_NO_PREEMPT)
35 #define CONFIGURE_INIT_TASK_ATTRIBUTES (RTEMS_DEFAULT_ATTRIBUTES | RTEMS_FLOATING_POINT)
35 #define CONFIGURE_INIT_TASK_ATTRIBUTES (RTEMS_DEFAULT_ATTRIBUTES | RTEMS_FLOATING_POINT)
36 #define CONFIGURE_MAXIMUM_DRIVERS 16
36 #define CONFIGURE_MAXIMUM_DRIVERS 16
37 #define CONFIGURE_MAXIMUM_PERIODS 5
37 #define CONFIGURE_MAXIMUM_PERIODS 5
38 #define CONFIGURE_MAXIMUM_TIMERS 5 // [spiq] [wtdg] [spacewire_reset_link]
38 #define CONFIGURE_MAXIMUM_TIMERS 5 // [spiq] [wtdg] [spacewire_reset_link]
39 #define CONFIGURE_MAXIMUM_MESSAGE_QUEUES 5
39 #define CONFIGURE_MAXIMUM_MESSAGE_QUEUES 5
40 #ifdef PRINT_STACK_REPORT
40 #ifdef PRINT_STACK_REPORT
41 #define CONFIGURE_STACK_CHECKER_ENABLED
41 #define CONFIGURE_STACK_CHECKER_ENABLED
42 #endif
42 #endif
43
43
44 #include <rtems/confdefs.h>
44 #include <rtems/confdefs.h>
45
45
46 /* If --drvmgr was enabled during the configuration of the RTEMS kernel */
46 /* If --drvmgr was enabled during the configuration of the RTEMS kernel */
47 #ifdef RTEMS_DRVMGR_STARTUP
47 #ifdef RTEMS_DRVMGR_STARTUP
48 #ifdef LEON3
48 #ifdef LEON3
49 /* Add Timer and UART Driver */
49 /* Add Timer and UART Driver */
50 #ifdef CONFIGURE_APPLICATION_NEEDS_CLOCK_DRIVER
50 #ifdef CONFIGURE_APPLICATION_NEEDS_CLOCK_DRIVER
51 #define CONFIGURE_DRIVER_AMBAPP_GAISLER_GPTIMER
51 #define CONFIGURE_DRIVER_AMBAPP_GAISLER_GPTIMER
52 #endif
52 #endif
53 #ifdef CONFIGURE_APPLICATION_NEEDS_CONSOLE_DRIVER
53 #ifdef CONFIGURE_APPLICATION_NEEDS_CONSOLE_DRIVER
54 #define CONFIGURE_DRIVER_AMBAPP_GAISLER_APBUART
54 #define CONFIGURE_DRIVER_AMBAPP_GAISLER_APBUART
55 #endif
55 #endif
56 #endif
56 #endif
57 #define CONFIGURE_DRIVER_AMBAPP_GAISLER_GRSPW /* GRSPW Driver */
57 #define CONFIGURE_DRIVER_AMBAPP_GAISLER_GRSPW /* GRSPW Driver */
58 #include <drvmgr/drvmgr_confdefs.h>
58 #include <drvmgr/drvmgr_confdefs.h>
59 #endif
59 #endif
60
60
61 #include "fsw_init.h"
61 #include "fsw_init.h"
62 #include "fsw_config.c"
62 #include "fsw_config.c"
63 #include "GscMemoryLPP.hpp"
63 #include "GscMemoryLPP.hpp"
64
64
65 void initCache()
65 void initCache()
66 {
66 {
67 // ASI 2 contains a few control registers that have not been assigned as ancillary state registers.
67 // ASI 2 contains a few control registers that have not been assigned as ancillary state registers.
68 // These should only be read and written using 32-bit LDA/STA instructions.
68 // These should only be read and written using 32-bit LDA/STA instructions.
69 // All cache registers are accessed through load/store operations to the alternate address space (LDA/STA), using ASI = 2.
69 // All cache registers are accessed through load/store operations to the alternate address space (LDA/STA), using ASI = 2.
70 // The table below shows the register addresses:
70 // The table below shows the register addresses:
71 // 0x00 Cache control register
71 // 0x00 Cache control register
72 // 0x04 Reserved
72 // 0x04 Reserved
73 // 0x08 Instruction cache configuration register
73 // 0x08 Instruction cache configuration register
74 // 0x0C Data cache configuration register
74 // 0x0C Data cache configuration register
75
75
76 // Cache Control Register Leon3 / Leon3FT
76 // Cache Control Register Leon3 / Leon3FT
77 // 31..30 29 28 27..24 23 22 21 20..19 18 17 16
77 // 31..30 29 28 27..24 23 22 21 20..19 18 17 16
78 // RFT PS TB DS FD FI FT ST IB
78 // RFT PS TB DS FD FI FT ST IB
79 // 15 14 13..12 11..10 9..8 7..6 5 4 3..2 1..0
79 // 15 14 13..12 11..10 9..8 7..6 5 4 3..2 1..0
80 // IP DP ITE IDE DTE DDE DF IF DCS ICS
80 // IP DP ITE IDE DTE DDE DF IF DCS ICS
81
81
82 unsigned int cacheControlRegister;
82 unsigned int cacheControlRegister;
83
83
84 cacheControlRegister = CCR_getValue();
84 cacheControlRegister = CCR_getValue();
85 PRINTF1("(0) cacheControlRegister = %x\n", cacheControlRegister);
85 PRINTF1("(0) cacheControlRegister = %x\n", cacheControlRegister);
86
86
87 CCR_resetCacheControlRegister();
87 CCR_resetCacheControlRegister();
88
88
89 CCR_enableInstructionCache(); // ICS bits
89 CCR_enableInstructionCache(); // ICS bits
90 CCR_enableDataCache(); // DCS bits
90 CCR_enableDataCache(); // DCS bits
91 CCR_enableInstructionBurstFetch(); // IB bit
91 CCR_enableInstructionBurstFetch(); // IB bit
92
92
93 cacheControlRegister = CCR_getValue();
93 cacheControlRegister = CCR_getValue();
94 PRINTF1("(1) cacheControlRegister = %x\n", cacheControlRegister);
94 PRINTF1("(1) cacheControlRegister = %x\n", cacheControlRegister);
95
95
96 CCR_faultTolerantScheme();
96 CCR_faultTolerantScheme();
97
97
98 // FT activation
98 PRINTF("\n");
99 }
99 }
100
100
101 rtems_task Init( rtems_task_argument ignored )
101 rtems_task Init( rtems_task_argument ignored )
102 {
102 {
103 /** This is the RTEMS INIT taks, it is the first task launched by the system.
103 /** This is the RTEMS INIT taks, it is the first task launched by the system.
104 *
104 *
105 * @param unused is the starting argument of the RTEMS task
105 * @param unused is the starting argument of the RTEMS task
106 *
106 *
107 * The INIT task create and run all other RTEMS tasks.
107 * The INIT task create and run all other RTEMS tasks.
108 *
108 *
109 */
109 */
110
110
111 //***********
111 //***********
112 // INIT CACHE
112 // INIT CACHE
113
113
114 unsigned char *vhdlVersion;
114 unsigned char *vhdlVersion;
115
115
116 reset_lfr();
116 reset_lfr();
117
117
118 reset_local_time();
118 reset_local_time();
119
119
120 rtems_cpu_usage_reset();
120 rtems_cpu_usage_reset();
121
121
122 rtems_status_code status;
122 rtems_status_code status;
123 rtems_status_code status_spw;
123 rtems_status_code status_spw;
124 rtems_isr_entry old_isr_handler;
124 rtems_isr_entry old_isr_handler;
125
125
126 // UART settings
126 // UART settings
127 send_console_outputs_on_apbuart_port();
127 enable_apbuart_transmitter();
128 set_apbuart_scaler_reload_register(REGS_ADDR_APBUART, APBUART_SCALER_RELOAD_VALUE);
128 set_apbuart_scaler_reload_register(REGS_ADDR_APBUART, APBUART_SCALER_RELOAD_VALUE);
129 enable_apbuart_transmitter();
130
129
131 DEBUG_PRINTF("\n\n\n\n\nIn INIT *** Now the console is on port COM1\n")
130 DEBUG_PRINTF("\n\n\n\n\nIn INIT *** Now the console is on port COM1\n")
132
131
133
132
134 PRINTF("\n\n\n\n\n")
133 PRINTF("\n\n\n\n\n")
135
134
136 initCache();
135 initCache();
137
136
138 PRINTF("*************************\n")
137 PRINTF("*************************\n")
139 PRINTF("** LFR Flight Software **\n")
138 PRINTF("** LFR Flight Software **\n")
140 PRINTF1("** %d.", SW_VERSION_N1)
139 PRINTF1("** %d.", SW_VERSION_N1)
141 PRINTF1("%d." , SW_VERSION_N2)
140 PRINTF1("%d." , SW_VERSION_N2)
142 PRINTF1("%d." , SW_VERSION_N3)
141 PRINTF1("%d." , SW_VERSION_N3)
143 PRINTF1("%d **\n", SW_VERSION_N4)
142 PRINTF1("%d **\n", SW_VERSION_N4)
144
143
145 vhdlVersion = (unsigned char *) (REGS_ADDR_VHDL_VERSION);
144 vhdlVersion = (unsigned char *) (REGS_ADDR_VHDL_VERSION);
146 PRINTF("** VHDL **\n")
145 PRINTF("** VHDL **\n")
147 PRINTF1("** %d.", vhdlVersion[1])
146 PRINTF1("** %d.", vhdlVersion[1])
148 PRINTF1("%d." , vhdlVersion[2])
147 PRINTF1("%d." , vhdlVersion[2])
149 PRINTF1("%d **\n", vhdlVersion[3])
148 PRINTF1("%d **\n", vhdlVersion[3])
150 PRINTF("*************************\n")
149 PRINTF("*************************\n")
151 PRINTF("\n\n")
150 PRINTF("\n\n")
152
151
153 init_parameter_dump();
152 init_parameter_dump();
154 init_kcoefficients_dump();
153 init_kcoefficients_dump();
155 init_local_mode_parameters();
154 init_local_mode_parameters();
156 init_housekeeping_parameters();
155 init_housekeeping_parameters();
157 init_k_coefficients_prc0();
156 init_k_coefficients_prc0();
158 init_k_coefficients_prc1();
157 init_k_coefficients_prc1();
159 init_k_coefficients_prc2();
158 init_k_coefficients_prc2();
160 pa_bia_status_info = 0x00;
159 pa_bia_status_info = 0x00;
161 update_last_valid_transition_date( DEFAULT_LAST_VALID_TRANSITION_DATE );
160 update_last_valid_transition_date( DEFAULT_LAST_VALID_TRANSITION_DATE );
162
161
163 // waveform picker initialization
162 // waveform picker initialization
164 WFP_init_rings(); LEON_Clear_interrupt( IRQ_SPARC_GPTIMER_WATCHDOG ); // initialize the waveform rings
163 WFP_init_rings(); LEON_Clear_interrupt( IRQ_SPARC_GPTIMER_WATCHDOG ); // initialize the waveform rings
165 WFP_reset_current_ring_nodes();
164 WFP_reset_current_ring_nodes();
166 reset_waveform_picker_regs();
165 reset_waveform_picker_regs();
167
166
168 // spectral matrices initialization
167 // spectral matrices initialization
169 SM_init_rings(); // initialize spectral matrices rings
168 SM_init_rings(); // initialize spectral matrices rings
170 SM_reset_current_ring_nodes();
169 SM_reset_current_ring_nodes();
171 reset_spectral_matrix_regs();
170 reset_spectral_matrix_regs();
172
171
173 // configure calibration
172 // configure calibration
174 configureCalibration( false ); // true means interleaved mode, false is for normal mode
173 configureCalibration( false ); // true means interleaved mode, false is for normal mode
175
174
176 updateLFRCurrentMode();
175 updateLFRCurrentMode();
177
176
178 BOOT_PRINTF1("in INIT *** lfrCurrentMode is %d\n", lfrCurrentMode)
177 BOOT_PRINTF1("in INIT *** lfrCurrentMode is %d\n", lfrCurrentMode)
179
178
180 create_names(); // create all names
179 create_names(); // create all names
181
180
182 status = create_timecode_timer(); // create the timer used by timecode_irq_handler
181 status = create_timecode_timer(); // create the timer used by timecode_irq_handler
183 if (status != RTEMS_SUCCESSFUL)
182 if (status != RTEMS_SUCCESSFUL)
184 {
183 {
185 PRINTF1("in INIT *** ERR in create_timer_timecode, code %d", status)
184 PRINTF1("in INIT *** ERR in create_timer_timecode, code %d", status)
186 }
185 }
187
186
188 status = create_message_queues(); // create message queues
187 status = create_message_queues(); // create message queues
189 if (status != RTEMS_SUCCESSFUL)
188 if (status != RTEMS_SUCCESSFUL)
190 {
189 {
191 PRINTF1("in INIT *** ERR in create_message_queues, code %d", status)
190 PRINTF1("in INIT *** ERR in create_message_queues, code %d", status)
192 }
191 }
193
192
194 status = create_all_tasks(); // create all tasks
193 status = create_all_tasks(); // create all tasks
195 if (status != RTEMS_SUCCESSFUL)
194 if (status != RTEMS_SUCCESSFUL)
196 {
195 {
197 PRINTF1("in INIT *** ERR in create_all_tasks, code %d\n", status)
196 PRINTF1("in INIT *** ERR in create_all_tasks, code %d\n", status)
198 }
197 }
199
198
200 // **************************
199 // **************************
201 // <SPACEWIRE INITIALIZATION>
200 // <SPACEWIRE INITIALIZATION>
202 grspw_timecode_callback = &timecode_irq_handler;
201 grspw_timecode_callback = &timecode_irq_handler;
203
202
204 status_spw = spacewire_open_link(); // (1) open the link
203 status_spw = spacewire_open_link(); // (1) open the link
205 if ( status_spw != RTEMS_SUCCESSFUL )
204 if ( status_spw != RTEMS_SUCCESSFUL )
206 {
205 {
207 PRINTF1("in INIT *** ERR spacewire_open_link code %d\n", status_spw )
206 PRINTF1("in INIT *** ERR spacewire_open_link code %d\n", status_spw )
208 }
207 }
209
208
210 if ( status_spw == RTEMS_SUCCESSFUL ) // (2) configure the link
209 if ( status_spw == RTEMS_SUCCESSFUL ) // (2) configure the link
211 {
210 {
212 status_spw = spacewire_configure_link( fdSPW );
211 status_spw = spacewire_configure_link( fdSPW );
213 if ( status_spw != RTEMS_SUCCESSFUL )
212 if ( status_spw != RTEMS_SUCCESSFUL )
214 {
213 {
215 PRINTF1("in INIT *** ERR spacewire_configure_link code %d\n", status_spw )
214 PRINTF1("in INIT *** ERR spacewire_configure_link code %d\n", status_spw )
216 }
215 }
217 }
216 }
218
217
219 if ( status_spw == RTEMS_SUCCESSFUL) // (3) start the link
218 if ( status_spw == RTEMS_SUCCESSFUL) // (3) start the link
220 {
219 {
221 status_spw = spacewire_start_link( fdSPW );
220 status_spw = spacewire_start_link( fdSPW );
222 if ( status_spw != RTEMS_SUCCESSFUL )
221 if ( status_spw != RTEMS_SUCCESSFUL )
223 {
222 {
224 PRINTF1("in INIT *** ERR spacewire_start_link code %d\n", status_spw )
223 PRINTF1("in INIT *** ERR spacewire_start_link code %d\n", status_spw )
225 }
224 }
226 }
225 }
227 // </SPACEWIRE INITIALIZATION>
226 // </SPACEWIRE INITIALIZATION>
228 // ***************************
227 // ***************************
229
228
230 status = start_all_tasks(); // start all tasks
229 status = start_all_tasks(); // start all tasks
231 if (status != RTEMS_SUCCESSFUL)
230 if (status != RTEMS_SUCCESSFUL)
232 {
231 {
233 PRINTF1("in INIT *** ERR in start_all_tasks, code %d", status)
232 PRINTF1("in INIT *** ERR in start_all_tasks, code %d", status)
234 }
233 }
235
234
236 // start RECV and SEND *AFTER* SpaceWire Initialization, due to the timeout of the start call during the initialization
235 // start RECV and SEND *AFTER* SpaceWire Initialization, due to the timeout of the start call during the initialization
237 status = start_recv_send_tasks();
236 status = start_recv_send_tasks();
238 if ( status != RTEMS_SUCCESSFUL )
237 if ( status != RTEMS_SUCCESSFUL )
239 {
238 {
240 PRINTF1("in INIT *** ERR start_recv_send_tasks code %d\n", status )
239 PRINTF1("in INIT *** ERR start_recv_send_tasks code %d\n", status )
241 }
240 }
242
241
243 // suspend science tasks, they will be restarted later depending on the mode
242 // suspend science tasks, they will be restarted later depending on the mode
244 status = suspend_science_tasks(); // suspend science tasks (not done in stop_current_mode if current mode = STANDBY)
243 status = suspend_science_tasks(); // suspend science tasks (not done in stop_current_mode if current mode = STANDBY)
245 if (status != RTEMS_SUCCESSFUL)
244 if (status != RTEMS_SUCCESSFUL)
246 {
245 {
247 PRINTF1("in INIT *** in suspend_science_tasks *** ERR code: %d\n", status)
246 PRINTF1("in INIT *** in suspend_science_tasks *** ERR code: %d\n", status)
248 }
247 }
249
248
250 // configure IRQ handling for the waveform picker unit
249 // configure IRQ handling for the waveform picker unit
251 status = rtems_interrupt_catch( waveforms_isr,
250 status = rtems_interrupt_catch( waveforms_isr,
252 IRQ_SPARC_WAVEFORM_PICKER,
251 IRQ_SPARC_WAVEFORM_PICKER,
253 &old_isr_handler) ;
252 &old_isr_handler) ;
254 // configure IRQ handling for the spectral matrices unit
253 // configure IRQ handling for the spectral matrices unit
255 status = rtems_interrupt_catch( spectral_matrices_isr,
254 status = rtems_interrupt_catch( spectral_matrices_isr,
256 IRQ_SPARC_SPECTRAL_MATRIX,
255 IRQ_SPARC_SPECTRAL_MATRIX,
257 &old_isr_handler) ;
256 &old_isr_handler) ;
258
257
259 // if the spacewire link is not up then send an event to the SPIQ task for link recovery
258 // if the spacewire link is not up then send an event to the SPIQ task for link recovery
260 if ( status_spw != RTEMS_SUCCESSFUL )
259 if ( status_spw != RTEMS_SUCCESSFUL )
261 {
260 {
262 status = rtems_event_send( Task_id[TASKID_SPIQ], SPW_LINKERR_EVENT );
261 status = rtems_event_send( Task_id[TASKID_SPIQ], SPW_LINKERR_EVENT );
263 if ( status != RTEMS_SUCCESSFUL ) {
262 if ( status != RTEMS_SUCCESSFUL ) {
264 PRINTF1("in INIT *** ERR rtems_event_send to SPIQ code %d\n", status )
263 PRINTF1("in INIT *** ERR rtems_event_send to SPIQ code %d\n", status )
265 }
264 }
266 }
265 }
267
266
268 BOOT_PRINTF("delete INIT\n")
267 BOOT_PRINTF("delete INIT\n")
269
268
270 set_hk_lfr_sc_potential_flag( true );
269 set_hk_lfr_sc_potential_flag( true );
271
270
272 status = rtems_task_delete(RTEMS_SELF);
271 status = rtems_task_delete(RTEMS_SELF);
273
272
274 }
273 }
275
274
276 void init_local_mode_parameters( void )
275 void init_local_mode_parameters( void )
277 {
276 {
278 /** This function initialize the param_local global variable with default values.
277 /** This function initialize the param_local global variable with default values.
279 *
278 *
280 */
279 */
281
280
282 unsigned int i;
281 unsigned int i;
283
282
284 // LOCAL PARAMETERS
283 // LOCAL PARAMETERS
285
284
286 BOOT_PRINTF1("local_sbm1_nb_cwf_max %d \n", param_local.local_sbm1_nb_cwf_max)
285 BOOT_PRINTF1("local_sbm1_nb_cwf_max %d \n", param_local.local_sbm1_nb_cwf_max)
287 BOOT_PRINTF1("local_sbm2_nb_cwf_max %d \n", param_local.local_sbm2_nb_cwf_max)
286 BOOT_PRINTF1("local_sbm2_nb_cwf_max %d \n", param_local.local_sbm2_nb_cwf_max)
288 BOOT_PRINTF1("nb_interrupt_f0_MAX = %d\n", param_local.local_nb_interrupt_f0_MAX)
287 BOOT_PRINTF1("nb_interrupt_f0_MAX = %d\n", param_local.local_nb_interrupt_f0_MAX)
289
288
290 // init sequence counters
289 // init sequence counters
291
290
292 for(i = 0; i<SEQ_CNT_NB_DEST_ID; i++)
291 for(i = 0; i<SEQ_CNT_NB_DEST_ID; i++)
293 {
292 {
294 sequenceCounters_TC_EXE[i] = 0x00;
293 sequenceCounters_TC_EXE[i] = 0x00;
295 sequenceCounters_TM_DUMP[i] = 0x00;
294 sequenceCounters_TM_DUMP[i] = 0x00;
296 }
295 }
297 sequenceCounters_SCIENCE_NORMAL_BURST = 0x00;
296 sequenceCounters_SCIENCE_NORMAL_BURST = 0x00;
298 sequenceCounters_SCIENCE_SBM1_SBM2 = 0x00;
297 sequenceCounters_SCIENCE_SBM1_SBM2 = 0x00;
299 sequenceCounterHK = TM_PACKET_SEQ_CTRL_STANDALONE << 8;
298 sequenceCounterHK = TM_PACKET_SEQ_CTRL_STANDALONE << 8;
300 }
299 }
301
300
302 void reset_local_time( void )
301 void reset_local_time( void )
303 {
302 {
304 time_management_regs->ctrl = time_management_regs->ctrl | 0x02; // [0010] software reset, coarse time = 0x80000000
303 time_management_regs->ctrl = time_management_regs->ctrl | 0x02; // [0010] software reset, coarse time = 0x80000000
305 }
304 }
306
305
307 void create_names( void ) // create all names for tasks and queues
306 void create_names( void ) // create all names for tasks and queues
308 {
307 {
309 /** This function creates all RTEMS names used in the software for tasks and queues.
308 /** This function creates all RTEMS names used in the software for tasks and queues.
310 *
309 *
311 * @return RTEMS directive status codes:
310 * @return RTEMS directive status codes:
312 * - RTEMS_SUCCESSFUL - successful completion
311 * - RTEMS_SUCCESSFUL - successful completion
313 *
312 *
314 */
313 */
315
314
316 // task names
315 // task names
317 Task_name[TASKID_RECV] = rtems_build_name( 'R', 'E', 'C', 'V' );
316 Task_name[TASKID_RECV] = rtems_build_name( 'R', 'E', 'C', 'V' );
318 Task_name[TASKID_ACTN] = rtems_build_name( 'A', 'C', 'T', 'N' );
317 Task_name[TASKID_ACTN] = rtems_build_name( 'A', 'C', 'T', 'N' );
319 Task_name[TASKID_SPIQ] = rtems_build_name( 'S', 'P', 'I', 'Q' );
318 Task_name[TASKID_SPIQ] = rtems_build_name( 'S', 'P', 'I', 'Q' );
320 Task_name[TASKID_LOAD] = rtems_build_name( 'L', 'O', 'A', 'D' );
319 Task_name[TASKID_LOAD] = rtems_build_name( 'L', 'O', 'A', 'D' );
321 Task_name[TASKID_AVF0] = rtems_build_name( 'A', 'V', 'F', '0' );
320 Task_name[TASKID_AVF0] = rtems_build_name( 'A', 'V', 'F', '0' );
322 Task_name[TASKID_SWBD] = rtems_build_name( 'S', 'W', 'B', 'D' );
321 Task_name[TASKID_SWBD] = rtems_build_name( 'S', 'W', 'B', 'D' );
323 Task_name[TASKID_WFRM] = rtems_build_name( 'W', 'F', 'R', 'M' );
322 Task_name[TASKID_WFRM] = rtems_build_name( 'W', 'F', 'R', 'M' );
324 Task_name[TASKID_DUMB] = rtems_build_name( 'D', 'U', 'M', 'B' );
323 Task_name[TASKID_DUMB] = rtems_build_name( 'D', 'U', 'M', 'B' );
325 Task_name[TASKID_HOUS] = rtems_build_name( 'H', 'O', 'U', 'S' );
324 Task_name[TASKID_HOUS] = rtems_build_name( 'H', 'O', 'U', 'S' );
326 Task_name[TASKID_PRC0] = rtems_build_name( 'P', 'R', 'C', '0' );
325 Task_name[TASKID_PRC0] = rtems_build_name( 'P', 'R', 'C', '0' );
327 Task_name[TASKID_CWF3] = rtems_build_name( 'C', 'W', 'F', '3' );
326 Task_name[TASKID_CWF3] = rtems_build_name( 'C', 'W', 'F', '3' );
328 Task_name[TASKID_CWF2] = rtems_build_name( 'C', 'W', 'F', '2' );
327 Task_name[TASKID_CWF2] = rtems_build_name( 'C', 'W', 'F', '2' );
329 Task_name[TASKID_CWF1] = rtems_build_name( 'C', 'W', 'F', '1' );
328 Task_name[TASKID_CWF1] = rtems_build_name( 'C', 'W', 'F', '1' );
330 Task_name[TASKID_SEND] = rtems_build_name( 'S', 'E', 'N', 'D' );
329 Task_name[TASKID_SEND] = rtems_build_name( 'S', 'E', 'N', 'D' );
331 Task_name[TASKID_WTDG] = rtems_build_name( 'W', 'T', 'D', 'G' );
330 Task_name[TASKID_WTDG] = rtems_build_name( 'W', 'T', 'D', 'G' );
332 Task_name[TASKID_AVF1] = rtems_build_name( 'A', 'V', 'F', '1' );
331 Task_name[TASKID_AVF1] = rtems_build_name( 'A', 'V', 'F', '1' );
333 Task_name[TASKID_PRC1] = rtems_build_name( 'P', 'R', 'C', '1' );
332 Task_name[TASKID_PRC1] = rtems_build_name( 'P', 'R', 'C', '1' );
334 Task_name[TASKID_AVF2] = rtems_build_name( 'A', 'V', 'F', '2' );
333 Task_name[TASKID_AVF2] = rtems_build_name( 'A', 'V', 'F', '2' );
335 Task_name[TASKID_PRC2] = rtems_build_name( 'P', 'R', 'C', '2' );
334 Task_name[TASKID_PRC2] = rtems_build_name( 'P', 'R', 'C', '2' );
336
335
337 // rate monotonic period names
336 // rate monotonic period names
338 name_hk_rate_monotonic = rtems_build_name( 'H', 'O', 'U', 'S' );
337 name_hk_rate_monotonic = rtems_build_name( 'H', 'O', 'U', 'S' );
339
338
340 misc_name[QUEUE_RECV] = rtems_build_name( 'Q', '_', 'R', 'V' );
339 misc_name[QUEUE_RECV] = rtems_build_name( 'Q', '_', 'R', 'V' );
341 misc_name[QUEUE_SEND] = rtems_build_name( 'Q', '_', 'S', 'D' );
340 misc_name[QUEUE_SEND] = rtems_build_name( 'Q', '_', 'S', 'D' );
342 misc_name[QUEUE_PRC0] = rtems_build_name( 'Q', '_', 'P', '0' );
341 misc_name[QUEUE_PRC0] = rtems_build_name( 'Q', '_', 'P', '0' );