##// END OF EJS Templates
AVGV modified...
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r352:c07c16776bd4 R3++ draft
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@@ -1,2 +1,2
1 1 3081d1f9bb20b2b64a192585337a292a9804e0c5 LFR_basic-parameters
2 e01ac8bd125a79a7af38b0e3ba0330f5be1a3c92 header/lfr_common_headers
2 7ee7da2ed42fbc9cd673ae7f3a865345cea0f83f header/lfr_common_headers
@@ -1,238 +1,235
1 1 #ifndef GRLIB_REGS_H_INCLUDED
2 2 #define GRLIB_REGS_H_INCLUDED
3 3
4 4 #define NB_GPTIMER 3
5 5
6 6 #include <stdint.h>
7 7
8 8 struct apbuart_regs_str{
9 9 volatile unsigned int data;
10 10 volatile unsigned int status;
11 11 volatile unsigned int ctrl;
12 12 volatile unsigned int scaler;
13 13 volatile unsigned int fifoDebug;
14 14 };
15 15
16 16 struct grgpio_regs_str{
17 17 volatile int io_port_data_register;
18 18 int io_port_output_register;
19 19 int io_port_direction_register;
20 20 int interrupt_mak_register;
21 21 int interrupt_polarity_register;
22 22 int interrupt_edge_register;
23 23 int bypass_register;
24 24 int reserved;
25 25 // 0x20-0x3c interrupt map register(s)
26 26 };
27 27
28 28 typedef struct {
29 29 volatile unsigned int counter;
30 30 volatile unsigned int reload;
31 31 volatile unsigned int ctrl;
32 32 volatile unsigned int unused;
33 33 } timer_regs_t;
34 34
35 35 //*************
36 36 //*************
37 37 // GPTIMER_REGS
38 38
39 39 #define GPTIMER_CLEAR_IRQ 0x00000010 // clear pending IRQ if any
40 40 #define GPTIMER_LD 0x00000004 // LD load value from the reload register
41 41 #define GPTIMER_EN 0x00000001 // EN enable the timer
42 42 #define GPTIMER_EN_MASK 0xfffffffe // EN enable the timer
43 43 #define GPTIMER_RS 0x00000002 // RS restart
44 44 #define GPTIMER_IE 0x00000008 // IE interrupt enable
45 45 #define GPTIMER_IE_MASK 0xffffffef // IE interrupt enable
46 46
47 47 typedef struct {
48 48 volatile unsigned int scaler_value;
49 49 volatile unsigned int scaler_reload;
50 50 volatile unsigned int conf;
51 51 volatile unsigned int unused0;
52 52 timer_regs_t timer[NB_GPTIMER];
53 53 } gptimer_regs_t;
54 54
55 55 //*********************
56 56 //*********************
57 57 // TIME_MANAGEMENT_REGS
58 58
59 59 #define VAL_SOFTWARE_RESET 0x02 // [0010] software reset
60 60 #define VAL_LFR_SYNCHRONIZED 0x80000000
61 61 #define BIT_SYNCHRONIZATION 31
62 62 #define COARSE_TIME_MASK 0x7fffffff
63 63 #define SYNC_BIT_MASK 0x7f
64 64 #define SYNC_BIT 0x80
65 65 #define BIT_CAL_RELOAD 0x00000010
66 66 #define MASK_CAL_RELOAD 0xffffffef // [1110 1111]
67 67 #define BIT_CAL_ENABLE 0x00000040
68 68 #define MASK_CAL_ENABLE 0xffffffbf // [1011 1111]
69 69 #define BIT_SET_INTERLEAVED 0x00000020 // [0010 0000]
70 70 #define MASK_SET_INTERLEAVED 0xffffffdf // [1101 1111]
71 71 #define BIT_SOFT_RESET 0x00000004 // [0100]
72 72 #define MASK_SOFT_RESET 0xfffffffb // [1011]
73 73
74 74 typedef struct {
75 75 volatile int ctrl; // bit 0 forces the load of the coarse_time_load value and resets the fine_time
76 76 // bit 1 is the soft reset for the time management module
77 77 // bit 2 is the soft reset for the waveform picker and the spectral matrix modules, set to 1 after HW reset
78 78 volatile int coarse_time_load;
79 79 volatile int coarse_time;
80 80 volatile int fine_time;
81 81 // TEMPERATURES
82 82 volatile int temp_pcb; // SEL1 = 0 SEL0 = 0
83 83 volatile int temp_fpga; // SEL1 = 0 SEL0 = 1
84 84 volatile int temp_scm; // SEL1 = 1 SEL0 = 0
85 85 // CALIBRATION
86 86 volatile unsigned int calDACCtrl;
87 87 volatile unsigned int calPrescaler;
88 88 volatile unsigned int calDivisor;
89 89 volatile unsigned int calDataPtr;
90 90 volatile unsigned int calData;
91 91 } time_management_regs_t;
92 92
93 93 //*********************
94 94 //*********************
95 95 // WAVEFORM_PICKER_REGS
96 96
97 97 #define BITS_WFP_STATUS_F3 0xc0 // [1100 0000] check the f3 full bits
98 98 #define BIT_WFP_BUF_F3_0 0x40 // [0100 0000] f3 buffer 0 is full
99 99 #define BIT_WFP_BUF_F3_1 0x80 // [1000 0000] f3 buffer 1 is full
100 100 #define RST_WFP_F3_0 0x00008840 // [1000 1000 0100 0000]
101 101 #define RST_WFP_F3_1 0x00008880 // [1000 1000 1000 0000]
102 102
103 103 #define BITS_WFP_STATUS_F2 0x30 // [0011 0000] get the status bits for f2
104 104 #define SHIFT_WFP_STATUS_F2 4
105 105 #define BIT_WFP_BUF_F2_0 0x10 // [0001 0000] f2 buffer 0 is full
106 106 #define BIT_WFP_BUF_F2_1 0x20 // [0010 0000] f2 buffer 1 is full
107 107 #define RST_WFP_F2_0 0x00004410 // [0100 0100 0001 0000]
108 108 #define RST_WFP_F2_1 0x00004420 // [0100 0100 0010 0000]
109 109
110 110 #define BITS_WFP_STATUS_F1 0x0c // [0000 1100] check the f1 full bits
111 111 #define BIT_WFP_BUF_F1_0 0x04 // [0000 0100] f1 buffer 0 is full
112 112 #define BIT_WFP_BUF_F1_1 0x08 // [0000 1000] f1 buffer 1 is full
113 113 #define RST_WFP_F1_0 0x00002204 // [0010 0010 0000 0100] f1 bits = 0
114 114 #define RST_WFP_F1_1 0x00002208 // [0010 0010 0000 1000] f1 bits = 0
115 115
116 116 #define BITS_WFP_STATUS_F0 0x03 // [0000 0011] check the f0 full bits
117 117 #define RST_WFP_F0_0 0x00001101 // [0001 0001 0000 0001]
118 118 #define RST_WFP_F0_1 0x00001102 // [0001 0001 0000 0010]
119 119
120 120 #define BIT_WFP_BUFFER_0 0x01
121 121 #define BIT_WFP_BUFFER_1 0x02
122 122
123 123 #define RST_BITS_RUN_BURST_EN 0x80 // [1000 0000] burst f2, f1, f0 enable f3, f2, f1, f0
124 124 #define BITS_WFP_ENABLE_ALL 0x0f // [0000 1111] enable f3, f2, f1, f0
125 125 #define BITS_WFP_ENABLE_BURST 0x0c // [0000 1100] enable f3, f2
126 126 #define RUN_BURST_ENABLE_SBM2 0x60 // [0110 0000] enable f2 and f1 burst
127 127 #define RUN_BURST_ENABLE_BURST 0x40 // [0100 0000] f2 burst enabled
128 128
129 129 #define DFLT_WFP_NB_DATA_BY_BUFFER 0xa7f // 0x30 *** 2688 - 1 => nb samples -1
130 130 #define DFLT_WFP_SNAPSHOT_PARAM 0xa80 // 0x34 *** 2688 => nb samples
131 131 #define DFLT_WFP_BUFFER_LENGTH 0x1f8 // buffer length in burst = 3 * 2688 / 16 = 504 = 0x1f8
132 132 #define DFLT_WFP_DELTA_F0_2 0x30 // 48 = 11 0000, max 7 bits
133 133
134 134 // PDB >= 0.1.28, 0x80000f54
135 135 typedef struct{
136 136 int data_shaping; // 0x00 00 *** R2 R1 R0 SP1 SP0 BW
137 137 int run_burst_enable; // 0x04 01 *** [run *** burst f2, f1, f0 *** enable f3, f2, f1, f0 ]
138 138 int addr_data_f0_0; // 0x08
139 139 int addr_data_f0_1; // 0x0c
140 140 int addr_data_f1_0; // 0x10
141 141 int addr_data_f1_1; // 0x14
142 142 int addr_data_f2_0; // 0x18
143 143 int addr_data_f2_1; // 0x1c
144 144 int addr_data_f3_0; // 0x20
145 145 int addr_data_f3_1; // 0x24
146 146 volatile int status; // 0x28
147 147 volatile int delta_snapshot; // 0x2c
148 148 int delta_f0; // 0x30
149 149 int delta_f0_2; // 0x34
150 150 int delta_f1; // 0x38
151 151 int delta_f2; // 0x3c
152 152 int nb_data_by_buffer; // 0x40 number of samples in a buffer = 2688
153 153 int snapshot_param; // 0x44
154 154 int start_date; // 0x48
155 155 //
156 156 volatile unsigned int f0_0_coarse_time; // 0x4c
157 157 volatile unsigned int f0_0_fine_time; // 0x50
158 158 volatile unsigned int f0_1_coarse_time; // 0x54
159 159 volatile unsigned int f0_1_fine_time; // 0x58
160 160 //
161 161 volatile unsigned int f1_0_coarse_time; // 0x5c
162 162 volatile unsigned int f1_0_fine_time; // 0x60
163 163 volatile unsigned int f1_1_coarse_time; // 0x64
164 164 volatile unsigned int f1_1_fine_time; // 0x68
165 165 //
166 166 volatile unsigned int f2_0_coarse_time; // 0x6c
167 167 volatile unsigned int f2_0_fine_time; // 0x70
168 168 volatile unsigned int f2_1_coarse_time; // 0x74
169 169 volatile unsigned int f2_1_fine_time; // 0x78
170 170 //
171 171 volatile unsigned int f3_0_coarse_time; // 0x7c => 0x7c + 0xf54 = 0xd0
172 172 volatile unsigned int f3_0_fine_time; // 0x80
173 173 volatile unsigned int f3_1_coarse_time; // 0x84
174 174 volatile unsigned int f3_1_fine_time; // 0x88
175 175 //
176 176 unsigned int buffer_length; // 0x8c = buffer length in burst 2688 / 16 = 168
177 177 //
178 volatile int16_t v_dummy; // 0x90
179 volatile int16_t v; // 0x90
180 volatile int16_t e1_dummy; // 0x94
181 volatile int16_t e1; // 0x94
182 volatile int16_t e2_dummy; // 0x98
183 volatile int16_t e2; // 0x98
178 volatile int v; // 0x90
179 volatile int e1; // 0x94
180 volatile int e2; // 0x98
184 181 } waveform_picker_regs_0_1_18_t;
185 182
186 183 //*********************
187 184 //*********************
188 185 // SPECTRAL_MATRIX_REGS
189 186
190 187 #define BITS_STATUS_F0 0x03 // [0011]
191 188 #define BITS_STATUS_F1 0x0c // [1100]
192 189 #define BITS_STATUS_F2 0x30 // [0011 0000]
193 190 #define BITS_HK_AA_SM 0x780 // [0111 1000 0000]
194 191 #define BITS_SM_ERR 0x7c0 // [0111 1100 0000]
195 192 #define BITS_STATUS_REG 0x7ff // [0111 1111 1111]
196 193 #define BIT_READY_0 0x1 // [01]
197 194 #define BIT_READY_1 0x2 // [10]
198 195 #define BIT_READY_0_1 0x3 // [11]
199 196 #define BIT_STATUS_F1_0 0x04 // [0100]
200 197 #define BIT_STATUS_F1_1 0x08 // [1000]
201 198 #define BIT_STATUS_F2_0 0x10 // [0001 0000]
202 199 #define BIT_STATUS_F2_1 0x20 // [0010 0000]
203 200 #define DEFAULT_MATRIX_LENGTH 0xc8 // 25 * 128 / 16 = 200 = 0xc8
204 201 #define BIT_IRQ_ON_NEW_MATRIX 0x01
205 202 #define MASK_IRQ_ON_NEW_MATRIX 0xfffffffe
206 203 #define BIT_IRQ_ON_ERROR 0x02
207 204 #define MASK_IRQ_ON_ERROR 0xfffffffd
208 205
209 206 typedef struct {
210 207 volatile int config; // 0x00
211 208 volatile int status; // 0x04
212 209 volatile int f0_0_address; // 0x08
213 210 volatile int f0_1_address; // 0x0C
214 211 //
215 212 volatile int f1_0_address; // 0x10
216 213 volatile int f1_1_address; // 0x14
217 214 volatile int f2_0_address; // 0x18
218 215 volatile int f2_1_address; // 0x1C
219 216 //
220 217 volatile unsigned int f0_0_coarse_time; // 0x20
221 218 volatile unsigned int f0_0_fine_time; // 0x24
222 219 volatile unsigned int f0_1_coarse_time; // 0x28
223 220 volatile unsigned int f0_1_fine_time; // 0x2C
224 221 //
225 222 volatile unsigned int f1_0_coarse_time; // 0x30
226 223 volatile unsigned int f1_0_fine_time; // 0x34
227 224 volatile unsigned int f1_1_coarse_time; // 0x38
228 225 volatile unsigned int f1_1_fine_time; // 0x3C
229 226 //
230 227 volatile unsigned int f2_0_coarse_time; // 0x40
231 228 volatile unsigned int f2_0_fine_time; // 0x44
232 229 volatile unsigned int f2_1_coarse_time; // 0x48
233 230 volatile unsigned int f2_1_fine_time; // 0x4C
234 231 //
235 232 unsigned int matrix_length; // 0x50, length of a spectral matrix in burst 3200 / 16 = 200 = 0xc8
236 233 } spectral_matrix_regs_t;
237 234
238 235 #endif // GRLIB_REGS_H_INCLUDED
@@ -1,122 +1,124
1 1 #ifndef TC_LOAD_DUMP_PARAMETERS_H
2 2 #define TC_LOAD_DUMP_PARAMETERS_H
3 3
4 4 #include <rtems.h>
5 5 #include <stdio.h>
6 6
7 7 #include "fsw_params.h"
8 8 #include "wf_handler.h"
9 9 #include "tm_lfr_tc_exe.h"
10 10 #include "fsw_misc.h"
11 11 #include "basic_parameters_params.h"
12 12 #include "avf0_prc0.h"
13 13
14 14 #define FLOAT_EQUAL_ZERO 0.001
15 15 #define NB_BINS_TO_REMOVE 3
16 16 #define FI_INTERVAL_COEFF 0.285
17 17 #define BIN_MIN 0
18 18 #define BIN_MAX 127
19 19 #define DELTAF_F0 96.
20 20 #define DELTAF_F1 16.
21 21 #define DELTAF_F2 1.
22 22 #define DELTAF_DIV 2.
23 23
24 24 #define BIT_RW1_F1 0x80
25 25 #define BIT_RW1_F2 0x40
26 26 #define BIT_RW2_F1 0x20
27 27 #define BIT_RW2_F2 0x10
28 28 #define BIT_RW3_F1 0x08
29 29 #define BIT_RW3_F2 0x04
30 30 #define BIT_RW4_F1 0x02
31 31 #define BIT_RW4_F2 0x01
32 32
33 33 #define WHEEL_1 1
34 34 #define WHEEL_2 2
35 35 #define WHEEL_3 3
36 36 #define WHEEL_4 4
37 37 #define FREQ_1 1
38 38 #define FREQ_2 2
39 39 #define FREQ_3 3
40 40 #define FREQ_4 4
41 41 #define FLAG_OFFSET_WHEELS_1_3 8
42 42 #define FLAG_OFFSET_WHEELS_2_4 4
43 43
44 44 #define FLAG_NAN 0 // Not A NUMBER
45 45 #define FLAG_IAN 1 // Is A Number
46 46
47 47 #define SBM_KCOEFF_PER_NORM_KCOEFF 2
48 48
49 49 extern unsigned short sequenceCounterParameterDump;
50 50 extern unsigned short sequenceCounters_TM_DUMP[];
51 51 extern float k_coeff_intercalib_f0_norm[ ];
52 52 extern float k_coeff_intercalib_f0_sbm[ ];
53 53 extern float k_coeff_intercalib_f1_norm[ ];
54 54 extern float k_coeff_intercalib_f1_sbm[ ];
55 55 extern float k_coeff_intercalib_f2[ ];
56 56 extern fbins_masks_t fbins_masks;
57 57
58 58 int action_load_common_par( ccsdsTelecommandPacket_t *TC );
59 59 int action_load_normal_par(ccsdsTelecommandPacket_t *TC, rtems_id queue_id , unsigned char *time);
60 60 int action_load_burst_par(ccsdsTelecommandPacket_t *TC, rtems_id queue_id , unsigned char *time);
61 61 int action_load_sbm1_par(ccsdsTelecommandPacket_t *TC, rtems_id queue_id , unsigned char *time);
62 62 int action_load_sbm2_par(ccsdsTelecommandPacket_t *TC, rtems_id queue_id , unsigned char *time);
63 63 int action_load_kcoefficients(ccsdsTelecommandPacket_t *TC, rtems_id queue_id, unsigned char *time);
64 64 int action_load_fbins_mask(ccsdsTelecommandPacket_t *TC, rtems_id queue_id, unsigned char *time);
65 65 int action_load_filter_par(ccsdsTelecommandPacket_t *TC, rtems_id queue_id, unsigned char *time);
66 66 int action_dump_kcoefficients(ccsdsTelecommandPacket_t *TC, rtems_id queue_id, unsigned char *time);
67 67 int action_dump_par(ccsdsTelecommandPacket_t *TC, rtems_id queue_id );
68 68
69 69 // NORMAL
70 70 int check_normal_par_consistency( ccsdsTelecommandPacket_t *TC, rtems_id queue_id );
71 71 int set_sy_lfr_n_swf_l( ccsdsTelecommandPacket_t *TC );
72 72 int set_sy_lfr_n_swf_p( ccsdsTelecommandPacket_t *TC );
73 73 int set_sy_lfr_n_asm_p( ccsdsTelecommandPacket_t *TC );
74 74 int set_sy_lfr_n_bp_p0( ccsdsTelecommandPacket_t *TC );
75 75 int set_sy_lfr_n_bp_p1( ccsdsTelecommandPacket_t *TC );
76 76 int set_sy_lfr_n_cwf_long_f3( ccsdsTelecommandPacket_t *TC );
77 77
78 78 // BURST
79 79 int set_sy_lfr_b_bp_p0( ccsdsTelecommandPacket_t *TC );
80 80 int set_sy_lfr_b_bp_p1( ccsdsTelecommandPacket_t *TC );
81 81
82 82 // SBM1
83 83 int set_sy_lfr_s1_bp_p0( ccsdsTelecommandPacket_t *TC );
84 84 int set_sy_lfr_s1_bp_p1( ccsdsTelecommandPacket_t *TC );
85 85
86 86 // SBM2
87 87 int set_sy_lfr_s2_bp_p0( ccsdsTelecommandPacket_t *TC );
88 88 int set_sy_lfr_s2_bp_p1( ccsdsTelecommandPacket_t *TC );
89 89
90 90 // TC_LFR_UPDATE_INFO
91 91 unsigned int check_update_info_hk_lfr_mode( unsigned char mode );
92 92 unsigned int check_update_info_hk_tds_mode( unsigned char mode );
93 93 unsigned int check_update_info_hk_thr_mode( unsigned char mode );
94 94 void set_hk_lfr_sc_rw_f_flag( unsigned char wheel, unsigned char freq, float value );
95 95 void set_hk_lfr_sc_rw_f_flags( void );
96 int check_sy_lfr_rw_f( ccsdsTelecommandPacket_t *TC, int offset, int* pos, float* value );
97 int check_all_sy_lfr_rw_f( ccsdsTelecommandPacket_t *TC, int *pos, float*value );
96 98 void getReactionWheelsFrequencies( ccsdsTelecommandPacket_t *TC );
97 99 void setFBinMask(unsigned char *fbins_mask, float rw_f, unsigned char deltaFreq, float sy_lfr_rw_k );
98 100 void build_sy_lfr_rw_mask( unsigned int channel );
99 101 void build_sy_lfr_rw_masks();
100 102 void merge_fbins_masks( void );
101 103
102 104 // FBINS_MASK
103 105 int set_sy_lfr_fbins( ccsdsTelecommandPacket_t *TC );
104 106
105 107 // TC_LFR_LOAD_PARS_FILTER_PAR
106 108 int check_sy_lfr_rw_k( ccsdsTelecommandPacket_t *TC, int offset, int* pos, float* value );
107 109 int check_all_sy_lfr_rw_k( ccsdsTelecommandPacket_t *TC, int *pos, float*value );
108 110 int check_sy_lfr_filter_parameters( ccsdsTelecommandPacket_t *TC, rtems_id queue_id );
109 111
110 112 // KCOEFFICIENTS
111 113 int set_sy_lfr_kcoeff(ccsdsTelecommandPacket_t *TC , rtems_id queue_id);
112 114 void copyFloatByChar( unsigned char *destination, unsigned char *source );
113 115 void copyInt32ByChar( unsigned char *destination, unsigned char *source );
114 116 void copyInt16ByChar( unsigned char *destination, unsigned char *source );
115 117 void floatToChar( float value, unsigned char* ptr);
116 118
117 119 void init_parameter_dump( void );
118 120 void init_kcoefficients_dump( void );
119 121 void init_kcoefficients_dump_packet( Packet_TM_LFR_KCOEFFICIENTS_DUMP_t *kcoefficients_dump, unsigned char pkt_nr, unsigned char blk_nr );
120 122 void increment_seq_counter_destination_id_dump( unsigned char *packet_sequence_control, unsigned char destination_id );
121 123
122 124 #endif // TC_LOAD_DUMP_PARAMETERS_H
@@ -1,98 +1,98
1 1 /** Global variables of the LFR flight software.
2 2 *
3 3 * @file
4 4 * @author P. LEROY
5 5 *
6 6 * Among global variables, there are:
7 7 * - RTEMS names and id.
8 8 * - APB configuration registers.
9 9 * - waveforms global buffers, used by the waveform picker hardware module to store data.
10 10 * - spectral matrices buffesr, used by the hardware module to store data.
11 11 * - variable related to LFR modes parameters.
12 12 * - the global HK packet buffer.
13 13 * - the global dump parameter buffer.
14 14 *
15 15 */
16 16
17 17 #include <rtems.h>
18 18 #include <grspw.h>
19 19
20 20 #include "ccsds_types.h"
21 21 #include "grlib_regs.h"
22 22 #include "fsw_params.h"
23 23 #include "fsw_params_wf_handler.h"
24 24
25 25 #define NB_OF_TASKS 20
26 26 #define NB_OF_MISC_NAMES 5
27 27
28 28 // RTEMS GLOBAL VARIABLES
29 29 rtems_name misc_name[NB_OF_MISC_NAMES] = {0};
30 30 rtems_name Task_name[NB_OF_TASKS] = {0}; /* array of task names */
31 31 rtems_id Task_id[NB_OF_TASKS] = {0}; /* array of task ids */
32 32 rtems_name timecode_timer_name = 0;
33 33 rtems_id timecode_timer_id = RTEMS_ID_NONE;
34 34 rtems_name name_hk_rate_monotonic = 0; // name of the HK rate monotonic
35 35 rtems_id HK_id = RTEMS_ID_NONE;// id of the HK rate monotonic period
36 36 rtems_name name_avgv_rate_monotonic = 0; // name of the AVGV rate monotonic
37 37 rtems_id AVGV_id = RTEMS_ID_NONE;// id of the AVGV rate monotonic period
38 38 int fdSPW = 0;
39 39 int fdUART = 0;
40 40 unsigned char lfrCurrentMode = 0;
41 41 unsigned char pa_bia_status_info = 0;
42 42 unsigned char thisIsAnASMRestart = 0;
43 43 unsigned char oneTcLfrUpdateTimeReceived = 0;
44 44
45 45 // WAVEFORMS GLOBAL VARIABLES // 2048 * 3 * 4 + 2 * 4 = 24576 + 8 bytes = 24584
46 46 // 97 * 256 = 24832 => delta = 248 bytes = 62 words
47 47 // WAVEFORMS GLOBAL VARIABLES // 2688 * 3 * 4 + 2 * 4 = 32256 + 8 bytes = 32264
48 48 // 127 * 256 = 32512 => delta = 248 bytes = 62 words
49 49 // F0 F1 F2 F3
50 50 volatile int wf_buffer_f0[ NB_RING_NODES_F0 * WFRM_BUFFER ] __attribute__((aligned(0x100))) = {0};
51 51 volatile int wf_buffer_f1[ NB_RING_NODES_F1 * WFRM_BUFFER ] __attribute__((aligned(0x100))) = {0};
52 52 volatile int wf_buffer_f2[ NB_RING_NODES_F2 * WFRM_BUFFER ] __attribute__((aligned(0x100))) = {0};
53 53 volatile int wf_buffer_f3[ NB_RING_NODES_F3 * WFRM_BUFFER ] __attribute__((aligned(0x100))) = {0};
54 54
55 55 //***********************************
56 56 // SPECTRAL MATRICES GLOBAL VARIABLES
57 57
58 58 // alignment constraints for the spectral matrices buffers => the first data after the time (8 bytes) shall be aligned on 0x00
59 59 volatile int sm_f0[ NB_RING_NODES_SM_F0 * TOTAL_SIZE_SM ] __attribute__((aligned(0x100))) = {0};
60 60 volatile int sm_f1[ NB_RING_NODES_SM_F1 * TOTAL_SIZE_SM ] __attribute__((aligned(0x100))) = {0};
61 61 volatile int sm_f2[ NB_RING_NODES_SM_F2 * TOTAL_SIZE_SM ] __attribute__((aligned(0x100))) = {0};
62 62
63 63 // APB CONFIGURATION REGISTERS
64 64 time_management_regs_t *time_management_regs = (time_management_regs_t*) REGS_ADDR_TIME_MANAGEMENT;
65 65 gptimer_regs_t *gptimer_regs = (gptimer_regs_t *) REGS_ADDR_GPTIMER;
66 66 waveform_picker_regs_0_1_18_t *waveform_picker_regs = (waveform_picker_regs_0_1_18_t*) REGS_ADDR_WAVEFORM_PICKER;
67 67 spectral_matrix_regs_t *spectral_matrix_regs = (spectral_matrix_regs_t*) REGS_ADDR_SPECTRAL_MATRIX;
68 68
69 69 // MODE PARAMETERS
70 70 Packet_TM_LFR_PARAMETER_DUMP_t parameter_dump_packet = {0};
71 71 struct param_local_str param_local = {0};
72 72 unsigned int lastValidEnterModeTime = {0};
73 73
74 74 // HK PACKETS
75 75 Packet_TM_LFR_HK_t housekeeping_packet = {0};
76 76 // message queues occupancy
77 77 unsigned char hk_lfr_q_sd_fifo_size_max = 0;
78 78 unsigned char hk_lfr_q_rv_fifo_size_max = 0;
79 79 unsigned char hk_lfr_q_p0_fifo_size_max = 0;
80 80 unsigned char hk_lfr_q_p1_fifo_size_max = 0;
81 81 unsigned char hk_lfr_q_p2_fifo_size_max = 0;
82 82 // sequence counters are incremented by APID (PID + CAT) and destination ID
83 unsigned short sequenceCounters_SCIENCE_NORMAL_BURST = 0;
84 unsigned short sequenceCounters_SCIENCE_SBM1_SBM2 = 0;
85 unsigned short sequenceCounters_TC_EXE[SEQ_CNT_NB_DEST_ID] = {0};
86 unsigned short sequenceCounters_TM_DUMP[SEQ_CNT_NB_DEST_ID] = {0};
87 unsigned short sequenceCounterHK = {0};
88 spw_stats grspw_stats = {0};
83 unsigned short sequenceCounters_SCIENCE_NORMAL_BURST __attribute__((aligned(0x4))) = 0;
84 unsigned short sequenceCounters_SCIENCE_SBM1_SBM2 __attribute__((aligned(0x4))) = 0;
85 unsigned short sequenceCounters_TC_EXE[SEQ_CNT_NB_DEST_ID] __attribute__((aligned(0x4))) = {0};
86 unsigned short sequenceCounters_TM_DUMP[SEQ_CNT_NB_DEST_ID] __attribute__((aligned(0x4))) = {0};
87 unsigned short sequenceCounterHK __attribute__((aligned(0x4))) = {0};
88 spw_stats grspw_stats __attribute__((aligned(0x4))) = {0};
89 89
90 90 // TC_LFR_UPDATE_INFO
91 91 rw_f_t rw_f;
92 92
93 93 // TC_LFR_LOAD_FILTER_PAR
94 94 filterPar_t filterPar = {0};
95 95
96 96 fbins_masks_t fbins_masks = {0};
97 97 unsigned int acquisitionDurations[NB_ACQUISITION_DURATION]
98 98 = {ACQUISITION_DURATION_F0, ACQUISITION_DURATION_F1, ACQUISITION_DURATION_F2};
@@ -1,972 +1,972
1 1 /** This is the RTEMS initialization module.
2 2 *
3 3 * @file
4 4 * @author P. LEROY
5 5 *
6 6 * This module contains two very different information:
7 7 * - specific instructions to configure the compilation of the RTEMS executive
8 8 * - functions related to the fligth softwre initialization, especially the INIT RTEMS task
9 9 *
10 10 */
11 11
12 12 //*************************
13 13 // GPL reminder to be added
14 14 //*************************
15 15
16 16 #include <rtems.h>
17 17
18 18 /* configuration information */
19 19
20 20 #define CONFIGURE_INIT
21 21
22 22 #include <bsp.h> /* for device driver prototypes */
23 23
24 24 /* configuration information */
25 25
26 26 #define CONFIGURE_APPLICATION_NEEDS_CONSOLE_DRIVER
27 27 #define CONFIGURE_APPLICATION_NEEDS_CLOCK_DRIVER
28 28
29 29 #define CONFIGURE_MAXIMUM_TASKS 21 // number of tasks concurrently active including INIT
30 30 #define CONFIGURE_RTEMS_INIT_TASKS_TABLE
31 31 #define CONFIGURE_EXTRA_TASK_STACKS (3 * RTEMS_MINIMUM_STACK_SIZE)
32 32 #define CONFIGURE_LIBIO_MAXIMUM_FILE_DESCRIPTORS 32
33 33 #define CONFIGURE_INIT_TASK_PRIORITY 1 // instead of 100
34 34 #define CONFIGURE_INIT_TASK_MODE (RTEMS_DEFAULT_MODES | RTEMS_NO_PREEMPT)
35 35 #define CONFIGURE_INIT_TASK_ATTRIBUTES (RTEMS_DEFAULT_ATTRIBUTES | RTEMS_FLOATING_POINT)
36 36 #define CONFIGURE_MAXIMUM_DRIVERS 16
37 #define CONFIGURE_MAXIMUM_PERIODS 5 // [hous] [load] [avgv]
38 #define CONFIGURE_MAXIMUM_TIMERS 5 // [spiq] [link] [spacewire_reset_link]
37 #define CONFIGURE_MAXIMUM_PERIODS 6 // [hous] [load] [avgv]
38 #define CONFIGURE_MAXIMUM_TIMERS 6 // [spiq] [link] [spacewire_reset_link]
39 39 #define CONFIGURE_MAXIMUM_MESSAGE_QUEUES 5
40 40 #ifdef PRINT_STACK_REPORT
41 41 #define CONFIGURE_STACK_CHECKER_ENABLED
42 42 #endif
43 43
44 44 #include <rtems/confdefs.h>
45 45
46 46 /* If --drvmgr was enabled during the configuration of the RTEMS kernel */
47 47 #ifdef RTEMS_DRVMGR_STARTUP
48 48 #ifdef LEON3
49 49 /* Add Timer and UART Driver */
50 50
51 51 #ifdef CONFIGURE_APPLICATION_NEEDS_CLOCK_DRIVER
52 52 #define CONFIGURE_DRIVER_AMBAPP_GAISLER_GPTIMER
53 53 #endif
54 54
55 55 #ifdef CONFIGURE_APPLICATION_NEEDS_CONSOLE_DRIVER
56 56 #define CONFIGURE_DRIVER_AMBAPP_GAISLER_APBUART
57 57 #endif
58 58
59 59 #endif
60 60 #define CONFIGURE_DRIVER_AMBAPP_GAISLER_GRSPW /* GRSPW Driver */
61 61
62 62 #include <drvmgr/drvmgr_confdefs.h>
63 63 #endif
64 64
65 65 #include "fsw_init.h"
66 66 #include "fsw_config.c"
67 67 #include "GscMemoryLPP.hpp"
68 68
69 69 void initCache()
70 70 {
71 71 // ASI 2 contains a few control registers that have not been assigned as ancillary state registers.
72 72 // These should only be read and written using 32-bit LDA/STA instructions.
73 73 // All cache registers are accessed through load/store operations to the alternate address space (LDA/STA), using ASI = 2.
74 74 // The table below shows the register addresses:
75 75 // 0x00 Cache control register
76 76 // 0x04 Reserved
77 77 // 0x08 Instruction cache configuration register
78 78 // 0x0C Data cache configuration register
79 79
80 80 // Cache Control Register Leon3 / Leon3FT
81 81 // 31..30 29 28 27..24 23 22 21 20..19 18 17 16
82 82 // RFT PS TB DS FD FI FT ST IB
83 83 // 15 14 13..12 11..10 9..8 7..6 5 4 3..2 1..0
84 84 // IP DP ITE IDE DTE DDE DF IF DCS ICS
85 85
86 86 unsigned int cacheControlRegister;
87 87
88 88 CCR_resetCacheControlRegister();
89 89 ASR16_resetRegisterProtectionControlRegister();
90 90
91 91 cacheControlRegister = CCR_getValue();
92 92 PRINTF1("(0) CCR - Cache Control Register = %x\n", cacheControlRegister);
93 93 PRINTF1("(0) ASR16 = %x\n", *asr16Ptr);
94 94
95 95 CCR_enableInstructionCache(); // ICS bits
96 96 CCR_enableDataCache(); // DCS bits
97 97 CCR_enableInstructionBurstFetch(); // IB bit
98 98
99 99 faultTolerantScheme();
100 100
101 101 cacheControlRegister = CCR_getValue();
102 102 PRINTF1("(1) CCR - Cache Control Register = %x\n", cacheControlRegister);
103 103 PRINTF1("(1) ASR16 Register protection control register = %x\n", *asr16Ptr);
104 104
105 105 PRINTF("\n");
106 106 }
107 107
108 108 rtems_task Init( rtems_task_argument ignored )
109 109 {
110 110 /** This is the RTEMS INIT taks, it is the first task launched by the system.
111 111 *
112 112 * @param unused is the starting argument of the RTEMS task
113 113 *
114 114 * The INIT task create and run all other RTEMS tasks.
115 115 *
116 116 */
117 117
118 118 //***********
119 119 // INIT CACHE
120 120
121 121 unsigned char *vhdlVersion;
122 122
123 123 reset_lfr();
124 124
125 125 reset_local_time();
126 126
127 127 rtems_cpu_usage_reset();
128 128
129 129 rtems_status_code status;
130 130 rtems_status_code status_spw;
131 131 rtems_isr_entry old_isr_handler;
132 132
133 133 old_isr_handler = NULL;
134 134
135 135 // UART settings
136 136 enable_apbuart_transmitter();
137 137 set_apbuart_scaler_reload_register(REGS_ADDR_APBUART, APBUART_SCALER_RELOAD_VALUE);
138 138
139 139 DEBUG_PRINTF("\n\n\n\n\nIn INIT *** Now the console is on port COM1\n")
140 140
141 141
142 142 PRINTF("\n\n\n\n\n")
143 143
144 144 initCache();
145 145
146 146 PRINTF("*************************\n")
147 147 PRINTF("** LFR Flight Software **\n")
148 148
149 149 PRINTF1("** %d-", SW_VERSION_N1)
150 150 PRINTF1("%d-" , SW_VERSION_N2)
151 151 PRINTF1("%d-" , SW_VERSION_N3)
152 152 PRINTF1("%d **\n", SW_VERSION_N4)
153 153
154 154 vhdlVersion = (unsigned char *) (REGS_ADDR_VHDL_VERSION);
155 155 PRINTF("** VHDL **\n")
156 156 PRINTF1("** %d-", vhdlVersion[1])
157 157 PRINTF1("%d-" , vhdlVersion[2])
158 158 PRINTF1("%d **\n", vhdlVersion[3])
159 159 PRINTF("*************************\n")
160 160 PRINTF("\n\n")
161 161
162 162 init_parameter_dump();
163 163 init_kcoefficients_dump();
164 164 init_local_mode_parameters();
165 165 init_housekeeping_parameters();
166 166 init_k_coefficients_prc0();
167 167 init_k_coefficients_prc1();
168 168 init_k_coefficients_prc2();
169 169 pa_bia_status_info = INIT_CHAR;
170 170
171 171 // initialize all reaction wheels frequencies to NaN
172 172 rw_f.cp_rpw_sc_rw1_f1 = NAN;
173 173 rw_f.cp_rpw_sc_rw1_f2 = NAN;
174 174 rw_f.cp_rpw_sc_rw1_f3 = NAN;
175 175 rw_f.cp_rpw_sc_rw1_f4 = NAN;
176 176 rw_f.cp_rpw_sc_rw2_f1 = NAN;
177 177 rw_f.cp_rpw_sc_rw2_f2 = NAN;
178 178 rw_f.cp_rpw_sc_rw2_f3 = NAN;
179 179 rw_f.cp_rpw_sc_rw2_f4 = NAN;
180 180 rw_f.cp_rpw_sc_rw3_f1 = NAN;
181 181 rw_f.cp_rpw_sc_rw3_f2 = NAN;
182 182 rw_f.cp_rpw_sc_rw3_f3 = NAN;
183 183 rw_f.cp_rpw_sc_rw3_f4 = NAN;
184 184 rw_f.cp_rpw_sc_rw4_f1 = NAN;
185 185 rw_f.cp_rpw_sc_rw4_f2 = NAN;
186 186 rw_f.cp_rpw_sc_rw4_f3 = NAN;
187 187 rw_f.cp_rpw_sc_rw4_f4 = NAN;
188 188
189 189 // initialize filtering parameters
190 190 filterPar.spare_sy_lfr_pas_filter_enabled = DEFAULT_SY_LFR_PAS_FILTER_ENABLED;
191 191 filterPar.sy_lfr_pas_filter_modulus = DEFAULT_SY_LFR_PAS_FILTER_MODULUS;
192 192 filterPar.sy_lfr_pas_filter_tbad = DEFAULT_SY_LFR_PAS_FILTER_TBAD;
193 193 filterPar.sy_lfr_pas_filter_offset = DEFAULT_SY_LFR_PAS_FILTER_OFFSET;
194 194 filterPar.sy_lfr_pas_filter_shift = DEFAULT_SY_LFR_PAS_FILTER_SHIFT;
195 195 filterPar.sy_lfr_sc_rw_delta_f = DEFAULT_SY_LFR_SC_RW_DELTA_F;
196 196 update_last_valid_transition_date( DEFAULT_LAST_VALID_TRANSITION_DATE );
197 197
198 198 // waveform picker initialization
199 199 WFP_init_rings();
200 200 LEON_Clear_interrupt( IRQ_SPARC_GPTIMER_WATCHDOG ); // initialize the waveform rings
201 201 WFP_reset_current_ring_nodes();
202 202 reset_waveform_picker_regs();
203 203
204 204 // spectral matrices initialization
205 205 SM_init_rings(); // initialize spectral matrices rings
206 206 SM_reset_current_ring_nodes();
207 207 reset_spectral_matrix_regs();
208 208
209 209 // configure calibration
210 210 configureCalibration( false ); // true means interleaved mode, false is for normal mode
211 211
212 212 updateLFRCurrentMode( LFR_MODE_STANDBY );
213 213
214 214 BOOT_PRINTF1("in INIT *** lfrCurrentMode is %d\n", lfrCurrentMode)
215 215
216 216 create_names(); // create all names
217 217
218 218 status = create_timecode_timer(); // create the timer used by timecode_irq_handler
219 219 if (status != RTEMS_SUCCESSFUL)
220 220 {
221 221 PRINTF1("in INIT *** ERR in create_timer_timecode, code %d", status)
222 222 }
223 223
224 224 status = create_message_queues(); // create message queues
225 225 if (status != RTEMS_SUCCESSFUL)
226 226 {
227 227 PRINTF1("in INIT *** ERR in create_message_queues, code %d", status)
228 228 }
229 229
230 230 status = create_all_tasks(); // create all tasks
231 231 if (status != RTEMS_SUCCESSFUL)
232 232 {
233 233 PRINTF1("in INIT *** ERR in create_all_tasks, code %d\n", status)
234 234 }
235 235
236 236 // **************************
237 237 // <SPACEWIRE INITIALIZATION>
238 238 status_spw = spacewire_open_link(); // (1) open the link
239 239 if ( status_spw != RTEMS_SUCCESSFUL )
240 240 {
241 241 PRINTF1("in INIT *** ERR spacewire_open_link code %d\n", status_spw )
242 242 }
243 243
244 244 if ( status_spw == RTEMS_SUCCESSFUL ) // (2) configure the link
245 245 {
246 246 status_spw = spacewire_configure_link( fdSPW );
247 247 if ( status_spw != RTEMS_SUCCESSFUL )
248 248 {
249 249 PRINTF1("in INIT *** ERR spacewire_configure_link code %d\n", status_spw )
250 250 }
251 251 }
252 252
253 253 if ( status_spw == RTEMS_SUCCESSFUL) // (3) start the link
254 254 {
255 255 status_spw = spacewire_start_link( fdSPW );
256 256 if ( status_spw != RTEMS_SUCCESSFUL )
257 257 {
258 258 PRINTF1("in INIT *** ERR spacewire_start_link code %d\n", status_spw )
259 259 }
260 260 }
261 261 // </SPACEWIRE INITIALIZATION>
262 262 // ***************************
263 263
264 264 status = start_all_tasks(); // start all tasks
265 265 if (status != RTEMS_SUCCESSFUL)
266 266 {
267 267 PRINTF1("in INIT *** ERR in start_all_tasks, code %d", status)
268 268 }
269 269
270 270 // start RECV and SEND *AFTER* SpaceWire Initialization, due to the timeout of the start call during the initialization
271 271 status = start_recv_send_tasks();
272 272 if ( status != RTEMS_SUCCESSFUL )
273 273 {
274 274 PRINTF1("in INIT *** ERR start_recv_send_tasks code %d\n", status )
275 275 }
276 276
277 277 // suspend science tasks, they will be restarted later depending on the mode
278 278 status = suspend_science_tasks(); // suspend science tasks (not done in stop_current_mode if current mode = STANDBY)
279 279 if (status != RTEMS_SUCCESSFUL)
280 280 {
281 281 PRINTF1("in INIT *** in suspend_science_tasks *** ERR code: %d\n", status)
282 282 }
283 283
284 284 // configure IRQ handling for the waveform picker unit
285 285 status = rtems_interrupt_catch( waveforms_isr,
286 286 IRQ_SPARC_WAVEFORM_PICKER,
287 287 &old_isr_handler) ;
288 288 // configure IRQ handling for the spectral matrices unit
289 289 status = rtems_interrupt_catch( spectral_matrices_isr,
290 290 IRQ_SPARC_SPECTRAL_MATRIX,
291 291 &old_isr_handler) ;
292 292
293 293 // if the spacewire link is not up then send an event to the SPIQ task for link recovery
294 294 if ( status_spw != RTEMS_SUCCESSFUL )
295 295 {
296 296 status = rtems_event_send( Task_id[TASKID_SPIQ], SPW_LINKERR_EVENT );
297 297 if ( status != RTEMS_SUCCESSFUL ) {
298 298 PRINTF1("in INIT *** ERR rtems_event_send to SPIQ code %d\n", status )
299 299 }
300 300 }
301 301
302 302 BOOT_PRINTF("delete INIT\n")
303 303
304 304 set_hk_lfr_sc_potential_flag( true );
305 305
306 306 // start the timer to detect a missing spacewire timecode
307 307 // the timeout is larger because the spw IP needs to receive several valid timecodes before generating a tickout
308 308 // if a tickout is generated, the timer is restarted
309 309 status = rtems_timer_fire_after( timecode_timer_id, TIMECODE_TIMER_TIMEOUT_INIT, timecode_timer_routine, NULL );
310 310
311 311 grspw_timecode_callback = &timecode_irq_handler;
312 312
313 313 status = rtems_task_delete(RTEMS_SELF);
314 314
315 315 }
316 316
317 317 void init_local_mode_parameters( void )
318 318 {
319 319 /** This function initialize the param_local global variable with default values.
320 320 *
321 321 */
322 322
323 323 unsigned int i;
324 324
325 325 // LOCAL PARAMETERS
326 326
327 327 BOOT_PRINTF1("local_sbm1_nb_cwf_max %d \n", param_local.local_sbm1_nb_cwf_max)
328 328 BOOT_PRINTF1("local_sbm2_nb_cwf_max %d \n", param_local.local_sbm2_nb_cwf_max)
329 329
330 330 // init sequence counters
331 331
332 332 for(i = 0; i<SEQ_CNT_NB_DEST_ID; i++)
333 333 {
334 334 sequenceCounters_TC_EXE[i] = INIT_CHAR;
335 335 sequenceCounters_TM_DUMP[i] = INIT_CHAR;
336 336 }
337 337 sequenceCounters_SCIENCE_NORMAL_BURST = INIT_CHAR;
338 338 sequenceCounters_SCIENCE_SBM1_SBM2 = INIT_CHAR;
339 339 sequenceCounterHK = TM_PACKET_SEQ_CTRL_STANDALONE << TM_PACKET_SEQ_SHIFT;
340 340 }
341 341
342 342 void reset_local_time( void )
343 343 {
344 344 time_management_regs->ctrl = time_management_regs->ctrl | VAL_SOFTWARE_RESET; // [0010] software reset, coarse time = 0x80000000
345 345 }
346 346
347 347 void create_names( void ) // create all names for tasks and queues
348 348 {
349 349 /** This function creates all RTEMS names used in the software for tasks and queues.
350 350 *
351 351 * @return RTEMS directive status codes:
352 352 * - RTEMS_SUCCESSFUL - successful completion
353 353 *
354 354 */
355 355
356 356 // task names
357 357 Task_name[TASKID_AVGV] = rtems_build_name( 'A', 'V', 'G', 'V' );
358 358 Task_name[TASKID_RECV] = rtems_build_name( 'R', 'E', 'C', 'V' );
359 359 Task_name[TASKID_ACTN] = rtems_build_name( 'A', 'C', 'T', 'N' );
360 360 Task_name[TASKID_SPIQ] = rtems_build_name( 'S', 'P', 'I', 'Q' );
361 361 Task_name[TASKID_LOAD] = rtems_build_name( 'L', 'O', 'A', 'D' );
362 362 Task_name[TASKID_AVF0] = rtems_build_name( 'A', 'V', 'F', '0' );
363 363 Task_name[TASKID_SWBD] = rtems_build_name( 'S', 'W', 'B', 'D' );
364 364 Task_name[TASKID_WFRM] = rtems_build_name( 'W', 'F', 'R', 'M' );
365 365 Task_name[TASKID_DUMB] = rtems_build_name( 'D', 'U', 'M', 'B' );
366 366 Task_name[TASKID_HOUS] = rtems_build_name( 'H', 'O', 'U', 'S' );
367 367 Task_name[TASKID_PRC0] = rtems_build_name( 'P', 'R', 'C', '0' );
368 368 Task_name[TASKID_CWF3] = rtems_build_name( 'C', 'W', 'F', '3' );
369 369 Task_name[TASKID_CWF2] = rtems_build_name( 'C', 'W', 'F', '2' );
370 370 Task_name[TASKID_CWF1] = rtems_build_name( 'C', 'W', 'F', '1' );
371 371 Task_name[TASKID_SEND] = rtems_build_name( 'S', 'E', 'N', 'D' );
372 372 Task_name[TASKID_LINK] = rtems_build_name( 'L', 'I', 'N', 'K' );
373 373 Task_name[TASKID_AVF1] = rtems_build_name( 'A', 'V', 'F', '1' );
374 374 Task_name[TASKID_PRC1] = rtems_build_name( 'P', 'R', 'C', '1' );
375 375 Task_name[TASKID_AVF2] = rtems_build_name( 'A', 'V', 'F', '2' );
376 376 Task_name[TASKID_PRC2] = rtems_build_name( 'P', 'R', 'C', '2' );
377 377
378 378 // rate monotonic period names
379 379 name_hk_rate_monotonic = rtems_build_name( 'H', 'O', 'U', 'S' );
380 380 name_avgv_rate_monotonic = rtems_build_name( 'A', 'V', 'G', 'V' );
381 381
382 382 misc_name[QUEUE_RECV] = rtems_build_name( 'Q', '_', 'R', 'V' );
383 383 misc_name[QUEUE_SEND] = rtems_build_name( 'Q', '_', 'S', 'D' );
384 384 misc_name[QUEUE_PRC0] = rtems_build_name( 'Q', '_', 'P', '0' );
385 385 misc_name[QUEUE_PRC1] = rtems_build_name( 'Q', '_', 'P', '1' );
386 386 misc_name[QUEUE_PRC2] = rtems_build_name( 'Q', '_', 'P', '2' );
387 387
388 388 timecode_timer_name = rtems_build_name( 'S', 'P', 'T', 'C' );
389 389 }
390 390
391 391 int create_all_tasks( void ) // create all tasks which run in the software
392 392 {
393 393 /** This function creates all RTEMS tasks used in the software.
394 394 *
395 395 * @return RTEMS directive status codes:
396 396 * - RTEMS_SUCCESSFUL - task created successfully
397 397 * - RTEMS_INVALID_ADDRESS - id is NULL
398 398 * - RTEMS_INVALID_NAME - invalid task name
399 399 * - RTEMS_INVALID_PRIORITY - invalid task priority
400 400 * - RTEMS_MP_NOT_CONFIGURED - multiprocessing not configured
401 401 * - RTEMS_TOO_MANY - too many tasks created
402 402 * - RTEMS_UNSATISFIED - not enough memory for stack/FP context
403 403 * - RTEMS_TOO_MANY - too many global objects
404 404 *
405 405 */
406 406
407 407 rtems_status_code status;
408 408
409 409 //**********
410 410 // SPACEWIRE
411 411 // RECV
412 412 status = rtems_task_create(
413 413 Task_name[TASKID_RECV], TASK_PRIORITY_RECV, RTEMS_MINIMUM_STACK_SIZE,
414 414 RTEMS_DEFAULT_MODES,
415 415 RTEMS_DEFAULT_ATTRIBUTES, &Task_id[TASKID_RECV]
416 416 );
417 417 if (status == RTEMS_SUCCESSFUL) // SEND
418 418 {
419 419 status = rtems_task_create(
420 420 Task_name[TASKID_SEND], TASK_PRIORITY_SEND, RTEMS_MINIMUM_STACK_SIZE * STACK_SIZE_MULT,
421 421 RTEMS_DEFAULT_MODES,
422 422 RTEMS_DEFAULT_ATTRIBUTES | RTEMS_FLOATING_POINT, &Task_id[TASKID_SEND]
423 423