##// END OF EJS Templates
setFBinMask corrected...
paul -
r313:972ae9f0eb8f R3_plus draft
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@@ -1,2 +1,2
1 3081d1f9bb20b2b64a192585337a292a9804e0c5 LFR_basic-parameters
1 3081d1f9bb20b2b64a192585337a292a9804e0c5 LFR_basic-parameters
2 94f0f2fccbcb8030d9437ffbb69ee0eefaaea188 header/lfr_common_headers
2 57edc38eadba4601cf0b1e2fa1eeab85082e9f41 header/lfr_common_headers
@@ -1,106 +1,108
1 cmake_minimum_required (VERSION 2.6)
1 cmake_minimum_required (VERSION 2.6)
2 project (fsw)
2 project (fsw)
3
3
4 include(sparc-rtems)
4 include(sparc-rtems)
5 include(cppcheck)
5 include(cppcheck)
6
6
7 include_directories("../header"
7 include_directories("../header"
8 "../header/lfr_common_headers"
8 "../header/lfr_common_headers"
9 "../header/processing"
9 "../header/processing"
10 "../LFR_basic-parameters"
10 "../LFR_basic-parameters"
11 "../src")
11 "../src")
12
12
13 set(SOURCES wf_handler.c
13 set(SOURCES wf_handler.c
14 tc_handler.c
14 tc_handler.c
15 fsw_misc.c
15 fsw_misc.c
16 fsw_init.c
16 fsw_init.c
17 fsw_globals.c
17 fsw_globals.c
18 fsw_spacewire.c
18 fsw_spacewire.c
19 tc_load_dump_parameters.c
19 tc_load_dump_parameters.c
20 tm_lfr_tc_exe.c
20 tm_lfr_tc_exe.c
21 tc_acceptance.c
21 tc_acceptance.c
22 processing/fsw_processing.c
22 processing/fsw_processing.c
23 processing/avf0_prc0.c
23 processing/avf0_prc0.c
24 processing/avf1_prc1.c
24 processing/avf1_prc1.c
25 processing/avf2_prc2.c
25 processing/avf2_prc2.c
26 lfr_cpu_usage_report.c
26 lfr_cpu_usage_report.c
27 ${LFR_BP_SRC}
27 ${LFR_BP_SRC}
28 ../header/wf_handler.h
28 ../header/wf_handler.h
29 ../header/tc_handler.h
29 ../header/tc_handler.h
30 ../header/grlib_regs.h
30 ../header/grlib_regs.h
31 ../header/fsw_misc.h
31 ../header/fsw_misc.h
32 ../header/fsw_init.h
32 ../header/fsw_init.h
33 ../header/fsw_spacewire.h
33 ../header/fsw_spacewire.h
34 ../header/tc_load_dump_parameters.h
34 ../header/tc_load_dump_parameters.h
35 ../header/tm_lfr_tc_exe.h
35 ../header/tm_lfr_tc_exe.h
36 ../header/tc_acceptance.h
36 ../header/tc_acceptance.h
37 ../header/processing/fsw_processing.h
37 ../header/processing/fsw_processing.h
38 ../header/processing/avf0_prc0.h
38 ../header/processing/avf0_prc0.h
39 ../header/processing/avf1_prc1.h
39 ../header/processing/avf1_prc1.h
40 ../header/processing/avf2_prc2.h
40 ../header/processing/avf2_prc2.h
41 ../header/fsw_params_wf_handler.h
41 ../header/fsw_params_wf_handler.h
42 ../header/lfr_cpu_usage_report.h
42 ../header/lfr_cpu_usage_report.h
43 ../header/lfr_common_headers/ccsds_types.h
43 ../header/lfr_common_headers/ccsds_types.h
44 ../header/lfr_common_headers/fsw_params.h
44 ../header/lfr_common_headers/fsw_params.h
45 ../header/lfr_common_headers/fsw_params_nb_bytes.h
45 ../header/lfr_common_headers/fsw_params_nb_bytes.h
46 ../header/lfr_common_headers/fsw_params_processing.h
46 ../header/lfr_common_headers/fsw_params_processing.h
47 ../header/lfr_common_headers/tm_byte_positions.h
47 ../header/lfr_common_headers/tm_byte_positions.h
48 ../LFR_basic-parameters/basic_parameters.h
48 ../LFR_basic-parameters/basic_parameters.h
49 ../LFR_basic-parameters/basic_parameters_params.h
49 ../LFR_basic-parameters/basic_parameters_params.h
50 ../header/GscMemoryLPP.hpp
50 ../header/GscMemoryLPP.hpp
51 )
51 )
52
52
53
53
54 option(FSW_verbose "Enable verbose LFR" ON)
54 option(FSW_verbose "Enable verbose LFR" ON)
55 option(FSW_boot_messages "Enable LFR boot messages" ON)
55 option(FSW_boot_messages "Enable LFR boot messages" ON)
56 option(FSW_debug_messages "Enable LFR debug messages" ON)
56 option(FSW_debug_messages "Enable LFR debug messages" ON)
57 option(FSW_cpu_usage_report "Enable LFR cpu usage report" OFF)
57 option(FSW_cpu_usage_report "Enable LFR cpu usage report" OFF)
58 option(FSW_stack_report "Enable LFR stack report" OFF)
58 option(FSW_stack_report "Enable LFR stack report" OFF)
59 option(FSW_vhdl_dev "?" OFF)
59 option(FSW_vhdl_dev "?" OFF)
60 option(FSW_lpp_dpu_destid "Set to debug at LPP" ON)
60 option(FSW_lpp_dpu_destid "Set to debug at LPP" ON)
61 option(FSW_debug_watchdog "Enable debug watchdog" OFF)
61 option(FSW_debug_watchdog "Enable debug watchdog" OFF)
62 option(FSW_debug_tch "?" OFF)
62 option(FSW_debug_tch "?" OFF)
63
63
64 set(SW_VERSION_N1 "3" CACHE STRING "Choose N1 FSW Version." FORCE)
64 set(SW_VERSION_N1 "3" CACHE STRING "Choose N1 FSW Version." FORCE)
65 set(SW_VERSION_N2 "1" CACHE STRING "Choose N2 FSW Version." FORCE)
65 set(SW_VERSION_N2 "1" CACHE STRING "Choose N2 FSW Version." FORCE)
66 set(SW_VERSION_N3 "0" CACHE STRING "Choose N3 FSW Version." FORCE)
66 set(SW_VERSION_N3 "0" CACHE STRING "Choose N3 FSW Version." FORCE)
67 set(SW_VERSION_N4 "4" CACHE STRING "Choose N4 FSW Version." FORCE)
67 set(SW_VERSION_N4 "4" CACHE STRING "Choose N4 FSW Version." FORCE)
68
68
69
69
70 if(FSW_verbose)
70 if(FSW_verbose)
71 add_definitions(-DPRINT_MESSAGES_ON_CONSOLE)
71 add_definitions(-DPRINT_MESSAGES_ON_CONSOLE)
72 endif()
72 endif()
73 if(FSW_boot_messages)
73 if(FSW_boot_messages)
74 add_definitions(-DBOOT_MESSAGES)
74 add_definitions(-DBOOT_MESSAGES)
75 endif()
75 endif()
76 if(FSW_debug_messages)
76 if(FSW_debug_messages)
77 add_definitions(-DDEBUG_MESSAGES)
77 add_definitions(-DDEBUG_MESSAGES)
78 endif()
78 endif()
79 if(FSW_cpu_usage_report)
79 if(FSW_cpu_usage_report)
80 add_definitions(-DPRINT_TASK_STATISTICS)
80 add_definitions(-DPRINT_TASK_STATISTICS)
81 endif()
81 endif()
82 if(FSW_stack_report)
82 if(FSW_stack_report)
83 add_definitions(-DPRINT_STACK_REPORT)
83 add_definitions(-DPRINT_STACK_REPORT)
84 endif()
84 endif()
85 if(FSW_vhdl_dev)
85 if(FSW_vhdl_dev)
86 add_definitions(-DVHDL_DEV)
86 add_definitions(-DVHDL_DEV)
87 endif()
87 endif()
88 if(FSW_lpp_dpu_destid)
88 if(FSW_lpp_dpu_destid)
89 add_definitions(-DLPP_DPU_DESTID)
89 add_definitions(-DLPP_DPU_DESTID)
90 endif()
90 endif()
91 if(FSW_debug_watchdog)
91 if(FSW_debug_watchdog)
92 add_definitions(-DDEBUG_WATCHDOG)
92 add_definitions(-DDEBUG_WATCHDOG)
93 endif()
93 endif()
94 if(FSW_debug_tch)
94 if(FSW_debug_tch)
95 add_definitions(-DDEBUG_TCH)
95 add_definitions(-DDEBUG_TCH)
96 endif()
96 endif()
97
97
98 add_definitions(-DMSB_FIRST_TCH)
98 add_definitions(-DMSB_FIRST_TCH)
99
99
100 add_definitions(-DSWVERSION=-1-0)
100 add_definitions(-DSWVERSION=-1-0)
101 add_definitions(-DSW_VERSION_N1=${SW_VERSION_N1})
101 add_definitions(-DSW_VERSION_N1=${SW_VERSION_N1})
102 add_definitions(-DSW_VERSION_N2=${SW_VERSION_N2})
102 add_definitions(-DSW_VERSION_N2=${SW_VERSION_N2})
103 add_definitions(-DSW_VERSION_N3=${SW_VERSION_N3})
103 add_definitions(-DSW_VERSION_N3=${SW_VERSION_N3})
104 add_definitions(-DSW_VERSION_N4=${SW_VERSION_N4})
104 add_definitions(-DSW_VERSION_N4=${SW_VERSION_N4})
105
105
106 add_executable(FSW ${SOURCES})
106 add_executable(FSW ${SOURCES})
107 add_test_cppcheck(FSW STYLE UNUSED_FUNCTIONS POSSIBLE_ERROR MISSING_INCLUDE)
108
@@ -1,786 +1,786
1 /** Functions related to data processing.
1 /** Functions related to data processing.
2 *
2 *
3 * @file
3 * @file
4 * @author P. LEROY
4 * @author P. LEROY
5 *
5 *
6 * These function are related to data processing, i.e. spectral matrices averaging and basic parameters computation.
6 * These function are related to data processing, i.e. spectral matrices averaging and basic parameters computation.
7 *
7 *
8 */
8 */
9
9
10 #include "fsw_processing.h"
10 #include "fsw_processing.h"
11 #include "fsw_processing_globals.c"
11 #include "fsw_processing_globals.c"
12 #include "fsw_init.h"
12 #include "fsw_init.h"
13
13
14 unsigned int nb_sm_f0;
14 unsigned int nb_sm_f0;
15 unsigned int nb_sm_f0_aux_f1;
15 unsigned int nb_sm_f0_aux_f1;
16 unsigned int nb_sm_f1;
16 unsigned int nb_sm_f1;
17 unsigned int nb_sm_f0_aux_f2;
17 unsigned int nb_sm_f0_aux_f2;
18
18
19 typedef enum restartState_t
19 typedef enum restartState_t
20 {
20 {
21 WAIT_FOR_F2,
21 WAIT_FOR_F2,
22 WAIT_FOR_F1,
22 WAIT_FOR_F1,
23 WAIT_FOR_F0
23 WAIT_FOR_F0
24 } restartState;
24 } restartState;
25
25
26 //************************
26 //************************
27 // spectral matrices rings
27 // spectral matrices rings
28 ring_node sm_ring_f0[ NB_RING_NODES_SM_F0 ];
28 ring_node sm_ring_f0[ NB_RING_NODES_SM_F0 ];
29 ring_node sm_ring_f1[ NB_RING_NODES_SM_F1 ];
29 ring_node sm_ring_f1[ NB_RING_NODES_SM_F1 ];
30 ring_node sm_ring_f2[ NB_RING_NODES_SM_F2 ];
30 ring_node sm_ring_f2[ NB_RING_NODES_SM_F2 ];
31 ring_node *current_ring_node_sm_f0;
31 ring_node *current_ring_node_sm_f0;
32 ring_node *current_ring_node_sm_f1;
32 ring_node *current_ring_node_sm_f1;
33 ring_node *current_ring_node_sm_f2;
33 ring_node *current_ring_node_sm_f2;
34 ring_node *ring_node_for_averaging_sm_f0;
34 ring_node *ring_node_for_averaging_sm_f0;
35 ring_node *ring_node_for_averaging_sm_f1;
35 ring_node *ring_node_for_averaging_sm_f1;
36 ring_node *ring_node_for_averaging_sm_f2;
36 ring_node *ring_node_for_averaging_sm_f2;
37
37
38 //
38 //
39 ring_node * getRingNodeForAveraging( unsigned char frequencyChannel)
39 ring_node * getRingNodeForAveraging( unsigned char frequencyChannel)
40 {
40 {
41 ring_node *node;
41 ring_node *node;
42
42
43 node = NULL;
43 node = NULL;
44 switch ( frequencyChannel ) {
44 switch ( frequencyChannel ) {
45 case 0:
45 case 0:
46 node = ring_node_for_averaging_sm_f0;
46 node = ring_node_for_averaging_sm_f0;
47 break;
47 break;
48 case 1:
48 case 1:
49 node = ring_node_for_averaging_sm_f1;
49 node = ring_node_for_averaging_sm_f1;
50 break;
50 break;
51 case 2:
51 case 2:
52 node = ring_node_for_averaging_sm_f2;
52 node = ring_node_for_averaging_sm_f2;
53 break;
53 break;
54 default:
54 default:
55 break;
55 break;
56 }
56 }
57
57
58 return node;
58 return node;
59 }
59 }
60
60
61 //***********************************************************
61 //***********************************************************
62 // Interrupt Service Routine for spectral matrices processing
62 // Interrupt Service Routine for spectral matrices processing
63
63
64 void spectral_matrices_isr_f0( int statusReg )
64 void spectral_matrices_isr_f0( int statusReg )
65 {
65 {
66 unsigned char status;
66 unsigned char status;
67 rtems_status_code status_code;
67 rtems_status_code status_code;
68 ring_node *full_ring_node;
68 ring_node *full_ring_node;
69
69
70 status = (unsigned char) (statusReg & 0x03); // [0011] get the status_ready_matrix_f0_x bits
70 status = (unsigned char) (statusReg & 0x03); // [0011] get the status_ready_matrix_f0_x bits
71
71
72 switch(status)
72 switch(status)
73 {
73 {
74 case 0:
74 case 0:
75 break;
75 break;
76 case 3:
76 case 3:
77 // UNEXPECTED VALUE
77 // UNEXPECTED VALUE
78 spectral_matrix_regs->status = 0x03; // [0011]
78 spectral_matrix_regs->status = 0x03; // [0011]
79 status_code = rtems_event_send( Task_id[TASKID_DUMB], RTEMS_EVENT_11 );
79 status_code = rtems_event_send( Task_id[TASKID_DUMB], RTEMS_EVENT_11 );
80 break;
80 break;
81 case 1:
81 case 1:
82 full_ring_node = current_ring_node_sm_f0->previous;
82 full_ring_node = current_ring_node_sm_f0->previous;
83 full_ring_node->coarseTime = spectral_matrix_regs->f0_0_coarse_time;
83 full_ring_node->coarseTime = spectral_matrix_regs->f0_0_coarse_time;
84 full_ring_node->fineTime = spectral_matrix_regs->f0_0_fine_time;
84 full_ring_node->fineTime = spectral_matrix_regs->f0_0_fine_time;
85 current_ring_node_sm_f0 = current_ring_node_sm_f0->next;
85 current_ring_node_sm_f0 = current_ring_node_sm_f0->next;
86 spectral_matrix_regs->f0_0_address = current_ring_node_sm_f0->buffer_address;
86 spectral_matrix_regs->f0_0_address = current_ring_node_sm_f0->buffer_address;
87 // if there are enough ring nodes ready, wake up an AVFx task
87 // if there are enough ring nodes ready, wake up an AVFx task
88 nb_sm_f0 = nb_sm_f0 + 1;
88 nb_sm_f0 = nb_sm_f0 + 1;
89 if (nb_sm_f0 == NB_SM_BEFORE_AVF0)
89 if (nb_sm_f0 == NB_SM_BEFORE_AVF0)
90 {
90 {
91 ring_node_for_averaging_sm_f0 = full_ring_node;
91 ring_node_for_averaging_sm_f0 = full_ring_node;
92 if (rtems_event_send( Task_id[TASKID_AVF0], RTEMS_EVENT_0 ) != RTEMS_SUCCESSFUL)
92 if (rtems_event_send( Task_id[TASKID_AVF0], RTEMS_EVENT_0 ) != RTEMS_SUCCESSFUL)
93 {
93 {
94 status_code = rtems_event_send( Task_id[TASKID_DUMB], RTEMS_EVENT_3 );
94 status_code = rtems_event_send( Task_id[TASKID_DUMB], RTEMS_EVENT_3 );
95 }
95 }
96 nb_sm_f0 = 0;
96 nb_sm_f0 = 0;
97 }
97 }
98 spectral_matrix_regs->status = 0x01; // [0000 0001]
98 spectral_matrix_regs->status = 0x01; // [0000 0001]
99 break;
99 break;
100 case 2:
100 case 2:
101 full_ring_node = current_ring_node_sm_f0->previous;
101 full_ring_node = current_ring_node_sm_f0->previous;
102 full_ring_node->coarseTime = spectral_matrix_regs->f0_1_coarse_time;
102 full_ring_node->coarseTime = spectral_matrix_regs->f0_1_coarse_time;
103 full_ring_node->fineTime = spectral_matrix_regs->f0_1_fine_time;
103 full_ring_node->fineTime = spectral_matrix_regs->f0_1_fine_time;
104 current_ring_node_sm_f0 = current_ring_node_sm_f0->next;
104 current_ring_node_sm_f0 = current_ring_node_sm_f0->next;
105 spectral_matrix_regs->f0_1_address = current_ring_node_sm_f0->buffer_address;
105 spectral_matrix_regs->f0_1_address = current_ring_node_sm_f0->buffer_address;
106 // if there are enough ring nodes ready, wake up an AVFx task
106 // if there are enough ring nodes ready, wake up an AVFx task
107 nb_sm_f0 = nb_sm_f0 + 1;
107 nb_sm_f0 = nb_sm_f0 + 1;
108 if (nb_sm_f0 == NB_SM_BEFORE_AVF0)
108 if (nb_sm_f0 == NB_SM_BEFORE_AVF0)
109 {
109 {
110 ring_node_for_averaging_sm_f0 = full_ring_node;
110 ring_node_for_averaging_sm_f0 = full_ring_node;
111 if (rtems_event_send( Task_id[TASKID_AVF0], RTEMS_EVENT_0 ) != RTEMS_SUCCESSFUL)
111 if (rtems_event_send( Task_id[TASKID_AVF0], RTEMS_EVENT_0 ) != RTEMS_SUCCESSFUL)
112 {
112 {
113 status_code = rtems_event_send( Task_id[TASKID_DUMB], RTEMS_EVENT_3 );
113 status_code = rtems_event_send( Task_id[TASKID_DUMB], RTEMS_EVENT_3 );
114 }
114 }
115 nb_sm_f0 = 0;
115 nb_sm_f0 = 0;
116 }
116 }
117 spectral_matrix_regs->status = 0x02; // [0000 0010]
117 spectral_matrix_regs->status = 0x02; // [0000 0010]
118 break;
118 break;
119 }
119 }
120 }
120 }
121
121
122 void spectral_matrices_isr_f1( int statusReg )
122 void spectral_matrices_isr_f1( int statusReg )
123 {
123 {
124 rtems_status_code status_code;
124 rtems_status_code status_code;
125 unsigned char status;
125 unsigned char status;
126 ring_node *full_ring_node;
126 ring_node *full_ring_node;
127
127
128 status = (unsigned char) ((statusReg & 0x0c) >> 2); // [1100] get the status_ready_matrix_f1_x bits
128 status = (unsigned char) ((statusReg & 0x0c) >> 2); // [1100] get the status_ready_matrix_f1_x bits
129
129
130 switch(status)
130 switch(status)
131 {
131 {
132 case 0:
132 case 0:
133 break;
133 break;
134 case 3:
134 case 3:
135 // UNEXPECTED VALUE
135 // UNEXPECTED VALUE
136 spectral_matrix_regs->status = 0xc0; // [1100]
136 spectral_matrix_regs->status = 0xc0; // [1100]
137 status_code = rtems_event_send( Task_id[TASKID_DUMB], RTEMS_EVENT_11 );
137 status_code = rtems_event_send( Task_id[TASKID_DUMB], RTEMS_EVENT_11 );
138 break;
138 break;
139 case 1:
139 case 1:
140 full_ring_node = current_ring_node_sm_f1->previous;
140 full_ring_node = current_ring_node_sm_f1->previous;
141 full_ring_node->coarseTime = spectral_matrix_regs->f1_0_coarse_time;
141 full_ring_node->coarseTime = spectral_matrix_regs->f1_0_coarse_time;
142 full_ring_node->fineTime = spectral_matrix_regs->f1_0_fine_time;
142 full_ring_node->fineTime = spectral_matrix_regs->f1_0_fine_time;
143 current_ring_node_sm_f1 = current_ring_node_sm_f1->next;
143 current_ring_node_sm_f1 = current_ring_node_sm_f1->next;
144 spectral_matrix_regs->f1_0_address = current_ring_node_sm_f1->buffer_address;
144 spectral_matrix_regs->f1_0_address = current_ring_node_sm_f1->buffer_address;
145 // if there are enough ring nodes ready, wake up an AVFx task
145 // if there are enough ring nodes ready, wake up an AVFx task
146 nb_sm_f1 = nb_sm_f1 + 1;
146 nb_sm_f1 = nb_sm_f1 + 1;
147 if (nb_sm_f1 == NB_SM_BEFORE_AVF1)
147 if (nb_sm_f1 == NB_SM_BEFORE_AVF1)
148 {
148 {
149 ring_node_for_averaging_sm_f1 = full_ring_node;
149 ring_node_for_averaging_sm_f1 = full_ring_node;
150 if (rtems_event_send( Task_id[TASKID_AVF1], RTEMS_EVENT_0 ) != RTEMS_SUCCESSFUL)
150 if (rtems_event_send( Task_id[TASKID_AVF1], RTEMS_EVENT_0 ) != RTEMS_SUCCESSFUL)
151 {
151 {
152 status_code = rtems_event_send( Task_id[TASKID_DUMB], RTEMS_EVENT_3 );
152 status_code = rtems_event_send( Task_id[TASKID_DUMB], RTEMS_EVENT_3 );
153 }
153 }
154 nb_sm_f1 = 0;
154 nb_sm_f1 = 0;
155 }
155 }
156 spectral_matrix_regs->status = 0x04; // [0000 0100]
156 spectral_matrix_regs->status = 0x04; // [0000 0100]
157 break;
157 break;
158 case 2:
158 case 2:
159 full_ring_node = current_ring_node_sm_f1->previous;
159 full_ring_node = current_ring_node_sm_f1->previous;
160 full_ring_node->coarseTime = spectral_matrix_regs->f1_1_coarse_time;
160 full_ring_node->coarseTime = spectral_matrix_regs->f1_1_coarse_time;
161 full_ring_node->fineTime = spectral_matrix_regs->f1_1_fine_time;
161 full_ring_node->fineTime = spectral_matrix_regs->f1_1_fine_time;
162 current_ring_node_sm_f1 = current_ring_node_sm_f1->next;
162 current_ring_node_sm_f1 = current_ring_node_sm_f1->next;
163 spectral_matrix_regs->f1_1_address = current_ring_node_sm_f1->buffer_address;
163 spectral_matrix_regs->f1_1_address = current_ring_node_sm_f1->buffer_address;
164 // if there are enough ring nodes ready, wake up an AVFx task
164 // if there are enough ring nodes ready, wake up an AVFx task
165 nb_sm_f1 = nb_sm_f1 + 1;
165 nb_sm_f1 = nb_sm_f1 + 1;
166 if (nb_sm_f1 == NB_SM_BEFORE_AVF1)
166 if (nb_sm_f1 == NB_SM_BEFORE_AVF1)
167 {
167 {
168 ring_node_for_averaging_sm_f1 = full_ring_node;
168 ring_node_for_averaging_sm_f1 = full_ring_node;
169 if (rtems_event_send( Task_id[TASKID_AVF1], RTEMS_EVENT_0 ) != RTEMS_SUCCESSFUL)
169 if (rtems_event_send( Task_id[TASKID_AVF1], RTEMS_EVENT_0 ) != RTEMS_SUCCESSFUL)
170 {
170 {
171 status_code = rtems_event_send( Task_id[TASKID_DUMB], RTEMS_EVENT_3 );
171 status_code = rtems_event_send( Task_id[TASKID_DUMB], RTEMS_EVENT_3 );
172 }
172 }
173 nb_sm_f1 = 0;
173 nb_sm_f1 = 0;
174 }
174 }
175 spectral_matrix_regs->status = 0x08; // [1000 0000]
175 spectral_matrix_regs->status = 0x08; // [1000 0000]
176 break;
176 break;
177 }
177 }
178 }
178 }
179
179
180 void spectral_matrices_isr_f2( int statusReg )
180 void spectral_matrices_isr_f2( int statusReg )
181 {
181 {
182 unsigned char status;
182 unsigned char status;
183 rtems_status_code status_code;
183 rtems_status_code status_code;
184
184
185 status = (unsigned char) ((statusReg & 0x30) >> 4); // [0011 0000] get the status_ready_matrix_f2_x bits
185 status = (unsigned char) ((statusReg & 0x30) >> 4); // [0011 0000] get the status_ready_matrix_f2_x bits
186
186
187 switch(status)
187 switch(status)
188 {
188 {
189 case 0:
189 case 0:
190 break;
190 break;
191 case 3:
191 case 3:
192 // UNEXPECTED VALUE
192 // UNEXPECTED VALUE
193 spectral_matrix_regs->status = 0x30; // [0011 0000]
193 spectral_matrix_regs->status = 0x30; // [0011 0000]
194 status_code = rtems_event_send( Task_id[TASKID_DUMB], RTEMS_EVENT_11 );
194 status_code = rtems_event_send( Task_id[TASKID_DUMB], RTEMS_EVENT_11 );
195 break;
195 break;
196 case 1:
196 case 1:
197 ring_node_for_averaging_sm_f2 = current_ring_node_sm_f2->previous;
197 ring_node_for_averaging_sm_f2 = current_ring_node_sm_f2->previous;
198 current_ring_node_sm_f2 = current_ring_node_sm_f2->next;
198 current_ring_node_sm_f2 = current_ring_node_sm_f2->next;
199 ring_node_for_averaging_sm_f2->coarseTime = spectral_matrix_regs->f2_0_coarse_time;
199 ring_node_for_averaging_sm_f2->coarseTime = spectral_matrix_regs->f2_0_coarse_time;
200 ring_node_for_averaging_sm_f2->fineTime = spectral_matrix_regs->f2_0_fine_time;
200 ring_node_for_averaging_sm_f2->fineTime = spectral_matrix_regs->f2_0_fine_time;
201 spectral_matrix_regs->f2_0_address = current_ring_node_sm_f2->buffer_address;
201 spectral_matrix_regs->f2_0_address = current_ring_node_sm_f2->buffer_address;
202 spectral_matrix_regs->status = 0x10; // [0001 0000]
202 spectral_matrix_regs->status = 0x10; // [0001 0000]
203 if (rtems_event_send( Task_id[TASKID_AVF2], RTEMS_EVENT_0 ) != RTEMS_SUCCESSFUL)
203 if (rtems_event_send( Task_id[TASKID_AVF2], RTEMS_EVENT_0 ) != RTEMS_SUCCESSFUL)
204 {
204 {
205 status_code = rtems_event_send( Task_id[TASKID_DUMB], RTEMS_EVENT_3 );
205 status_code = rtems_event_send( Task_id[TASKID_DUMB], RTEMS_EVENT_3 );
206 }
206 }
207 break;
207 break;
208 case 2:
208 case 2:
209 ring_node_for_averaging_sm_f2 = current_ring_node_sm_f2->previous;
209 ring_node_for_averaging_sm_f2 = current_ring_node_sm_f2->previous;
210 current_ring_node_sm_f2 = current_ring_node_sm_f2->next;
210 current_ring_node_sm_f2 = current_ring_node_sm_f2->next;
211 ring_node_for_averaging_sm_f2->coarseTime = spectral_matrix_regs->f2_1_coarse_time;
211 ring_node_for_averaging_sm_f2->coarseTime = spectral_matrix_regs->f2_1_coarse_time;
212 ring_node_for_averaging_sm_f2->fineTime = spectral_matrix_regs->f2_1_fine_time;
212 ring_node_for_averaging_sm_f2->fineTime = spectral_matrix_regs->f2_1_fine_time;
213 spectral_matrix_regs->f2_1_address = current_ring_node_sm_f2->buffer_address;
213 spectral_matrix_regs->f2_1_address = current_ring_node_sm_f2->buffer_address;
214 spectral_matrix_regs->status = 0x20; // [0010 0000]
214 spectral_matrix_regs->status = 0x20; // [0010 0000]
215 if (rtems_event_send( Task_id[TASKID_AVF2], RTEMS_EVENT_0 ) != RTEMS_SUCCESSFUL)
215 if (rtems_event_send( Task_id[TASKID_AVF2], RTEMS_EVENT_0 ) != RTEMS_SUCCESSFUL)
216 {
216 {
217 status_code = rtems_event_send( Task_id[TASKID_DUMB], RTEMS_EVENT_3 );
217 status_code = rtems_event_send( Task_id[TASKID_DUMB], RTEMS_EVENT_3 );
218 }
218 }
219 break;
219 break;
220 }
220 }
221 }
221 }
222
222
223 void spectral_matrix_isr_error_handler( int statusReg )
223 void spectral_matrix_isr_error_handler( int statusReg )
224 {
224 {
225 // STATUS REGISTER
225 // STATUS REGISTER
226 // input_fifo_write(2) *** input_fifo_write(1) *** input_fifo_write(0)
226 // input_fifo_write(2) *** input_fifo_write(1) *** input_fifo_write(0)
227 // 10 9 8
227 // 10 9 8
228 // buffer_full ** [bad_component_err] ** f2_1 ** f2_0 ** f1_1 ** f1_0 ** f0_1 ** f0_0
228 // buffer_full ** [bad_component_err] ** f2_1 ** f2_0 ** f1_1 ** f1_0 ** f0_1 ** f0_0
229 // 7 6 5 4 3 2 1 0
229 // 7 6 5 4 3 2 1 0
230 // [bad_component_err] not defined in the last version of the VHDL code
230 // [bad_component_err] not defined in the last version of the VHDL code
231
231
232 rtems_status_code status_code;
232 rtems_status_code status_code;
233
233
234 //***************************************************
234 //***************************************************
235 // the ASM status register is copied in the HK packet
235 // the ASM status register is copied in the HK packet
236 housekeeping_packet.hk_lfr_vhdl_aa_sm = (unsigned char) (statusReg & 0x780 >> 7); // [0111 1000 0000]
236 housekeeping_packet.hk_lfr_vhdl_aa_sm = (unsigned char) (statusReg & 0x780 >> 7); // [0111 1000 0000]
237
237
238 if (statusReg & 0x7c0) // [0111 1100 0000]
238 if (statusReg & 0x7c0) // [0111 1100 0000]
239 {
239 {
240 status_code = rtems_event_send( Task_id[TASKID_DUMB], RTEMS_EVENT_8 );
240 status_code = rtems_event_send( Task_id[TASKID_DUMB], RTEMS_EVENT_8 );
241 }
241 }
242
242
243 spectral_matrix_regs->status = spectral_matrix_regs->status & 0x7c0;
243 spectral_matrix_regs->status = spectral_matrix_regs->status & 0x7c0;
244
244
245 }
245 }
246
246
247 rtems_isr spectral_matrices_isr( rtems_vector_number vector )
247 rtems_isr spectral_matrices_isr( rtems_vector_number vector )
248 {
248 {
249 // STATUS REGISTER
249 // STATUS REGISTER
250 // input_fifo_write(2) *** input_fifo_write(1) *** input_fifo_write(0)
250 // input_fifo_write(2) *** input_fifo_write(1) *** input_fifo_write(0)
251 // 10 9 8
251 // 10 9 8
252 // buffer_full ** bad_component_err ** f2_1 ** f2_0 ** f1_1 ** f1_0 ** f0_1 ** f0_0
252 // buffer_full ** bad_component_err ** f2_1 ** f2_0 ** f1_1 ** f1_0 ** f0_1 ** f0_0
253 // 7 6 5 4 3 2 1 0
253 // 7 6 5 4 3 2 1 0
254
254
255 int statusReg;
255 int statusReg;
256
256
257 static restartState state = WAIT_FOR_F2;
257 static restartState state = WAIT_FOR_F2;
258
258
259 statusReg = spectral_matrix_regs->status;
259 statusReg = spectral_matrix_regs->status;
260
260
261 if (thisIsAnASMRestart == 0)
261 if (thisIsAnASMRestart == 0)
262 { // this is not a restart sequence, process incoming matrices normally
262 { // this is not a restart sequence, process incoming matrices normally
263 spectral_matrices_isr_f0( statusReg );
263 spectral_matrices_isr_f0( statusReg );
264
264
265 spectral_matrices_isr_f1( statusReg );
265 spectral_matrices_isr_f1( statusReg );
266
266
267 spectral_matrices_isr_f2( statusReg );
267 spectral_matrices_isr_f2( statusReg );
268 }
268 }
269 else
269 else
270 { // a restart sequence has to be launched
270 { // a restart sequence has to be launched
271 switch (state) {
271 switch (state) {
272 case WAIT_FOR_F2:
272 case WAIT_FOR_F2:
273 if ((statusReg & 0x30) != 0x00) // [0011 0000] check the status_ready_matrix_f2_x bits
273 if ((statusReg & 0x30) != 0x00) // [0011 0000] check the status_ready_matrix_f2_x bits
274 {
274 {
275 state = WAIT_FOR_F1;
275 state = WAIT_FOR_F1;
276 }
276 }
277 break;
277 break;
278 case WAIT_FOR_F1:
278 case WAIT_FOR_F1:
279 if ((statusReg & 0x0c) != 0x00) // [0000 1100] check the status_ready_matrix_f1_x bits
279 if ((statusReg & 0x0c) != 0x00) // [0000 1100] check the status_ready_matrix_f1_x bits
280 {
280 {
281 state = WAIT_FOR_F0;
281 state = WAIT_FOR_F0;
282 }
282 }
283 break;
283 break;
284 case WAIT_FOR_F0:
284 case WAIT_FOR_F0:
285 if ((statusReg & 0x03) != 0x00) // [0000 0011] check the status_ready_matrix_f0_x bits
285 if ((statusReg & 0x03) != 0x00) // [0000 0011] check the status_ready_matrix_f0_x bits
286 {
286 {
287 state = WAIT_FOR_F2;
287 state = WAIT_FOR_F2;
288 thisIsAnASMRestart = 0;
288 thisIsAnASMRestart = 0;
289 }
289 }
290 break;
290 break;
291 default:
291 default:
292 break;
292 break;
293 }
293 }
294 reset_sm_status();
294 reset_sm_status();
295 }
295 }
296
296
297 spectral_matrix_isr_error_handler( statusReg );
297 spectral_matrix_isr_error_handler( statusReg );
298
298
299 }
299 }
300
300
301 //******************
301 //******************
302 // Spectral Matrices
302 // Spectral Matrices
303
303
304 void reset_nb_sm( void )
304 void reset_nb_sm( void )
305 {
305 {
306 nb_sm_f0 = 0;
306 nb_sm_f0 = 0;
307 nb_sm_f0_aux_f1 = 0;
307 nb_sm_f0_aux_f1 = 0;
308 nb_sm_f0_aux_f2 = 0;
308 nb_sm_f0_aux_f2 = 0;
309
309
310 nb_sm_f1 = 0;
310 nb_sm_f1 = 0;
311 }
311 }
312
312
313 void SM_init_rings( void )
313 void SM_init_rings( void )
314 {
314 {
315 init_ring( sm_ring_f0, NB_RING_NODES_SM_F0, sm_f0, TOTAL_SIZE_SM );
315 init_ring( sm_ring_f0, NB_RING_NODES_SM_F0, sm_f0, TOTAL_SIZE_SM );
316 init_ring( sm_ring_f1, NB_RING_NODES_SM_F1, sm_f1, TOTAL_SIZE_SM );
316 init_ring( sm_ring_f1, NB_RING_NODES_SM_F1, sm_f1, TOTAL_SIZE_SM );
317 init_ring( sm_ring_f2, NB_RING_NODES_SM_F2, sm_f2, TOTAL_SIZE_SM );
317 init_ring( sm_ring_f2, NB_RING_NODES_SM_F2, sm_f2, TOTAL_SIZE_SM );
318
318
319 DEBUG_PRINTF1("sm_ring_f0 @%x\n", (unsigned int) sm_ring_f0)
319 DEBUG_PRINTF1("sm_ring_f0 @%x\n", (unsigned int) sm_ring_f0)
320 DEBUG_PRINTF1("sm_ring_f1 @%x\n", (unsigned int) sm_ring_f1)
320 DEBUG_PRINTF1("sm_ring_f1 @%x\n", (unsigned int) sm_ring_f1)
321 DEBUG_PRINTF1("sm_ring_f2 @%x\n", (unsigned int) sm_ring_f2)
321 DEBUG_PRINTF1("sm_ring_f2 @%x\n", (unsigned int) sm_ring_f2)
322 DEBUG_PRINTF1("sm_f0 @%x\n", (unsigned int) sm_f0)
322 DEBUG_PRINTF1("sm_f0 @%x\n", (unsigned int) sm_f0)
323 DEBUG_PRINTF1("sm_f1 @%x\n", (unsigned int) sm_f1)
323 DEBUG_PRINTF1("sm_f1 @%x\n", (unsigned int) sm_f1)
324 DEBUG_PRINTF1("sm_f2 @%x\n", (unsigned int) sm_f2)
324 DEBUG_PRINTF1("sm_f2 @%x\n", (unsigned int) sm_f2)
325 }
325 }
326
326
327 void ASM_generic_init_ring( ring_node_asm *ring, unsigned char nbNodes )
327 void ASM_generic_init_ring( ring_node_asm *ring, unsigned char nbNodes )
328 {
328 {
329 unsigned char i;
329 unsigned char i;
330
330
331 ring[ nbNodes - 1 ].next
331 ring[ nbNodes - 1 ].next
332 = (ring_node_asm*) &ring[ 0 ];
332 = (ring_node_asm*) &ring[ 0 ];
333
333
334 for(i=0; i<nbNodes-1; i++)
334 for(i=0; i<nbNodes-1; i++)
335 {
335 {
336 ring[ i ].next = (ring_node_asm*) &ring[ i + 1 ];
336 ring[ i ].next = (ring_node_asm*) &ring[ i + 1 ];
337 }
337 }
338 }
338 }
339
339
340 void SM_reset_current_ring_nodes( void )
340 void SM_reset_current_ring_nodes( void )
341 {
341 {
342 current_ring_node_sm_f0 = sm_ring_f0[0].next;
342 current_ring_node_sm_f0 = sm_ring_f0[0].next;
343 current_ring_node_sm_f1 = sm_ring_f1[0].next;
343 current_ring_node_sm_f1 = sm_ring_f1[0].next;
344 current_ring_node_sm_f2 = sm_ring_f2[0].next;
344 current_ring_node_sm_f2 = sm_ring_f2[0].next;
345
345
346 ring_node_for_averaging_sm_f0 = NULL;
346 ring_node_for_averaging_sm_f0 = NULL;
347 ring_node_for_averaging_sm_f1 = NULL;
347 ring_node_for_averaging_sm_f1 = NULL;
348 ring_node_for_averaging_sm_f2 = NULL;
348 ring_node_for_averaging_sm_f2 = NULL;
349 }
349 }
350
350
351 //*****************
351 //*****************
352 // Basic Parameters
352 // Basic Parameters
353
353
354 void BP_init_header( bp_packet *packet,
354 void BP_init_header( bp_packet *packet,
355 unsigned int apid, unsigned char sid,
355 unsigned int apid, unsigned char sid,
356 unsigned int packetLength, unsigned char blkNr )
356 unsigned int packetLength, unsigned char blkNr )
357 {
357 {
358 packet->targetLogicalAddress = CCSDS_DESTINATION_ID;
358 packet->targetLogicalAddress = CCSDS_DESTINATION_ID;
359 packet->protocolIdentifier = CCSDS_PROTOCOLE_ID;
359 packet->protocolIdentifier = CCSDS_PROTOCOLE_ID;
360 packet->reserved = 0x00;
360 packet->reserved = 0x00;
361 packet->userApplication = CCSDS_USER_APP;
361 packet->userApplication = CCSDS_USER_APP;
362 packet->packetID[0] = (unsigned char) (apid >> 8);
362 packet->packetID[0] = (unsigned char) (apid >> 8);
363 packet->packetID[1] = (unsigned char) (apid);
363 packet->packetID[1] = (unsigned char) (apid);
364 packet->packetSequenceControl[0] = TM_PACKET_SEQ_CTRL_STANDALONE;
364 packet->packetSequenceControl[0] = TM_PACKET_SEQ_CTRL_STANDALONE;
365 packet->packetSequenceControl[1] = 0x00;
365 packet->packetSequenceControl[1] = 0x00;
366 packet->packetLength[0] = (unsigned char) (packetLength >> 8);
366 packet->packetLength[0] = (unsigned char) (packetLength >> 8);
367 packet->packetLength[1] = (unsigned char) (packetLength);
367 packet->packetLength[1] = (unsigned char) (packetLength);
368 // DATA FIELD HEADER
368 // DATA FIELD HEADER
369 packet->spare1_pusVersion_spare2 = 0x10;
369 packet->spare1_pusVersion_spare2 = 0x10;
370 packet->serviceType = TM_TYPE_LFR_SCIENCE; // service type
370 packet->serviceType = TM_TYPE_LFR_SCIENCE; // service type
371 packet->serviceSubType = TM_SUBTYPE_LFR_SCIENCE_3; // service subtype
371 packet->serviceSubType = TM_SUBTYPE_LFR_SCIENCE_3; // service subtype
372 packet->destinationID = TM_DESTINATION_ID_GROUND;
372 packet->destinationID = TM_DESTINATION_ID_GROUND;
373 packet->time[0] = 0x00;
373 packet->time[0] = 0x00;
374 packet->time[1] = 0x00;
374 packet->time[1] = 0x00;
375 packet->time[2] = 0x00;
375 packet->time[2] = 0x00;
376 packet->time[3] = 0x00;
376 packet->time[3] = 0x00;
377 packet->time[4] = 0x00;
377 packet->time[4] = 0x00;
378 packet->time[5] = 0x00;
378 packet->time[5] = 0x00;
379 // AUXILIARY DATA HEADER
379 // AUXILIARY DATA HEADER
380 packet->sid = sid;
380 packet->sid = sid;
381 packet->pa_bia_status_info = 0x00;
381 packet->pa_bia_status_info = 0x00;
382 packet->sy_lfr_common_parameters_spare = 0x00;
382 packet->sy_lfr_common_parameters_spare = 0x00;
383 packet->sy_lfr_common_parameters = 0x00;
383 packet->sy_lfr_common_parameters = 0x00;
384 packet->acquisitionTime[0] = 0x00;
384 packet->acquisitionTime[0] = 0x00;
385 packet->acquisitionTime[1] = 0x00;
385 packet->acquisitionTime[1] = 0x00;
386 packet->acquisitionTime[2] = 0x00;
386 packet->acquisitionTime[2] = 0x00;
387 packet->acquisitionTime[3] = 0x00;
387 packet->acquisitionTime[3] = 0x00;
388 packet->acquisitionTime[4] = 0x00;
388 packet->acquisitionTime[4] = 0x00;
389 packet->acquisitionTime[5] = 0x00;
389 packet->acquisitionTime[5] = 0x00;
390 packet->pa_lfr_bp_blk_nr[0] = 0x00; // BLK_NR MSB
390 packet->pa_lfr_bp_blk_nr[0] = 0x00; // BLK_NR MSB
391 packet->pa_lfr_bp_blk_nr[1] = blkNr; // BLK_NR LSB
391 packet->pa_lfr_bp_blk_nr[1] = blkNr; // BLK_NR LSB
392 }
392 }
393
393
394 void BP_init_header_with_spare( bp_packet_with_spare *packet,
394 void BP_init_header_with_spare( bp_packet_with_spare *packet,
395 unsigned int apid, unsigned char sid,
395 unsigned int apid, unsigned char sid,
396 unsigned int packetLength , unsigned char blkNr)
396 unsigned int packetLength , unsigned char blkNr)
397 {
397 {
398 packet->targetLogicalAddress = CCSDS_DESTINATION_ID;
398 packet->targetLogicalAddress = CCSDS_DESTINATION_ID;
399 packet->protocolIdentifier = CCSDS_PROTOCOLE_ID;
399 packet->protocolIdentifier = CCSDS_PROTOCOLE_ID;
400 packet->reserved = 0x00;
400 packet->reserved = 0x00;
401 packet->userApplication = CCSDS_USER_APP;
401 packet->userApplication = CCSDS_USER_APP;
402 packet->packetID[0] = (unsigned char) (apid >> 8);
402 packet->packetID[0] = (unsigned char) (apid >> 8);
403 packet->packetID[1] = (unsigned char) (apid);
403 packet->packetID[1] = (unsigned char) (apid);
404 packet->packetSequenceControl[0] = TM_PACKET_SEQ_CTRL_STANDALONE;
404 packet->packetSequenceControl[0] = TM_PACKET_SEQ_CTRL_STANDALONE;
405 packet->packetSequenceControl[1] = 0x00;
405 packet->packetSequenceControl[1] = 0x00;
406 packet->packetLength[0] = (unsigned char) (packetLength >> 8);
406 packet->packetLength[0] = (unsigned char) (packetLength >> 8);
407 packet->packetLength[1] = (unsigned char) (packetLength);
407 packet->packetLength[1] = (unsigned char) (packetLength);
408 // DATA FIELD HEADER
408 // DATA FIELD HEADER
409 packet->spare1_pusVersion_spare2 = 0x10;
409 packet->spare1_pusVersion_spare2 = 0x10;
410 packet->serviceType = TM_TYPE_LFR_SCIENCE; // service type
410 packet->serviceType = TM_TYPE_LFR_SCIENCE; // service type
411 packet->serviceSubType = TM_SUBTYPE_LFR_SCIENCE_3; // service subtype
411 packet->serviceSubType = TM_SUBTYPE_LFR_SCIENCE_3; // service subtype
412 packet->destinationID = TM_DESTINATION_ID_GROUND;
412 packet->destinationID = TM_DESTINATION_ID_GROUND;
413 // AUXILIARY DATA HEADER
413 // AUXILIARY DATA HEADER
414 packet->sid = sid;
414 packet->sid = sid;
415 packet->pa_bia_status_info = 0x00;
415 packet->pa_bia_status_info = 0x00;
416 packet->sy_lfr_common_parameters_spare = 0x00;
416 packet->sy_lfr_common_parameters_spare = 0x00;
417 packet->sy_lfr_common_parameters = 0x00;
417 packet->sy_lfr_common_parameters = 0x00;
418 packet->time[0] = 0x00;
418 packet->time[0] = 0x00;
419 packet->time[0] = 0x00;
419 packet->time[0] = 0x00;
420 packet->time[0] = 0x00;
420 packet->time[0] = 0x00;
421 packet->time[0] = 0x00;
421 packet->time[0] = 0x00;
422 packet->time[0] = 0x00;
422 packet->time[0] = 0x00;
423 packet->time[0] = 0x00;
423 packet->time[0] = 0x00;
424 packet->source_data_spare = 0x00;
424 packet->source_data_spare = 0x00;
425 packet->pa_lfr_bp_blk_nr[0] = 0x00; // BLK_NR MSB
425 packet->pa_lfr_bp_blk_nr[0] = 0x00; // BLK_NR MSB
426 packet->pa_lfr_bp_blk_nr[1] = blkNr; // BLK_NR LSB
426 packet->pa_lfr_bp_blk_nr[1] = blkNr; // BLK_NR LSB
427 }
427 }
428
428
429 void BP_send(char *data, rtems_id queue_id, unsigned int nbBytesToSend, unsigned int sid )
429 void BP_send(char *data, rtems_id queue_id, unsigned int nbBytesToSend, unsigned int sid )
430 {
430 {
431 rtems_status_code status;
431 rtems_status_code status;
432
432
433 // SEND PACKET
433 // SEND PACKET
434 status = rtems_message_queue_send( queue_id, data, nbBytesToSend);
434 status = rtems_message_queue_send( queue_id, data, nbBytesToSend);
435 if (status != RTEMS_SUCCESSFUL)
435 if (status != RTEMS_SUCCESSFUL)
436 {
436 {
437 PRINTF1("ERR *** in BP_send *** ERR %d\n", (int) status)
437 PRINTF1("ERR *** in BP_send *** ERR %d\n", (int) status)
438 }
438 }
439 }
439 }
440
440
441 void BP_send_s1_s2(char *data, rtems_id queue_id, unsigned int nbBytesToSend, unsigned int sid )
441 void BP_send_s1_s2(char *data, rtems_id queue_id, unsigned int nbBytesToSend, unsigned int sid )
442 {
442 {
443 /** This function is used to send the BP paquets when needed.
443 /** This function is used to send the BP paquets when needed.
444 *
444 *
445 * @param transitionCoarseTime is the requested transition time contained in the TC_LFR_ENTER_MODE
445 * @param transitionCoarseTime is the requested transition time contained in the TC_LFR_ENTER_MODE
446 *
446 *
447 * @return void
447 * @return void
448 *
448 *
449 * SBM1 and SBM2 paquets are sent depending on the type of the LFR mode transition.
449 * SBM1 and SBM2 paquets are sent depending on the type of the LFR mode transition.
450 * BURST paquets are sent everytime.
450 * BURST paquets are sent everytime.
451 *
451 *
452 */
452 */
453
453
454 rtems_status_code status;
454 rtems_status_code status;
455
455
456 // SEND PACKET
456 // SEND PACKET
457 // before lastValidTransitionDate, the data are drops even if they are ready
457 // before lastValidTransitionDate, the data are drops even if they are ready
458 // this guarantees that no SBM packets will be received before the requested enter mode time
458 // this guarantees that no SBM packets will be received before the requested enter mode time
459 if ( time_management_regs->coarse_time >= lastValidEnterModeTime)
459 if ( time_management_regs->coarse_time >= lastValidEnterModeTime)
460 {
460 {
461 status = rtems_message_queue_send( queue_id, data, nbBytesToSend);
461 status = rtems_message_queue_send( queue_id, data, nbBytesToSend);
462 if (status != RTEMS_SUCCESSFUL)
462 if (status != RTEMS_SUCCESSFUL)
463 {
463 {
464 PRINTF1("ERR *** in BP_send *** ERR %d\n", (int) status)
464 PRINTF1("ERR *** in BP_send *** ERR %d\n", (int) status)
465 }
465 }
466 }
466 }
467 }
467 }
468
468
469 //******************
469 //******************
470 // general functions
470 // general functions
471
471
472 void reset_sm_status( void )
472 void reset_sm_status( void )
473 {
473 {
474 // error
474 // error
475 // 10 --------------- 9 ---------------- 8 ---------------- 7 ---------
475 // 10 --------------- 9 ---------------- 8 ---------------- 7 ---------
476 // input_fif0_write_2 input_fifo_write_1 input_fifo_write_0 buffer_full
476 // input_fif0_write_2 input_fifo_write_1 input_fifo_write_0 buffer_full
477 // ---------- 5 -- 4 -- 3 -- 2 -- 1 -- 0 --
477 // ---------- 5 -- 4 -- 3 -- 2 -- 1 -- 0 --
478 // ready bits f2_1 f2_0 f1_1 f1_1 f0_1 f0_0
478 // ready bits f2_1 f2_0 f1_1 f1_1 f0_1 f0_0
479
479
480 spectral_matrix_regs->status = 0x7ff; // [0111 1111 1111]
480 spectral_matrix_regs->status = 0x7ff; // [0111 1111 1111]
481 }
481 }
482
482
483 void reset_spectral_matrix_regs( void )
483 void reset_spectral_matrix_regs( void )
484 {
484 {
485 /** This function resets the spectral matrices module registers.
485 /** This function resets the spectral matrices module registers.
486 *
486 *
487 * The registers affected by this function are located at the following offset addresses:
487 * The registers affected by this function are located at the following offset addresses:
488 *
488 *
489 * - 0x00 config
489 * - 0x00 config
490 * - 0x04 status
490 * - 0x04 status
491 * - 0x08 matrixF0_Address0
491 * - 0x08 matrixF0_Address0
492 * - 0x10 matrixFO_Address1
492 * - 0x10 matrixFO_Address1
493 * - 0x14 matrixF1_Address
493 * - 0x14 matrixF1_Address
494 * - 0x18 matrixF2_Address
494 * - 0x18 matrixF2_Address
495 *
495 *
496 */
496 */
497
497
498 set_sm_irq_onError( 0 );
498 set_sm_irq_onError( 0 );