##// END OF EJS Templates
Removed unused function and implemented scrubbing perriod counter...
jeandet -
r389:74df79cc7806 No PWD scrub with... draft
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@@ -1,157 +1,156
1 #ifndef FSW_MISC_H_INCLUDED
1 #ifndef FSW_MISC_H_INCLUDED
2 #define FSW_MISC_H_INCLUDED
2 #define FSW_MISC_H_INCLUDED
3
3
4 #include <rtems.h>
4 #include <rtems.h>
5 #include <stdio.h>
5 #include <stdio.h>
6 #include <grspw.h>
6 #include <grspw.h>
7 #include <grlib_regs.h>
7 #include <grlib_regs.h>
8
8
9 #include "fsw_params.h"
9 #include "fsw_params.h"
10 #include "fsw_spacewire.h"
10 #include "fsw_spacewire.h"
11 #include "lfr_cpu_usage_report.h"
11 #include "lfr_cpu_usage_report.h"
12
12
13 #define WATCHDOG_LOOP_PRINTF 10
13 #define WATCHDOG_LOOP_PRINTF 10
14 #define WATCHDOG_LOOP_DEBUG 3
14 #define WATCHDOG_LOOP_DEBUG 3
15
15
16 #define NB_RTEMS_EVENTS 32
16 #define NB_RTEMS_EVENTS 32
17 #define EVENT_12 12
17 #define EVENT_12 12
18 #define EVENT_13 13
18 #define EVENT_13 13
19 #define EVENT_14 14
19 #define EVENT_14 14
20 #define DUMB_MESSAGE_1 "in DUMB *** timecode_irq_handler"
20 #define DUMB_MESSAGE_1 "in DUMB *** timecode_irq_handler"
21 #define DUMB_MESSAGE_12 "WATCHDOG timer"
21 #define DUMB_MESSAGE_12 "WATCHDOG timer"
22 #define DUMB_MESSAGE_13 "TIMECODE timer"
22 #define DUMB_MESSAGE_13 "TIMECODE timer"
23
23
24 enum lfr_reset_cause_t{
24 enum lfr_reset_cause_t{
25 UNKNOWN_CAUSE,
25 UNKNOWN_CAUSE,
26 POWER_ON,
26 POWER_ON,
27 TC_RESET,
27 TC_RESET,
28 WATCHDOG,
28 WATCHDOG,
29 ERROR_RESET,
29 ERROR_RESET,
30 UNEXP_RESET
30 UNEXP_RESET
31 };
31 };
32
32
33 typedef struct{
33 typedef struct{
34 unsigned char dpu_spw_parity;
34 unsigned char dpu_spw_parity;
35 unsigned char dpu_spw_disconnect;
35 unsigned char dpu_spw_disconnect;
36 unsigned char dpu_spw_escape;
36 unsigned char dpu_spw_escape;
37 unsigned char dpu_spw_credit;
37 unsigned char dpu_spw_credit;
38 unsigned char dpu_spw_write_sync;
38 unsigned char dpu_spw_write_sync;
39 unsigned char timecode_erroneous;
39 unsigned char timecode_erroneous;
40 unsigned char timecode_missing;
40 unsigned char timecode_missing;
41 unsigned char timecode_invalid;
41 unsigned char timecode_invalid;
42 unsigned char time_timecode_it;
42 unsigned char time_timecode_it;
43 unsigned char time_not_synchro;
43 unsigned char time_not_synchro;
44 unsigned char time_timecode_ctr;
44 unsigned char time_timecode_ctr;
45 unsigned char ahb_correctable;
45 unsigned char ahb_correctable;
46 } hk_lfr_le_t;
46 } hk_lfr_le_t;
47
47
48 typedef struct{
48 typedef struct{
49 unsigned char dpu_spw_early_eop;
49 unsigned char dpu_spw_early_eop;
50 unsigned char dpu_spw_invalid_addr;
50 unsigned char dpu_spw_invalid_addr;
51 unsigned char dpu_spw_eep;
51 unsigned char dpu_spw_eep;
52 unsigned char dpu_spw_rx_too_big;
52 unsigned char dpu_spw_rx_too_big;
53 } hk_lfr_me_t;
53 } hk_lfr_me_t;
54
54
55 #define B00 196
55 #define B00 196
56 #define B01 196
56 #define B01 196
57 #define B02 0
57 #define B02 0
58 #define B10 131
58 #define B10 131
59 #define B11 -244
59 #define B11 -244
60 #define B12 131
60 #define B12 131
61 #define B20 161
61 #define B20 161
62 #define B21 -314
62 #define B21 -314
63 #define B22 161
63 #define B22 161
64
64
65 #define A00 1
65 #define A00 1
66 #define A01 -925
66 #define A01 -925
67 #define A02 0
67 #define A02 0
68 #define A10 1
68 #define A10 1
69 #define A11 -947
69 #define A11 -947
70 #define A12 439
70 #define A12 439
71 #define A20 1
71 #define A20 1
72 #define A21 -993
72 #define A21 -993
73 #define A22 486
73 #define A22 486
74
74
75 #define GAIN_B0 12
75 #define GAIN_B0 12
76 #define GAIN_B1 11
76 #define GAIN_B1 11
77 #define GAIN_B2 10
77 #define GAIN_B2 10
78
78
79 #define GAIN_A0 10
79 #define GAIN_A0 10
80 #define GAIN_A1 9
80 #define GAIN_A1 9
81 #define GAIN_A2 9
81 #define GAIN_A2 9
82
82
83 #define NB_COEFFS 3
83 #define NB_COEFFS 3
84 #define COEFF0 0
84 #define COEFF0 0
85 #define COEFF1 1
85 #define COEFF1 1
86 #define COEFF2 2
86 #define COEFF2 2
87
87
88 typedef struct filter_ctx
88 typedef struct filter_ctx
89 {
89 {
90 int W[NB_COEFFS][NB_COEFFS];
90 int W[NB_COEFFS][NB_COEFFS];
91 }filter_ctx;
91 }filter_ctx;
92
92
93 extern gptimer_regs_t *gptimer_regs;
93 extern gptimer_regs_t *gptimer_regs;
94 extern void ASR16_get_FPRF_IURF_ErrorCounters( unsigned int*, unsigned int* );
94 extern void ASR16_get_FPRF_IURF_ErrorCounters( unsigned int*, unsigned int* );
95 extern void CCR_getInstructionAndDataErrorCounters( unsigned int*, unsigned int* );
95 extern void CCR_getInstructionAndDataErrorCounters( unsigned int*, unsigned int* );
96
96
97 extern rtems_name name_hk_rate_monotonic; // name of the HK rate monotonic
97 extern rtems_name name_hk_rate_monotonic; // name of the HK rate monotonic
98 extern rtems_id HK_id;// id of the HK rate monotonic period
98 extern rtems_id HK_id;// id of the HK rate monotonic period
99 extern rtems_name name_avgv_rate_monotonic; // name of the AVGV rate monotonic
99 extern rtems_name name_avgv_rate_monotonic; // name of the AVGV rate monotonic
100 extern rtems_id AVGV_id;// id of the AVGV rate monotonic period
100 extern rtems_id AVGV_id;// id of the AVGV rate monotonic period
101
101
102 void timer_configure( unsigned char timer, unsigned int clock_divider,
102 void timer_configure( unsigned char timer, unsigned int clock_divider,
103 unsigned char interrupt_level, rtems_isr (*timer_isr)() );
103 unsigned char interrupt_level, rtems_isr (*timer_isr)() );
104 void timer_start( unsigned char timer );
104 void timer_start( unsigned char timer );
105 void timer_stop( unsigned char timer );
105 void timer_stop( unsigned char timer );
106 void timer_set_clock_divider(unsigned char timer, unsigned int clock_divider);
106 void timer_set_clock_divider(unsigned char timer, unsigned int clock_divider);
107
107
108 // WATCHDOG
108 // WATCHDOG
109 rtems_isr watchdog_isr( rtems_vector_number vector );
109 rtems_isr watchdog_isr( rtems_vector_number vector );
110 void watchdog_configure(void);
110 void watchdog_configure(void);
111 void watchdog_stop(void);
111 void watchdog_stop(void);
112 void watchdog_reload(void);
112 void watchdog_reload(void);
113 void watchdog_start(void);
113 void watchdog_start(void);
114
114
115 // SERIAL LINK
115 // SERIAL LINK
116 int send_console_outputs_on_apbuart_port( void );
116 int send_console_outputs_on_apbuart_port( void );
117 int enable_apbuart_transmitter( void );
117 int enable_apbuart_transmitter( void );
118 void set_apbuart_scaler_reload_register(unsigned int regs, unsigned int value);
118 void set_apbuart_scaler_reload_register(unsigned int regs, unsigned int value);
119
119
120 // RTEMS TASKS
120 // RTEMS TASKS
121 rtems_task load_task( rtems_task_argument argument );
121 rtems_task load_task( rtems_task_argument argument );
122 rtems_task hous_task( rtems_task_argument argument );
122 rtems_task hous_task( rtems_task_argument argument );
123 rtems_task avgv_task( rtems_task_argument argument );
123 rtems_task avgv_task( rtems_task_argument argument );
124 rtems_task dumb_task( rtems_task_argument unused );
124 rtems_task dumb_task( rtems_task_argument unused );
125 rtems_task scrubbing_task( rtems_task_argument unused );
125 rtems_task scrubbing_task( rtems_task_argument unused );
126 rtems_task calibration_sweep_task( rtems_task_argument unused );
126 rtems_task calibration_sweep_task( rtems_task_argument unused );
127
127
128 void init_housekeeping_parameters( void );
128 void init_housekeeping_parameters( void );
129 void increment_seq_counter(unsigned short *packetSequenceControl);
129 void increment_seq_counter(unsigned short *packetSequenceControl);
130 void getTime( unsigned char *time);
130 void getTime( unsigned char *time);
131 unsigned long long int getTimeAsUnsignedLongLongInt( );
131 unsigned long long int getTimeAsUnsignedLongLongInt( );
132 void send_dumb_hk( void );
133 void get_temperatures( unsigned char *temperatures );
132 void get_temperatures( unsigned char *temperatures );
134 void get_v_e1_e2_f3( unsigned char *spacecraft_potential );
133 void get_v_e1_e2_f3( unsigned char *spacecraft_potential );
135 void get_cpu_load( unsigned char *resource_statistics );
134 void get_cpu_load( unsigned char *resource_statistics );
136 void set_hk_lfr_sc_potential_flag( bool state );
135 void set_hk_lfr_sc_potential_flag( bool state );
137 void set_sy_lfr_pas_filter_enabled( bool state );
136 void set_sy_lfr_pas_filter_enabled( bool state );
138 void set_sy_lfr_watchdog_enabled( bool state );
137 void set_sy_lfr_watchdog_enabled( bool state );
139 void set_hk_lfr_calib_enable( bool state );
138 void set_hk_lfr_calib_enable( bool state );
140 void set_hk_lfr_reset_cause( enum lfr_reset_cause_t lfr_reset_cause );
139 void set_hk_lfr_reset_cause( enum lfr_reset_cause_t lfr_reset_cause );
141 void hk_lfr_le_me_he_update();
140 void hk_lfr_le_me_he_update();
142 void set_hk_lfr_time_not_synchro();
141 void set_hk_lfr_time_not_synchro();
143
142
144 extern int sched_yield( void );
143 extern int sched_yield( void );
145 extern void rtems_cpu_usage_reset();
144 extern void rtems_cpu_usage_reset();
146 extern ring_node *current_ring_node_f3;
145 extern ring_node *current_ring_node_f3;
147 extern ring_node *ring_node_to_send_cwf_f3;
146 extern ring_node *ring_node_to_send_cwf_f3;
148 extern ring_node waveform_ring_f3[];
147 extern ring_node waveform_ring_f3[];
149 extern unsigned short sequenceCounterHK;
148 extern unsigned short sequenceCounterHK;
150
149
151 extern unsigned char hk_lfr_q_sd_fifo_size_max;
150 extern unsigned char hk_lfr_q_sd_fifo_size_max;
152 extern unsigned char hk_lfr_q_rv_fifo_size_max;
151 extern unsigned char hk_lfr_q_rv_fifo_size_max;
153 extern unsigned char hk_lfr_q_p0_fifo_size_max;
152 extern unsigned char hk_lfr_q_p0_fifo_size_max;
154 extern unsigned char hk_lfr_q_p1_fifo_size_max;
153 extern unsigned char hk_lfr_q_p1_fifo_size_max;
155 extern unsigned char hk_lfr_q_p2_fifo_size_max;
154 extern unsigned char hk_lfr_q_p2_fifo_size_max;
156
155
157 #endif // FSW_MISC_H_INCLUDED
156 #endif // FSW_MISC_H_INCLUDED
@@ -1,44 +1,39
1 set(rtems_dir /opt/rtems-4.10/)
1 set(rtems_dir /opt/rtems-4.10/)
2
2
3 set(CMAKE_SYSTEM_NAME rtems)
3 set(CMAKE_SYSTEM_NAME rtems)
4 set(CMAKE_C_COMPILER ${rtems_dir}/bin/sparc-rtems-gcc)
4 set(CMAKE_C_COMPILER ${rtems_dir}/bin/sparc-rtems-gcc)
5 set(CMAKE_CXX_COMPILER ${rtems_dir}/bin/sparc-rtems-g++)
5 set(CMAKE_CXX_COMPILER ${rtems_dir}/bin/sparc-rtems-g++)
6 set(CMAKE_LINKER ${rtems_dir}/bin/sparc-rtems-g++)
6 set(CMAKE_LINKER ${rtems_dir}/bin/sparc-rtems-g++)
7 SET(CMAKE_EXE_LINKER_FLAGS "-static")
7 SET(CMAKE_EXE_LINKER_FLAGS "-static")
8 option(fix-b2bst "Activate -mfix-b2bst switch to mitigate \"LEON3FT Stale Cache Entry After Store with Data Tag Parity Error\" errata, GRLIB-TN-0009" ON)
8 option(fix-b2bst "Activate -mfix-b2bst switch to mitigate \"LEON3FT Stale Cache Entry After Store with Data Tag Parity Error\" errata, GRLIB-TN-0009" ON)
9
9
10 option(Coverage "Enables code coverage" OFF)
10 option(Coverage "Enables code coverage" OFF)
11
11
12
12
13 set(CMAKE_C_FLAGS_RELEASE "-O3")
13 set(CMAKE_C_FLAGS_RELEASE "-O3")
14 set(CMAKE_C_FLAGS_DEBUG "-O0")
14 set(CMAKE_C_FLAGS_DEBUG "-O0")
15
15
16
16
17 if(fix-b2bst)
17 if(fix-b2bst)
18 set(CMAKE_C_FLAGS_RELEASE "${CMAKE_C_FLAGS_RELEASE} -mfix-b2bst")
18 set(CMAKE_C_FLAGS_RELEASE "${CMAKE_C_FLAGS_RELEASE} -mfix-b2bst")
19 set(CMAKE_C_FLAGS_DEBUG "${CMAKE_C_FLAGS_DEBUG} -mfix-b2bst")
19 set(CMAKE_C_FLAGS_DEBUG "${CMAKE_C_FLAGS_DEBUG} -mfix-b2bst")
20 endif()
20 endif()
21
21
22 #if(Coverage)
23 # set(CMAKE_C_FLAGS_RELEASE "${CMAKE_C_FLAGS_RELEASE} -fprofile-arcs -ftest-coverage")
24 # set(CMAKE_C_FLAGS_DEBUG "${CMAKE_C_FLAGS_DEBUG} -fprofile-arcs -ftest-coverage")
25 #endif()
26
27
22
28 set(CMAKE_C_LINK_EXECUTABLE "<CMAKE_LINKER> <FLAGS> -Xlinker -Map=<TARGET>.map <CMAKE_CXX_LINK_FLAGS> <LINK_FLAGS> <OBJECTS> -o <TARGET> <LINK_LIBRARIES>")
23 set(CMAKE_C_LINK_EXECUTABLE "<CMAKE_LINKER> <FLAGS> -Xlinker -Map=<TARGET>.map <CMAKE_CXX_LINK_FLAGS> <LINK_FLAGS> <OBJECTS> -o <TARGET> <LINK_LIBRARIES>")
29
24
30 include_directories("${rtems_dir}/sparc-rtems/leon3/lib/include")
25 include_directories("${rtems_dir}/sparc-rtems/leon3/lib/include")
31
26
32 function (check_b2bst target bin)
27 function (check_b2bst target bin)
33 add_custom_command(TARGET ${target}
28 add_custom_command(TARGET ${target}
34 POST_BUILD
29 POST_BUILD
35 COMMAND ${rtems_dir}/bin/sparc-rtems-objdump -d ${bin}/${target} | ${CMAKE_SOURCE_DIR}/sparc/leon3ft-b2bst-scan.tcl
30 COMMAND ${rtems_dir}/bin/sparc-rtems-objdump -d ${bin}/${target} | ${CMAKE_SOURCE_DIR}/sparc/leon3ft-b2bst-scan.tcl
36 )
31 )
37 endfunction()
32 endfunction()
38
33
39 function (build_srec target bin rev)
34 function (build_srec target bin rev)
40 add_custom_command(TARGET ${target}
35 add_custom_command(TARGET ${target}
41 POST_BUILD
36 POST_BUILD
42 COMMAND ${rtems_dir}/bin/sparc-rtems-objcopy -j .data -F srec ${bin}/${target} RpwLfrApp_XXXX_data_rev-${rev}.srec && ${rtems_dir}/bin/sparc-rtems-objcopy -j .text -F srec ${bin}/${target} RpwLfrApp_XXXX_text_rev-${rev}.srec
37 COMMAND ${rtems_dir}/bin/sparc-rtems-objcopy -j .data -F srec ${bin}/${target} RpwLfrApp_XXXX_data_rev-${rev}.srec && ${rtems_dir}/bin/sparc-rtems-objcopy -j .text -F srec ${bin}/${target} RpwLfrApp_XXXX_text_rev-${rev}.srec
43 )
38 )
44 endfunction()
39 endfunction()
@@ -1,125 +1,130
1 cmake_minimum_required (VERSION 2.6)
1 cmake_minimum_required (VERSION 2.6)
2 project (fsw)
2 project (fsw)
3
3
4 include(sparc-rtems)
4 include(sparc-rtems)
5 include(cppcheck)
5 include(cppcheck)
6
6
7 include_directories("../header"
7 include_directories("../header"
8 "../header/lfr_common_headers"
8 "../header/lfr_common_headers"
9 "../header/processing"
9 "../header/processing"
10 "../LFR_basic-parameters"
10 "../LFR_basic-parameters"
11 "../src")
11 "../src")
12
12
13 set(SOURCES wf_handler.c
13 set(SOURCES wf_handler.c
14 tc_handler.c
14 tc_handler.c
15 fsw_misc.c
15 fsw_misc.c
16 fsw_init.c
16 fsw_init.c
17 fsw_globals.c
17 fsw_globals.c
18 fsw_spacewire.c
18 fsw_spacewire.c
19 tc_load_dump_parameters.c
19 tc_load_dump_parameters.c
20 tm_lfr_tc_exe.c
20 tm_lfr_tc_exe.c
21 tc_acceptance.c
21 tc_acceptance.c
22 processing/fsw_processing.c
22 processing/fsw_processing.c
23 processing/avf0_prc0.c
23 processing/avf0_prc0.c
24 processing/avf1_prc1.c
24 processing/avf1_prc1.c
25 processing/avf2_prc2.c
25 processing/avf2_prc2.c
26 lfr_cpu_usage_report.c
26 lfr_cpu_usage_report.c
27 ${LFR_BP_SRC}
27 ${LFR_BP_SRC}
28 ../header/wf_handler.h
28 ../header/wf_handler.h
29 ../header/tc_handler.h
29 ../header/tc_handler.h
30 ../header/grlib_regs.h
30 ../header/grlib_regs.h
31 ../header/fsw_misc.h
31 ../header/fsw_misc.h
32 ../header/fsw_init.h
32 ../header/fsw_init.h
33 ../header/fsw_spacewire.h
33 ../header/fsw_spacewire.h
34 ../header/tc_load_dump_parameters.h
34 ../header/tc_load_dump_parameters.h
35 ../header/tm_lfr_tc_exe.h
35 ../header/tm_lfr_tc_exe.h
36 ../header/tc_acceptance.h
36 ../header/tc_acceptance.h
37 ../header/processing/fsw_processing.h
37 ../header/processing/fsw_processing.h
38 ../header/processing/avf0_prc0.h
38 ../header/processing/avf0_prc0.h
39 ../header/processing/avf1_prc1.h
39 ../header/processing/avf1_prc1.h
40 ../header/processing/avf2_prc2.h
40 ../header/processing/avf2_prc2.h
41 ../header/fsw_params_wf_handler.h
41 ../header/fsw_params_wf_handler.h
42 ../header/lfr_cpu_usage_report.h
42 ../header/lfr_cpu_usage_report.h
43 ../header/lfr_common_headers/ccsds_types.h
43 ../header/lfr_common_headers/ccsds_types.h
44 ../header/lfr_common_headers/fsw_params.h
44 ../header/lfr_common_headers/fsw_params.h
45 ../header/lfr_common_headers/fsw_params_nb_bytes.h
45 ../header/lfr_common_headers/fsw_params_nb_bytes.h
46 ../header/lfr_common_headers/fsw_params_processing.h
46 ../header/lfr_common_headers/fsw_params_processing.h
47 ../header/lfr_common_headers/tm_byte_positions.h
47 ../header/lfr_common_headers/tm_byte_positions.h
48 ../LFR_basic-parameters/basic_parameters.h
48 ../LFR_basic-parameters/basic_parameters.h
49 ../LFR_basic-parameters/basic_parameters_params.h
49 ../LFR_basic-parameters/basic_parameters_params.h
50 ../header/GscMemoryLPP.hpp
50 ../header/GscMemoryLPP.hpp
51 )
51 )
52
52
53
53
54 option(FSW_verbose "Enable verbose LFR" OFF)
54 option(FSW_verbose "Enable verbose LFR" OFF)
55 option(FSW_boot_messages "Enable LFR boot messages" OFF)
55 option(FSW_boot_messages "Enable LFR boot messages" OFF)
56 option(FSW_debug_messages "Enable LFR debug messages" OFF)
56 option(FSW_debug_messages "Enable LFR debug messages" OFF)
57 option(FSW_cpu_usage_report "Enable LFR cpu usage report" OFF)
57 option(FSW_cpu_usage_report "Enable LFR cpu usage report" OFF)
58 option(FSW_stack_report "Enable LFR stack report" OFF)
58 option(FSW_stack_report "Enable LFR stack report" OFF)
59 option(FSW_vhdl_dev "?" OFF)
59 option(FSW_vhdl_dev "?" OFF)
60 option(FSW_lpp_dpu_destid "Set to debug at LPP" OFF)
60 option(FSW_lpp_dpu_destid "Set to debug at LPP" OFF)
61 option(FSW_debug_watchdog "Enable debug watchdog" OFF)
61 option(FSW_debug_watchdog "Enable debug watchdog" OFF)
62 option(FSW_debug_tch "?" OFF)
62 option(FSW_debug_tch "?" OFF)
63 option(FSW_Instrument_Scrubbing "Enable scrubbing counter" OFF)
63
64
64 set(SW_VERSION_N1 "3" CACHE STRING "Choose N1 FSW Version." FORCE)
65 set(SW_VERSION_N1 "3" CACHE STRING "Choose N1 FSW Version." FORCE)
65 set(SW_VERSION_N2 "2" CACHE STRING "Choose N2 FSW Version." FORCE)
66 set(SW_VERSION_N2 "2" CACHE STRING "Choose N2 FSW Version." FORCE)
66 set(SW_VERSION_N3 "0" CACHE STRING "Choose N3 FSW Version." FORCE)
67 set(SW_VERSION_N3 "0" CACHE STRING "Choose N3 FSW Version." FORCE)
67 set(SW_VERSION_N4 "20" CACHE STRING "Choose N4 FSW Version." FORCE)
68 set(SW_VERSION_N4 "20" CACHE STRING "Choose N4 FSW Version." FORCE)
68
69
69 if(FSW_verbose)
70 if(FSW_verbose)
70 add_definitions(-DPRINT_MESSAGES_ON_CONSOLE)
71 add_definitions(-DPRINT_MESSAGES_ON_CONSOLE)
71 endif()
72 endif()
72 if(FSW_boot_messages)
73 if(FSW_boot_messages)
73 add_definitions(-DBOOT_MESSAGES)
74 add_definitions(-DBOOT_MESSAGES)
74 endif()
75 endif()
75 if(FSW_debug_messages)
76 if(FSW_debug_messages)
76 add_definitions(-DDEBUG_MESSAGES)
77 add_definitions(-DDEBUG_MESSAGES)
77 endif()
78 endif()
78 if(FSW_cpu_usage_report)
79 if(FSW_cpu_usage_report)
79 add_definitions(-DPRINT_TASK_STATISTICS)
80 add_definitions(-DPRINT_TASK_STATISTICS)
80 endif()
81 endif()
81 if(FSW_stack_report)
82 if(FSW_stack_report)
82 add_definitions(-DPRINT_STACK_REPORT)
83 add_definitions(-DPRINT_STACK_REPORT)
83 endif()
84 endif()
84 if(FSW_vhdl_dev)
85 if(FSW_vhdl_dev)
85 add_definitions(-DVHDL_DEV)
86 add_definitions(-DVHDL_DEV)
86 endif()
87 endif()
87 if(FSW_lpp_dpu_destid)
88 if(FSW_lpp_dpu_destid)
88 add_definitions(-DLPP_DPU_DESTID)
89 add_definitions(-DLPP_DPU_DESTID)
89 endif()
90 endif()
90 if(FSW_debug_watchdog)
91 if(FSW_debug_watchdog)
91 add_definitions(-DDEBUG_WATCHDOG)
92 add_definitions(-DDEBUG_WATCHDOG)
92 endif()
93 endif()
93 if(FSW_debug_tch)
94 if(FSW_debug_tch)
94 add_definitions(-DDEBUG_TCH)
95 add_definitions(-DDEBUG_TCH)
95 endif()
96 endif()
96
97
97
98
98
99
99 add_definitions(-DMSB_FIRST_TCH)
100 add_definitions(-DMSB_FIRST_TCH)
100
101
101 add_definitions(-DSWVERSION=-1-0)
102 add_definitions(-DSWVERSION=-1-0)
102 add_definitions(-DSW_VERSION_N1=${SW_VERSION_N1})
103 add_definitions(-DSW_VERSION_N1=${SW_VERSION_N1})
103 add_definitions(-DSW_VERSION_N2=${SW_VERSION_N2})
104 add_definitions(-DSW_VERSION_N2=${SW_VERSION_N2})
104 add_definitions(-DSW_VERSION_N3=${SW_VERSION_N3})
105 add_definitions(-DSW_VERSION_N3=${SW_VERSION_N3})
105 add_definitions(-DSW_VERSION_N4=${SW_VERSION_N4})
106 add_definitions(-DSW_VERSION_N4=${SW_VERSION_N4})
106
107
107 add_executable(fsw ${SOURCES})
108 add_executable(fsw ${SOURCES})
108
109
110 if(FSW_Instrument_Scrubbing)
111 add_definitions(-DENABLE_SCRUBBING_COUNTER)
112 endif()
113
109 if(Coverage)
114 if(Coverage)
110 target_link_libraries(fsw gcov)
115 target_link_libraries(fsw gcov)
111 SET_TARGET_PROPERTIES(fsw PROPERTIES COMPILE_FLAGS "-fprofile-arcs -ftest-coverage")
116 SET_TARGET_PROPERTIES(fsw PROPERTIES COMPILE_FLAGS "-fprofile-arcs -ftest-coverage")
112 endif()
117 endif()
113
118
114
119
115 if(fix-b2bst)
120 if(fix-b2bst)
116 check_b2bst(fsw ${CMAKE_CURRENT_BINARY_DIR})
121 check_b2bst(fsw ${CMAKE_CURRENT_BINARY_DIR})
117 endif()
122 endif()
118
123
119 if(NOT FSW_lpp_dpu_destid)
124 if(NOT FSW_lpp_dpu_destid)
120 build_srec(fsw ${CMAKE_CURRENT_BINARY_DIR} "${SW_VERSION_N1}-${SW_VERSION_N2}-${SW_VERSION_N3}-${SW_VERSION_N4}")
125 build_srec(fsw ${CMAKE_CURRENT_BINARY_DIR} "${SW_VERSION_N1}-${SW_VERSION_N2}-${SW_VERSION_N3}-${SW_VERSION_N4}")
121 endif()
126 endif()
122
127
123
128
124 add_test_cppcheck(fsw STYLE UNUSED_FUNCTIONS POSSIBLE_ERROR MISSING_INCLUDE)
129 add_test_cppcheck(fsw STYLE UNUSED_FUNCTIONS POSSIBLE_ERROR MISSING_INCLUDE)
125
130
@@ -1,1103 +1,1054
1 /** General usage functions and RTEMS tasks.
1 /** General usage functions and RTEMS tasks.
2 *
2 *
3 * @file
3 * @file
4 * @author P. LEROY
4 * @author P. LEROY
5 *
5 *
6 */
6 */
7
7
8 #include "fsw_misc.h"
8 #include "fsw_misc.h"
9
9
10 int16_t hk_lfr_sc_v_f3_as_int16 = 0;
10 int16_t hk_lfr_sc_v_f3_as_int16 = 0;
11 int16_t hk_lfr_sc_e1_f3_as_int16 = 0;
11 int16_t hk_lfr_sc_e1_f3_as_int16 = 0;
12 int16_t hk_lfr_sc_e2_f3_as_int16 = 0;
12 int16_t hk_lfr_sc_e2_f3_as_int16 = 0;
13
13
14 void timer_configure(unsigned char timer, unsigned int clock_divider,
14 void timer_configure(unsigned char timer, unsigned int clock_divider,
15 unsigned char interrupt_level, rtems_isr (*timer_isr)() )
15 unsigned char interrupt_level, rtems_isr (*timer_isr)() )
16 {
16 {
17 /** This function configures a GPTIMER timer instantiated in the VHDL design.
17 /** This function configures a GPTIMER timer instantiated in the VHDL design.
18 *
18 *
19 * @param gptimer_regs points to the APB registers of the GPTIMER IP core.
19 * @param gptimer_regs points to the APB registers of the GPTIMER IP core.
20 * @param timer is the number of the timer in the IP core (several timers can be instantiated).
20 * @param timer is the number of the timer in the IP core (several timers can be instantiated).
21 * @param clock_divider is the divider of the 1 MHz clock that will be configured.
21 * @param clock_divider is the divider of the 1 MHz clock that will be configured.
22 * @param interrupt_level is the interrupt level that the timer drives.
22 * @param interrupt_level is the interrupt level that the timer drives.
23 * @param timer_isr is the interrupt subroutine that will be attached to the IRQ driven by the timer.
23 * @param timer_isr is the interrupt subroutine that will be attached to the IRQ driven by the timer.
24 *
24 *
25 * Interrupt levels are described in the SPARC documentation sparcv8.pdf p.76
25 * Interrupt levels are described in the SPARC documentation sparcv8.pdf p.76
26 *
26 *
27 */
27 */
28
28
29 rtems_status_code status;
29 rtems_status_code status;
30 rtems_isr_entry old_isr_handler;
30 rtems_isr_entry old_isr_handler;
31
31
32 old_isr_handler = NULL;
32 old_isr_handler = NULL;
33
33
34 gptimer_regs->timer[timer].ctrl = INIT_CHAR; // reset the control register
34 gptimer_regs->timer[timer].ctrl = INIT_CHAR; // reset the control register
35
35
36 status = rtems_interrupt_catch( timer_isr, interrupt_level, &old_isr_handler) ; // see sparcv8.pdf p.76 for interrupt levels
36 status = rtems_interrupt_catch( timer_isr, interrupt_level, &old_isr_handler) ; // see sparcv8.pdf p.76 for interrupt levels
37 if (status!=RTEMS_SUCCESSFUL)
37 if (status!=RTEMS_SUCCESSFUL)
38 {
38 {
39 PRINTF("in configure_timer *** ERR rtems_interrupt_catch\n")
39 PRINTF("in configure_timer *** ERR rtems_interrupt_catch\n")
40 }
40 }
41
41
42 timer_set_clock_divider( timer, clock_divider);
42 timer_set_clock_divider( timer, clock_divider);
43 }
43 }
44
44
45 void timer_start(unsigned char timer)
45 void timer_start(unsigned char timer)
46 {
46 {
47 /** This function starts a GPTIMER timer.
47 /** This function starts a GPTIMER timer.
48 *
48 *
49 * @param gptimer_regs points to the APB registers of the GPTIMER IP core.
49 * @param gptimer_regs points to the APB registers of the GPTIMER IP core.
50 * @param timer is the number of the timer in the IP core (several timers can be instantiated).
50 * @param timer is the number of the timer in the IP core (several timers can be instantiated).
51 *
51 *
52 */
52 */
53
53
54 gptimer_regs->timer[timer].ctrl = gptimer_regs->timer[timer].ctrl | GPTIMER_CLEAR_IRQ;
54 gptimer_regs->timer[timer].ctrl = gptimer_regs->timer[timer].ctrl | GPTIMER_CLEAR_IRQ;
55 gptimer_regs->timer[timer].ctrl = gptimer_regs->timer[timer].ctrl | GPTIMER_LD;
55 gptimer_regs->timer[timer].ctrl = gptimer_regs->timer[timer].ctrl | GPTIMER_LD;
56 gptimer_regs->timer[timer].ctrl = gptimer_regs->timer[timer].ctrl | GPTIMER_EN;
56 gptimer_regs->timer[timer].ctrl = gptimer_regs->timer[timer].ctrl | GPTIMER_EN;
57 gptimer_regs->timer[timer].ctrl = gptimer_regs->timer[timer].ctrl | GPTIMER_RS;
57 gptimer_regs->timer[timer].ctrl = gptimer_regs->timer[timer].ctrl | GPTIMER_RS;
58 gptimer_regs->timer[timer].ctrl = gptimer_regs->timer[timer].ctrl | GPTIMER_IE;
58 gptimer_regs->timer[timer].ctrl = gptimer_regs->timer[timer].ctrl | GPTIMER_IE;
59 }
59 }
60
60
61 void timer_stop(unsigned char timer)
61 void timer_stop(unsigned char timer)
62 {
62 {
63 /** This function stops a GPTIMER timer.
63 /** This function stops a GPTIMER timer.
64 *
64 *
65 * @param gptimer_regs points to the APB registers of the GPTIMER IP core.
65 * @param gptimer_regs points to the APB registers of the GPTIMER IP core.
66 * @param timer is the number of the timer in the IP core (several timers can be instantiated).
66 * @param timer is the number of the timer in the IP core (several timers can be instantiated).
67 *
67 *
68 */
68 */
69
69
70 gptimer_regs->timer[timer].ctrl = gptimer_regs->timer[timer].ctrl & GPTIMER_EN_MASK;
70 gptimer_regs->timer[timer].ctrl = gptimer_regs->timer[timer].ctrl & GPTIMER_EN_MASK;
71 gptimer_regs->timer[timer].ctrl = gptimer_regs->timer[timer].ctrl & GPTIMER_IE_MASK;
71 gptimer_regs->timer[timer].ctrl = gptimer_regs->timer[timer].ctrl & GPTIMER_IE_MASK;
72 gptimer_regs->timer[timer].ctrl = gptimer_regs->timer[timer].ctrl | GPTIMER_CLEAR_IRQ;
72 gptimer_regs->timer[timer].ctrl = gptimer_regs->timer[timer].ctrl | GPTIMER_CLEAR_IRQ;
73 }
73 }
74
74
75 void timer_set_clock_divider(unsigned char timer, unsigned int clock_divider)
75 void timer_set_clock_divider(unsigned char timer, unsigned int clock_divider)
76 {
76 {
77 /** This function sets the clock divider of a GPTIMER timer.
77 /** This function sets the clock divider of a GPTIMER timer.
78 *
78 *
79 * @param gptimer_regs points to the APB registers of the GPTIMER IP core.
79 * @param gptimer_regs points to the APB registers of the GPTIMER IP core.
80 * @param timer is the number of the timer in the IP core (several timers can be instantiated).
80 * @param timer is the number of the timer in the IP core (several timers can be instantiated).
81 * @param clock_divider is the divider of the 1 MHz clock that will be configured.
81 * @param clock_divider is the divider of the 1 MHz clock that will be configured.
82 *
82 *
83 */
83 */
84
84
85 gptimer_regs->timer[timer].reload = clock_divider; // base clock frequency is 1 MHz
85 gptimer_regs->timer[timer].reload = clock_divider; // base clock frequency is 1 MHz
86 }
86 }
87
87
88 // WATCHDOG
88 // WATCHDOG
89
89
90 rtems_isr watchdog_isr( rtems_vector_number vector )
90 rtems_isr watchdog_isr( rtems_vector_number vector )
91 {
91 {
92 rtems_status_code status_code;
92 rtems_status_code status_code;
93
93
94 status_code = rtems_event_send( Task_id[TASKID_DUMB], RTEMS_EVENT_12 );
94 status_code = rtems_event_send( Task_id[TASKID_DUMB], RTEMS_EVENT_12 );
95
95
96 PRINTF("watchdog_isr *** this is the end, exit(0)\n");
96 PRINTF("watchdog_isr *** this is the end, exit(0)\n");
97
97
98 exit(0);
98 exit(0);
99 }
99 }
100
100
101 void watchdog_configure(void)
101 void watchdog_configure(void)
102 {
102 {
103 /** This function configure the watchdog.
103 /** This function configure the watchdog.
104 *
104 *
105 * @param gptimer_regs points to the APB registers of the GPTIMER IP core.
105 * @param gptimer_regs points to the APB registers of the GPTIMER IP core.
106 * @param timer is the number of the timer in the IP core (several timers can be instantiated).
106 * @param timer is the number of the timer in the IP core (several timers can be instantiated).
107 *
107 *
108 * The watchdog is a timer provided by the GPTIMER IP core of the GRLIB.
108 * The watchdog is a timer provided by the GPTIMER IP core of the GRLIB.
109 *
109 *
110 */
110 */
111
111
112 LEON_Mask_interrupt( IRQ_GPTIMER_WATCHDOG ); // mask gptimer/watchdog interrupt during configuration
112 LEON_Mask_interrupt( IRQ_GPTIMER_WATCHDOG ); // mask gptimer/watchdog interrupt during configuration
113
113
114 timer_configure( TIMER_WATCHDOG, CLKDIV_WATCHDOG, IRQ_SPARC_GPTIMER_WATCHDOG, watchdog_isr );
114 timer_configure( TIMER_WATCHDOG, CLKDIV_WATCHDOG, IRQ_SPARC_GPTIMER_WATCHDOG, watchdog_isr );
115
115
116 LEON_Clear_interrupt( IRQ_GPTIMER_WATCHDOG ); // clear gptimer/watchdog interrupt
116 LEON_Clear_interrupt( IRQ_GPTIMER_WATCHDOG ); // clear gptimer/watchdog interrupt
117 }
117 }
118
118
119 void watchdog_stop(void)
119 void watchdog_stop(void)
120 {
120 {
121 LEON_Mask_interrupt( IRQ_GPTIMER_WATCHDOG ); // mask gptimer/watchdog interrupt line
121 LEON_Mask_interrupt( IRQ_GPTIMER_WATCHDOG ); // mask gptimer/watchdog interrupt line
122 timer_stop( TIMER_WATCHDOG );
122 timer_stop( TIMER_WATCHDOG );
123 LEON_Clear_interrupt( IRQ_GPTIMER_WATCHDOG ); // clear gptimer/watchdog interrupt
123 LEON_Clear_interrupt( IRQ_GPTIMER_WATCHDOG ); // clear gptimer/watchdog interrupt
124 }
124 }
125
125
126 void watchdog_reload(void)
126 void watchdog_reload(void)
127 {
127 {
128 /** This function reloads the watchdog timer counter with the timer reload value.
128 /** This function reloads the watchdog timer counter with the timer reload value.
129 *
129 *
130 * @param void
130 * @param void
131 *
131 *
132 * @return void
132 * @return void
133 *
133 *
134 */
134 */
135
135
136 gptimer_regs->timer[TIMER_WATCHDOG].ctrl = gptimer_regs->timer[TIMER_WATCHDOG].ctrl | GPTIMER_LD;
136 gptimer_regs->timer[TIMER_WATCHDOG].ctrl = gptimer_regs->timer[TIMER_WATCHDOG].ctrl | GPTIMER_LD;
137 }
137 }
138
138
139 void watchdog_start(void)
139 void watchdog_start(void)
140 {
140 {
141 /** This function starts the watchdog timer.
141 /** This function starts the watchdog timer.
142 *
142 *
143 * @param gptimer_regs points to the APB registers of the GPTIMER IP core.
143 * @param gptimer_regs points to the APB registers of the GPTIMER IP core.
144 * @param timer is the number of the timer in the IP core (several timers can be instantiated).
144 * @param timer is the number of the timer in the IP core (several timers can be instantiated).
145 *
145 *
146 */
146 */
147
147
148 LEON_Clear_interrupt( IRQ_GPTIMER_WATCHDOG );
148 LEON_Clear_interrupt( IRQ_GPTIMER_WATCHDOG );
149
149
150 gptimer_regs->timer[TIMER_WATCHDOG].ctrl = gptimer_regs->timer[TIMER_WATCHDOG].ctrl | GPTIMER_CLEAR_IRQ;
150 gptimer_regs->timer[TIMER_WATCHDOG].ctrl = gptimer_regs->timer[TIMER_WATCHDOG].ctrl | GPTIMER_CLEAR_IRQ;
151 gptimer_regs->timer[TIMER_WATCHDOG].ctrl = gptimer_regs->timer[TIMER_WATCHDOG].ctrl | GPTIMER_LD;
151 gptimer_regs->timer[TIMER_WATCHDOG].ctrl = gptimer_regs->timer[TIMER_WATCHDOG].ctrl | GPTIMER_LD;
152 gptimer_regs->timer[TIMER_WATCHDOG].ctrl = gptimer_regs->timer[TIMER_WATCHDOG].ctrl | GPTIMER_EN;
152 gptimer_regs->timer[TIMER_WATCHDOG].ctrl = gptimer_regs->timer[TIMER_WATCHDOG].ctrl | GPTIMER_EN;
153 gptimer_regs->timer[TIMER_WATCHDOG].ctrl = gptimer_regs->timer[TIMER_WATCHDOG].ctrl | GPTIMER_IE;
153 gptimer_regs->timer[TIMER_WATCHDOG].ctrl = gptimer_regs->timer[TIMER_WATCHDOG].ctrl | GPTIMER_IE;
154
154
155 LEON_Unmask_interrupt( IRQ_GPTIMER_WATCHDOG );
155 LEON_Unmask_interrupt( IRQ_GPTIMER_WATCHDOG );
156
156
157 }
157 }
158
158
159 int enable_apbuart_transmitter( void ) // set the bit 1, TE Transmitter Enable to 1 in the APBUART control register
159 int enable_apbuart_transmitter( void ) // set the bit 1, TE Transmitter Enable to 1 in the APBUART control register
160 {
160 {
161 struct apbuart_regs_str *apbuart_regs = (struct apbuart_regs_str *) REGS_ADDR_APBUART;
161 struct apbuart_regs_str *apbuart_regs = (struct apbuart_regs_str *) REGS_ADDR_APBUART;
162
162
163 apbuart_regs->ctrl = APBUART_CTRL_REG_MASK_TE;
163 apbuart_regs->ctrl = APBUART_CTRL_REG_MASK_TE;
164
164
165 return 0;
165 return 0;
166 }
166 }
167
167
168 void set_apbuart_scaler_reload_register(unsigned int regs, unsigned int value)
168 void set_apbuart_scaler_reload_register(unsigned int regs, unsigned int value)
169 {
169 {
170 /** This function sets the scaler reload register of the apbuart module
170 /** This function sets the scaler reload register of the apbuart module
171 *
171 *
172 * @param regs is the address of the apbuart registers in memory
172 * @param regs is the address of the apbuart registers in memory
173 * @param value is the value that will be stored in the scaler register
173 * @param value is the value that will be stored in the scaler register
174 *
174 *
175 * The value shall be set by the software to get data on the serial interface.
175 * The value shall be set by the software to get data on the serial interface.
176 *
176 *
177 */
177 */
178
178
179 struct apbuart_regs_str *apbuart_regs = (struct apbuart_regs_str *) regs;
179 struct apbuart_regs_str *apbuart_regs = (struct apbuart_regs_str *) regs;
180
180
181 apbuart_regs->scaler = value;
181 apbuart_regs->scaler = value;
182
182
183 BOOT_PRINTF1("OK *** apbuart port scaler reload register set to 0x%x\n", value)
183 BOOT_PRINTF1("OK *** apbuart port scaler reload register set to 0x%x\n", value)
184 }
184 }
185
185
186 //************
186 //************
187 // RTEMS TASKS
187 // RTEMS TASKS
188
188
189 rtems_task load_task(rtems_task_argument argument)
189 rtems_task load_task(rtems_task_argument argument)
190 {
190 {
191 BOOT_PRINTF("in LOAD *** \n")
191 BOOT_PRINTF("in LOAD *** \n")
192
192
193 rtems_status_code status;
193 rtems_status_code status;
194 unsigned int i;
194 unsigned int i;
195 unsigned int j;
195 unsigned int j;
196 rtems_name name_watchdog_rate_monotonic; // name of the watchdog rate monotonic
196 rtems_name name_watchdog_rate_monotonic; // name of the watchdog rate monotonic
197 rtems_id watchdog_period_id; // id of the watchdog rate monotonic period
197 rtems_id watchdog_period_id; // id of the watchdog rate monotonic period
198
198
199 watchdog_period_id = RTEMS_ID_NONE;
199 watchdog_period_id = RTEMS_ID_NONE;
200
200
201 name_watchdog_rate_monotonic = rtems_build_name( 'L', 'O', 'A', 'D' );
201 name_watchdog_rate_monotonic = rtems_build_name( 'L', 'O', 'A', 'D' );
202
202
203 status = rtems_rate_monotonic_create( name_watchdog_rate_monotonic, &watchdog_period_id );
203 status = rtems_rate_monotonic_create( name_watchdog_rate_monotonic, &watchdog_period_id );
204 if( status != RTEMS_SUCCESSFUL ) {
204 if( status != RTEMS_SUCCESSFUL ) {
205 PRINTF1( "in LOAD *** rtems_rate_monotonic_create failed with status of %d\n", status )
205 PRINTF1( "in LOAD *** rtems_rate_monotonic_create failed with status of %d\n", status )
206 }
206 }
207
207
208 i = 0;
208 i = 0;
209 j = 0;
209 j = 0;
210
210
211 watchdog_configure();
211 watchdog_configure();
212
212
213 watchdog_start();
213 watchdog_start();
214
214
215 set_sy_lfr_watchdog_enabled( true );
215 set_sy_lfr_watchdog_enabled( true );
216
216
217 while(1){
217 while(1){
218 status = rtems_rate_monotonic_period( watchdog_period_id, WATCHDOG_PERIOD );
218 status = rtems_rate_monotonic_period( watchdog_period_id, WATCHDOG_PERIOD );
219 watchdog_reload();
219 watchdog_reload();
220 i = i + 1;
220 i = i + 1;
221 if ( i == WATCHDOG_LOOP_PRINTF )
221 if ( i == WATCHDOG_LOOP_PRINTF )
222 {
222 {
223 i = 0;
223 i = 0;
224 j = j + 1;
224 j = j + 1;
225 PRINTF1("%d\n", j)
225 PRINTF1("%d\n", j)
226 }
226 }
227 #ifdef DEBUG_WATCHDOG
227 #ifdef DEBUG_WATCHDOG
228 if (j == WATCHDOG_LOOP_DEBUG )
228 if (j == WATCHDOG_LOOP_DEBUG )
229 {
229 {
230 status = rtems_task_delete(RTEMS_SELF);
230 status = rtems_task_delete(RTEMS_SELF);
231 }
231 }
232 #endif
232 #endif
233 }
233 }
234 }
234 }
235
235
236 rtems_task hous_task(rtems_task_argument argument)
236 rtems_task hous_task(rtems_task_argument argument)
237 {
237 {
238 rtems_status_code status;
238 rtems_status_code status;
239 rtems_status_code spare_status;
239 rtems_status_code spare_status;
240 rtems_id queue_id;
240 rtems_id queue_id;
241 rtems_rate_monotonic_period_status period_status;
241 rtems_rate_monotonic_period_status period_status;
242 bool isSynchronized;
242 bool isSynchronized;
243
243
244 queue_id = RTEMS_ID_NONE;
244 queue_id = RTEMS_ID_NONE;
245 memset(&period_status, 0, sizeof(rtems_rate_monotonic_period_status));
245 memset(&period_status, 0, sizeof(rtems_rate_monotonic_period_status));
246 isSynchronized = false;
246 isSynchronized = false;
247
247
248 status = get_message_queue_id_send( &queue_id );
248 status = get_message_queue_id_send( &queue_id );
249 if (status != RTEMS_SUCCESSFUL)
249 if (status != RTEMS_SUCCESSFUL)
250 {
250 {
251 PRINTF1("in HOUS *** ERR get_message_queue_id_send %d\n", status)
251 PRINTF1("in HOUS *** ERR get_message_queue_id_send %d\n", status)
252 }
252 }
253
253
254 BOOT_PRINTF("in HOUS ***\n");
254 BOOT_PRINTF("in HOUS ***\n");
255
255
256 if (rtems_rate_monotonic_ident( name_hk_rate_monotonic, &HK_id) != RTEMS_SUCCESSFUL) {
256 if (rtems_rate_monotonic_ident( name_hk_rate_monotonic, &HK_id) != RTEMS_SUCCESSFUL) {
257 status = rtems_rate_monotonic_create( name_hk_rate_monotonic, &HK_id );
257 status = rtems_rate_monotonic_create( name_hk_rate_monotonic, &HK_id );
258 if( status != RTEMS_SUCCESSFUL ) {
258 if( status != RTEMS_SUCCESSFUL ) {
259 PRINTF1( "rtems_rate_monotonic_create failed with status of %d\n", status );
259 PRINTF1( "rtems_rate_monotonic_create failed with status of %d\n", status );
260 }
260 }
261 }
261 }
262
262
263 status = rtems_rate_monotonic_cancel(HK_id);
263 status = rtems_rate_monotonic_cancel(HK_id);
264 if( status != RTEMS_SUCCESSFUL ) {
264 if( status != RTEMS_SUCCESSFUL ) {
265 PRINTF1( "ERR *** in HOUS *** rtems_rate_monotonic_cancel(HK_id) ***code: %d\n", status );
265 PRINTF1( "ERR *** in HOUS *** rtems_rate_monotonic_cancel(HK_id) ***code: %d\n", status );
266 }
266 }
267 else {
267 else {
268 DEBUG_PRINTF("OK *** in HOUS *** rtems_rate_monotonic_cancel(HK_id)\n");
268 DEBUG_PRINTF("OK *** in HOUS *** rtems_rate_monotonic_cancel(HK_id)\n");
269 }
269 }
270
270
271 // startup phase
271 // startup phase
272 status = rtems_rate_monotonic_period( HK_id, SY_LFR_TIME_SYN_TIMEOUT_in_ticks );
272 status = rtems_rate_monotonic_period( HK_id, SY_LFR_TIME_SYN_TIMEOUT_in_ticks );
273 status = rtems_rate_monotonic_get_status( HK_id, &period_status );
273 status = rtems_rate_monotonic_get_status( HK_id, &period_status );
274 DEBUG_PRINTF1("startup HK, HK_id status = %d\n", period_status.state)
274 DEBUG_PRINTF1("startup HK, HK_id status = %d\n", period_status.state)
275 while( (period_status.state != RATE_MONOTONIC_EXPIRED)
275 while( (period_status.state != RATE_MONOTONIC_EXPIRED)
276 && (isSynchronized == false) ) // after SY_LFR_TIME_SYN_TIMEOUT ms, starts HK anyway
276 && (isSynchronized == false) ) // after SY_LFR_TIME_SYN_TIMEOUT ms, starts HK anyway
277 {
277 {
278 if ((time_management_regs->coarse_time & VAL_LFR_SYNCHRONIZED) == INT32_ALL_0) // check time synchronization
278 if ((time_management_regs->coarse_time & VAL_LFR_SYNCHRONIZED) == INT32_ALL_0) // check time synchronization
279 {
279 {
280 isSynchronized = true;
280 isSynchronized = true;
281 }
281 }
282 else
282 else
283 {
283 {
284 status = rtems_rate_monotonic_get_status( HK_id, &period_status );
284 status = rtems_rate_monotonic_get_status( HK_id, &period_status );
285
285
286 status = rtems_task_wake_after( HK_SYNC_WAIT ); // wait HK_SYNCH_WAIT 100 ms = 10 * 10 ms
286 status = rtems_task_wake_after( HK_SYNC_WAIT ); // wait HK_SYNCH_WAIT 100 ms = 10 * 10 ms
287 }
287 }
288 }
288 }
289 status = rtems_rate_monotonic_cancel(HK_id);
289 status = rtems_rate_monotonic_cancel(HK_id);
290 DEBUG_PRINTF1("startup HK, HK_id status = %d\n", period_status.state)
290 DEBUG_PRINTF1("startup HK, HK_id status = %d\n", period_status.state)
291
291
292 set_hk_lfr_reset_cause( POWER_ON );
292 set_hk_lfr_reset_cause( POWER_ON );
293
293
294 while(1){ // launch the rate monotonic task
294 while(1){ // launch the rate monotonic task
295 status = rtems_rate_monotonic_period( HK_id, HK_PERIOD );
295 status = rtems_rate_monotonic_period( HK_id, HK_PERIOD );
296 if ( status != RTEMS_SUCCESSFUL ) {
296 if ( status != RTEMS_SUCCESSFUL ) {
297