@@ -1,221 +1,222 | |||||
1 | #ifndef GSCMEMORY_HPP_ |
|
1 | #ifndef GSCMEMORY_HPP_ | |
2 | #define GSCMEMORY_HPP_ |
|
2 | #define GSCMEMORY_HPP_ | |
3 |
|
3 | |||
4 | #ifndef LEON3 |
|
4 | #ifndef LEON3 | |
5 | #define LEON3 |
|
5 | #define LEON3 | |
6 | #endif |
|
6 | #endif | |
7 |
|
7 | |||
8 | #define REGS_ADDR_PLUGANDPLAY 0xFFFFF000 |
|
8 | #define REGS_ADDR_PLUGANDPLAY 0xFFFFF000 | |
9 | #define ASR16_REG_ADDRESS 0x90400040 // Ancillary State Register 16 = Register protection control register (FT only) |
|
9 | #define ASR16_REG_ADDRESS 0x90400040 // Ancillary State Register 16 = Register protection control register (FT only) | |
10 |
|
10 | |||
11 | #define DEVICEID_LEON3 0x003 |
|
11 | #define DEVICEID_LEON3 0x003 | |
12 | #define DEVICEID_LEON3FT 0x053 |
|
12 | #define DEVICEID_LEON3FT 0x053 | |
13 | #define VENDORID_GAISLER 0x01 |
|
13 | #define VENDORID_GAISLER 0x01 | |
14 |
|
14 | |||
15 | // CCR |
|
15 | // CCR | |
16 | #define POS_FT 19 |
|
16 | #define POS_FT 19 | |
17 | // |
|
17 | // | |
18 | #define POS_ITE 12 |
|
18 | #define POS_ITE 12 | |
19 | #define COUNTER_FIELD_ITE 0x00003000 // 0000 0000 0000 0000 0011 0000 0000 0000 |
|
19 | #define COUNTER_FIELD_ITE 0x00003000 // 0000 0000 0000 0000 0011 0000 0000 0000 | |
20 | #define COUNTER_MASK_ITE 0xffffcfff // 1111 1111 1111 1111 1100 1111 1111 1111 |
|
20 | #define COUNTER_MASK_ITE 0xffffcfff // 1111 1111 1111 1111 1100 1111 1111 1111 | |
21 | #define POS_IDE 10 |
|
21 | #define POS_IDE 10 | |
22 | #define COUNTER_FIELD_IDE 0x00000c00 // 0000 0000 0000 0000 0000 1100 0000 0000 |
|
22 | #define COUNTER_FIELD_IDE 0x00000c00 // 0000 0000 0000 0000 0000 1100 0000 0000 | |
23 | #define COUNTER_MASK_IDE 0xfffff3ff // 1111 1111 1111 1111 1111 0011 1111 1111 |
|
23 | #define COUNTER_MASK_IDE 0xfffff3ff // 1111 1111 1111 1111 1111 0011 1111 1111 | |
24 | // |
|
24 | // | |
25 | #define POS_DTE 8 |
|
25 | #define POS_DTE 8 | |
26 | #define COUNTER_FIELD_DTE 0x00000300 // 0000 0000 0000 0000 0000 0011 0000 0000 |
|
26 | #define COUNTER_FIELD_DTE 0x00000300 // 0000 0000 0000 0000 0000 0011 0000 0000 | |
27 | #define COUNTER_MASK_DTE 0xfffffcff // 1111 1111 1111 1111 1111 1100 1111 1111 |
|
27 | #define COUNTER_MASK_DTE 0xfffffcff // 1111 1111 1111 1111 1111 1100 1111 1111 | |
28 | #define POS_DDE 6 |
|
28 | #define POS_DDE 6 | |
29 | #define COUNTER_FIELD_DDE 0x000000c0 // 0000 0000 0000 0000 0000 0000 1100 0000 |
|
29 | #define COUNTER_FIELD_DDE 0x000000c0 // 0000 0000 0000 0000 0000 0000 1100 0000 | |
30 | #define COUNTER_MASK_DDE 0xffffff3f // 1111 1111 1111 1111 1111 1111 0011 1111 |
|
30 | #define COUNTER_MASK_DDE 0xffffff3f // 1111 1111 1111 1111 1111 1111 0011 1111 | |
31 |
|
31 | |||
32 | // ASR16 |
|
32 | // ASR16 | |
33 | #define POS_FPFTID 30 |
|
33 | #define POS_FPFTID 30 | |
34 | #define POS_FPRF 27 |
|
34 | #define POS_FPRF 27 | |
35 | #define POS_FDI 16 // FP RF protection enable/disable |
|
35 | #define POS_FDI 16 // FP RF protection enable/disable | |
36 | #define POS_IUFTID 14 |
|
36 | #define POS_IUFTID 14 | |
37 | #define POS_IURF 11 |
|
37 | #define POS_IURF 11 | |
38 | #define POS_IDI 0 // IU RF protection enable/disable |
|
38 | #define POS_IDI 0 // IU RF protection enable/disable | |
39 |
|
39 | |||
40 | #define COUNTER_FIELD_FPRF 0x38000000 // 0011 1000 0000 0000 0000 0000 0000 0000 |
|
40 | #define COUNTER_FIELD_FPRF 0x38000000 // 0011 1000 0000 0000 0000 0000 0000 0000 | |
41 | #define COUNTER_MASK_FPRF 0xc7ffffff // 1100 0111 1111 1111 1111 1111 1111 1111 |
|
41 | #define COUNTER_MASK_FPRF 0xc7ffffff // 1100 0111 1111 1111 1111 1111 1111 1111 | |
42 |
|
42 | |||
43 | #define COUNTER_FIELD_IURF 0x00003800 // 0000 0000 0000 0000 0011 1000 0000 0000 |
|
43 | #define COUNTER_FIELD_IURF 0x00003800 // 0000 0000 0000 0000 0011 1000 0000 0000 | |
44 | #define COUNTER_MASK_IURF 0xffffc7ff // 1111 1111 1111 1111 1100 0111 1111 1111 |
|
44 | #define COUNTER_MASK_IURF 0xffffc7ff // 1111 1111 1111 1111 1100 0111 1111 1111 | |
45 |
|
45 | |||
46 | volatile unsigned int *asr16Ptr = (volatile unsigned int *) ASR16_REG_ADDRESS; |
|
46 | volatile unsigned int *asr16Ptr = (volatile unsigned int *) ASR16_REG_ADDRESS; | |
47 |
|
47 | #ifdef ENABLE_DEAD_CODE | ||
48 | static inline void flushCache() |
|
48 | static inline void flushCache() | |
49 | { |
|
49 | { | |
50 | /** |
|
50 | /** | |
51 | * Flush the data cache and the instruction cache. |
|
51 | * Flush the data cache and the instruction cache. | |
52 | * |
|
52 | * | |
53 | * @param void |
|
53 | * @param void | |
54 | * |
|
54 | * | |
55 | * @return void |
|
55 | * @return void | |
56 | */ |
|
56 | */ | |
57 |
|
57 | |||
58 | asm("flush"); |
|
58 | asm("flush"); | |
59 | } |
|
59 | } | |
|
60 | #endif | |||
60 |
|
61 | |||
61 | //*************************** |
|
62 | //*************************** | |
62 | // CCR Cache control register |
|
63 | // CCR Cache control register | |
63 |
|
64 | |||
64 | static unsigned int CCR_getValue() |
|
65 | static unsigned int CCR_getValue() | |
65 | { |
|
66 | { | |
66 | unsigned int cacheControlRegister = 0; |
|
67 | unsigned int cacheControlRegister = 0; | |
67 | __asm__ __volatile__("lda [%%g0] 2, %0" : "=r"(cacheControlRegister) : ); |
|
68 | __asm__ __volatile__("lda [%%g0] 2, %0" : "=r"(cacheControlRegister) : ); | |
68 | return cacheControlRegister; |
|
69 | return cacheControlRegister; | |
69 | } |
|
70 | } | |
70 |
|
71 | |||
71 | static void CCR_setValue(unsigned int cacheControlRegister) |
|
72 | static void CCR_setValue(unsigned int cacheControlRegister) | |
72 | { |
|
73 | { | |
73 | __asm__ __volatile__("sta %0, [%%g0] 2" : : "r"(cacheControlRegister)); |
|
74 | __asm__ __volatile__("sta %0, [%%g0] 2" : : "r"(cacheControlRegister)); | |
74 | } |
|
75 | } | |
75 |
|
76 | |||
76 | static void CCR_resetCacheControlRegister() |
|
77 | static void CCR_resetCacheControlRegister() | |
77 | { |
|
78 | { | |
78 | unsigned int cacheControlRegister; |
|
79 | unsigned int cacheControlRegister; | |
79 | cacheControlRegister = 0x00; |
|
80 | cacheControlRegister = 0x00; | |
80 | CCR_setValue(cacheControlRegister); |
|
81 | CCR_setValue(cacheControlRegister); | |
81 | } |
|
82 | } | |
82 |
|
83 | |||
83 | static void CCR_enableInstructionCache() |
|
84 | static void CCR_enableInstructionCache() | |
84 | { |
|
85 | { | |
85 | // [1:0] Instruction Cache state (ICS) |
|
86 | // [1:0] Instruction Cache state (ICS) | |
86 | // Indicates the current data cache state according to the following: X0 = disabled, 01 = frozen, 11 = enabled. |
|
87 | // Indicates the current data cache state according to the following: X0 = disabled, 01 = frozen, 11 = enabled. | |
87 | unsigned int cacheControlRegister; |
|
88 | unsigned int cacheControlRegister; | |
88 | cacheControlRegister = CCR_getValue(); |
|
89 | cacheControlRegister = CCR_getValue(); | |
89 | cacheControlRegister = (cacheControlRegister | 0x3); |
|
90 | cacheControlRegister = (cacheControlRegister | 0x3); | |
90 | CCR_setValue(cacheControlRegister); |
|
91 | CCR_setValue(cacheControlRegister); | |
91 | } |
|
92 | } | |
92 |
|
93 | |||
93 | static void CCR_enableDataCache() |
|
94 | static void CCR_enableDataCache() | |
94 | { |
|
95 | { | |
95 | // [3:2] Data Cache state (DCS) |
|
96 | // [3:2] Data Cache state (DCS) | |
96 | // Indicates the current data cache state according to the following: X0 = disabled, 01 = frozen, 11 = enabled. |
|
97 | // Indicates the current data cache state according to the following: X0 = disabled, 01 = frozen, 11 = enabled. | |
97 | unsigned int cacheControlRegister; |
|
98 | unsigned int cacheControlRegister; | |
98 | cacheControlRegister = CCR_getValue(); |
|
99 | cacheControlRegister = CCR_getValue(); | |
99 | cacheControlRegister = (cacheControlRegister | 0xc); |
|
100 | cacheControlRegister = (cacheControlRegister | 0xc); | |
100 | CCR_setValue(cacheControlRegister); |
|
101 | CCR_setValue(cacheControlRegister); | |
101 | } |
|
102 | } | |
102 |
|
103 | |||
103 | static void CCR_enableInstructionBurstFetch() |
|
104 | static void CCR_enableInstructionBurstFetch() | |
104 | { |
|
105 | { | |
105 | // [16] Instruction burst fetch (IB). This bit enables burst fill during instruction fetch. |
|
106 | // [16] Instruction burst fetch (IB). This bit enables burst fill during instruction fetch. | |
106 | unsigned int cacheControlRegister; |
|
107 | unsigned int cacheControlRegister; | |
107 | cacheControlRegister = CCR_getValue(); |
|
108 | cacheControlRegister = CCR_getValue(); | |
108 | // set the bit IB to 1 |
|
109 | // set the bit IB to 1 | |
109 | cacheControlRegister = (cacheControlRegister | 0x10000); |
|
110 | cacheControlRegister = (cacheControlRegister | 0x10000); | |
110 | CCR_setValue(cacheControlRegister); |
|
111 | CCR_setValue(cacheControlRegister); | |
111 | } |
|
112 | } | |
112 |
|
113 | |||
113 | void CCR_getInstructionAndDataErrorCounters( unsigned int* instructionErrorCounter, unsigned int* dataErrorCounter ) |
|
114 | void CCR_getInstructionAndDataErrorCounters( unsigned int* instructionErrorCounter, unsigned int* dataErrorCounter ) | |
114 | { |
|
115 | { | |
115 | // [13:12] Instruction Tag Errors (ITE) - Number of detected parity errors in the instruction tag cache. |
|
116 | // [13:12] Instruction Tag Errors (ITE) - Number of detected parity errors in the instruction tag cache. | |
116 | // Only available if fault-tolerance is enabled (FT field in this register is non-zero). |
|
117 | // Only available if fault-tolerance is enabled (FT field in this register is non-zero). | |
117 | // [11:10] Instruction Data Errors (IDE) - Number of detected parity errors in the instruction data cache. |
|
118 | // [11:10] Instruction Data Errors (IDE) - Number of detected parity errors in the instruction data cache. | |
118 | // Only available if fault-tolerance is enabled (FT field in this register is non-zero). |
|
119 | // Only available if fault-tolerance is enabled (FT field in this register is non-zero). | |
119 |
|
120 | |||
120 | unsigned int cacheControlRegister; |
|
121 | unsigned int cacheControlRegister; | |
121 | unsigned int iTE; |
|
122 | unsigned int iTE; | |
122 | unsigned int iDE; |
|
123 | unsigned int iDE; | |
123 | unsigned int dTE; |
|
124 | unsigned int dTE; | |
124 | unsigned int dDE; |
|
125 | unsigned int dDE; | |
125 |
|
126 | |||
126 | cacheControlRegister = CCR_getValue(); |
|
127 | cacheControlRegister = CCR_getValue(); | |
127 | iTE = (cacheControlRegister & COUNTER_FIELD_ITE) >> POS_ITE; |
|
128 | iTE = (cacheControlRegister & COUNTER_FIELD_ITE) >> POS_ITE; | |
128 | iDE = (cacheControlRegister & COUNTER_FIELD_IDE) >> POS_IDE; |
|
129 | iDE = (cacheControlRegister & COUNTER_FIELD_IDE) >> POS_IDE; | |
129 | dTE = (cacheControlRegister & COUNTER_FIELD_DTE) >> POS_DTE; |
|
130 | dTE = (cacheControlRegister & COUNTER_FIELD_DTE) >> POS_DTE; | |
130 | dDE = (cacheControlRegister & COUNTER_FIELD_DDE) >> POS_DDE; |
|
131 | dDE = (cacheControlRegister & COUNTER_FIELD_DDE) >> POS_DDE; | |
131 |
|
132 | |||
132 | *instructionErrorCounter = iTE + iDE; |
|
133 | *instructionErrorCounter = iTE + iDE; | |
133 | *dataErrorCounter = dTE + dDE; |
|
134 | *dataErrorCounter = dTE + dDE; | |
134 |
|
135 | |||
135 | // reset counters |
|
136 | // reset counters | |
136 | cacheControlRegister = cacheControlRegister |
|
137 | cacheControlRegister = cacheControlRegister | |
137 | & COUNTER_FIELD_ITE |
|
138 | & COUNTER_FIELD_ITE | |
138 | & COUNTER_FIELD_IDE |
|
139 | & COUNTER_FIELD_IDE | |
139 | & COUNTER_FIELD_DTE |
|
140 | & COUNTER_FIELD_DTE | |
140 | & COUNTER_FIELD_DDE; |
|
141 | & COUNTER_FIELD_DDE; | |
141 |
|
142 | |||
142 | CCR_setValue(cacheControlRegister); |
|
143 | CCR_setValue(cacheControlRegister); | |
143 | } |
|
144 | } | |
144 |
|
145 | |||
145 | //******************************************* |
|
146 | //******************************************* | |
146 | // ASR16 Register protection control register |
|
147 | // ASR16 Register protection control register | |
147 |
|
148 | |||
148 | static void ASR16_resetRegisterProtectionControlRegister() |
|
149 | static void ASR16_resetRegisterProtectionControlRegister() | |
149 | { |
|
150 | { | |
150 | *asr16Ptr = 0x00; |
|
151 | *asr16Ptr = 0x00; | |
151 | } |
|
152 | } | |
152 |
|
153 | |||
153 | void ASR16_get_FPRF_IURF_ErrorCounters( unsigned int* fprfErrorCounter, unsigned int* iurfErrorCounter) |
|
154 | void ASR16_get_FPRF_IURF_ErrorCounters( unsigned int* fprfErrorCounter, unsigned int* iurfErrorCounter) | |
154 | { |
|
155 | { | |
155 | /** This function is used to retrieve the integer unit register file error counter and the floating point unit |
|
156 | /** This function is used to retrieve the integer unit register file error counter and the floating point unit | |
156 | * register file error counter |
|
157 | * register file error counter | |
157 | * |
|
158 | * | |
158 | * @return void |
|
159 | * @return void | |
159 | * |
|
160 | * | |
160 | * [29:27] FP RF error counter - Number of detected parity errors in the FP register file. |
|
161 | * [29:27] FP RF error counter - Number of detected parity errors in the FP register file. | |
161 | * [13:11] IU RF error counter - Number of detected parity errors in the IU register file. |
|
162 | * [13:11] IU RF error counter - Number of detected parity errors in the IU register file. | |
162 | * |
|
163 | * | |
163 | */ |
|
164 | */ | |
164 |
|
165 | |||
165 | unsigned int asr16; |
|
166 | unsigned int asr16; | |
166 |
|
167 | |||
167 | asr16 = *asr16Ptr; |
|
168 | asr16 = *asr16Ptr; | |
168 | *fprfErrorCounter = ( asr16 & COUNTER_FIELD_FPRF ) >> POS_FPRF; |
|
169 | *fprfErrorCounter = ( asr16 & COUNTER_FIELD_FPRF ) >> POS_FPRF; | |
169 | *iurfErrorCounter = ( asr16 & COUNTER_FIELD_IURF ) >> POS_IURF; |
|
170 | *iurfErrorCounter = ( asr16 & COUNTER_FIELD_IURF ) >> POS_IURF; | |
170 |
|
171 | |||
171 | // reset the counter to 0 |
|
172 | // reset the counter to 0 | |
172 | asr16 = asr16 |
|
173 | asr16 = asr16 | |
173 | & COUNTER_MASK_FPRF |
|
174 | & COUNTER_MASK_FPRF | |
174 | & COUNTER_FIELD_IURF; |
|
175 | & COUNTER_FIELD_IURF; | |
175 |
|
176 | |||
176 | *asr16Ptr = asr16; |
|
177 | *asr16Ptr = asr16; | |
177 | } |
|
178 | } | |
178 |
|
179 | |||
179 | static void faultTolerantScheme() |
|
180 | static void faultTolerantScheme() | |
180 | { |
|
181 | { | |
181 | // [20:19] FT scheme (FT) - β00β = no FT, β01β = 4-bit checking implemented |
|
182 | // [20:19] FT scheme (FT) - β00β = no FT, β01β = 4-bit checking implemented | |
182 | unsigned int cacheControlRegister; |
|
183 | unsigned int cacheControlRegister; | |
183 | unsigned int *plugAndPlayRegister; |
|
184 | unsigned int *plugAndPlayRegister; | |
184 | unsigned int vendorId; |
|
185 | unsigned int vendorId; | |
185 | unsigned int deviceId; |
|
186 | unsigned int deviceId; | |
186 |
|
187 | |||
187 | plugAndPlayRegister = (unsigned int*) REGS_ADDR_PLUGANDPLAY; |
|
188 | plugAndPlayRegister = (unsigned int*) REGS_ADDR_PLUGANDPLAY; | |
188 | vendorId = ( (*plugAndPlayRegister) & 0xff000000 ) >> 24; |
|
189 | vendorId = ( (*plugAndPlayRegister) & 0xff000000 ) >> 24; | |
189 | deviceId = ( (*plugAndPlayRegister) & 0x00fff000 ) >> 12; |
|
190 | deviceId = ( (*plugAndPlayRegister) & 0x00fff000 ) >> 12; | |
190 |
|
191 | |||
191 | cacheControlRegister = CCR_getValue(); |
|
192 | cacheControlRegister = CCR_getValue(); | |
192 |
|
193 | |||
193 | if( (vendorId == VENDORID_GAISLER) & (deviceId ==DEVICEID_LEON3FT) ) |
|
194 | if( (vendorId == VENDORID_GAISLER) & (deviceId ==DEVICEID_LEON3FT) ) | |
194 | { |
|
195 | { | |
195 | PRINTF("in faultTolerantScheme *** Leon3FT detected\n"); |
|
196 | PRINTF("in faultTolerantScheme *** Leon3FT detected\n"); | |
196 | PRINTF2(" *** vendorID = 0x%x, deviceId = 0x%x\n", vendorId, deviceId); |
|
197 | PRINTF2(" *** vendorID = 0x%x, deviceId = 0x%x\n", vendorId, deviceId); | |
197 | PRINTF1("ASR16 IU RF protection, bit 0 (IDI) is: 0x%x (0 => protection enabled)\n", |
|
198 | PRINTF1("ASR16 IU RF protection, bit 0 (IDI) is: 0x%x (0 => protection enabled)\n", | |
198 | (*asr16Ptr >> POS_IDI) & 1); |
|
199 | (*asr16Ptr >> POS_IDI) & 1); | |
199 | PRINTF1("ASR16 FP RF protection, bit 16 (FDI) is: 0x%x (0 => protection enabled)\n", |
|
200 | PRINTF1("ASR16 FP RF protection, bit 16 (FDI) is: 0x%x (0 => protection enabled)\n", | |
200 | (*asr16Ptr >> POS_FDI) & 1); |
|
201 | (*asr16Ptr >> POS_FDI) & 1); | |
201 | PRINTF1("ASR16 IU FT ID bits [15:14] is: 0x%x (2 => 8-bit parity without restart)\n", |
|
202 | PRINTF1("ASR16 IU FT ID bits [15:14] is: 0x%x (2 => 8-bit parity without restart)\n", | |
202 | (*asr16Ptr >> POS_IUFTID) & 0x3); |
|
203 | (*asr16Ptr >> POS_IUFTID) & 0x3); | |
203 | PRINTF1("ASR16 FP FT ID bits [31:30] is: 0x%x (1 => 4-bit parity with restart)\n", |
|
204 | PRINTF1("ASR16 FP FT ID bits [31:30] is: 0x%x (1 => 4-bit parity with restart)\n", | |
204 | (*asr16Ptr >> POS_FPFTID) & 0x03); |
|
205 | (*asr16Ptr >> POS_FPFTID) & 0x03); | |
205 | PRINTF1("CCR FT bits [20:19] are: 0x%x (1 => 4-bit parity with restart)\n", |
|
206 | PRINTF1("CCR FT bits [20:19] are: 0x%x (1 => 4-bit parity with restart)\n", | |
206 | (cacheControlRegister >> POS_FT) & 0x3 ); |
|
207 | (cacheControlRegister >> POS_FT) & 0x3 ); | |
207 |
|
208 | |||
208 | // CCR The FFT bits are just read, the FT scheme is set to β01β = 4-bit checking implemented by default |
|
209 | // CCR The FFT bits are just read, the FT scheme is set to β01β = 4-bit checking implemented by default | |
209 |
|
210 | |||
210 | // ASR16 Ancillary State Register configuration (Register protection control register) |
|
211 | // ASR16 Ancillary State Register configuration (Register protection control register) | |
211 | // IU RF protection is set by default, bit 0 IDI = 0 |
|
212 | // IU RF protection is set by default, bit 0 IDI = 0 | |
212 | // FP RF protection is set by default, bit 16 FDI = 0 |
|
213 | // FP RF protection is set by default, bit 16 FDI = 0 | |
213 | } |
|
214 | } | |
214 | else |
|
215 | else | |
215 | { |
|
216 | { | |
216 | PRINTF("in faultTolerantScheme *** Leon3FT not detected\n"); |
|
217 | PRINTF("in faultTolerantScheme *** Leon3FT not detected\n"); | |
217 | PRINTF2(" *** vendorID = 0x%x, deviceId = 0x%x\n", vendorId, deviceId); |
|
218 | PRINTF2(" *** vendorID = 0x%x, deviceId = 0x%x\n", vendorId, deviceId); | |
218 | } |
|
219 | } | |
219 | } |
|
220 | } | |
220 |
|
221 | |||
221 | #endif /* GSCMEMORY_HPP_ */ |
|
222 | #endif /* GSCMEMORY_HPP_ */ |
@@ -1,136 +1,136 | |||||
1 | cmake_minimum_required (VERSION 3.5) |
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1 | cmake_minimum_required (VERSION 3.5) | |
2 | project (fsw) |
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2 | project (fsw) | |
3 |
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3 | |||
4 | include(sparc-rtems) |
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4 | include(sparc-rtems) | |
5 | include(cppcheck) |
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5 | include(cppcheck) | |
6 |
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6 | |||
7 | include_directories("../header" |
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7 | include_directories("../header" | |
8 | "../header/lfr_common_headers" |
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8 | "../header/lfr_common_headers" | |
9 | "../header/processing" |
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9 | "../header/processing" | |
10 | "../LFR_basic-parameters" |
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10 | "../LFR_basic-parameters" | |
11 | "../src") |
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11 | "../src") | |
12 |
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12 | |||
13 | set(SOURCES wf_handler.c |
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13 | set(SOURCES wf_handler.c | |
14 | tc_handler.c |
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14 | tc_handler.c | |
15 | fsw_misc.c |
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15 | fsw_misc.c | |
16 | fsw_init.c |
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16 | fsw_init.c | |
17 | fsw_globals.c |
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17 | fsw_globals.c | |
18 | fsw_spacewire.c |
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18 | fsw_spacewire.c | |
19 | tc_load_dump_parameters.c |
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19 | tc_load_dump_parameters.c | |
20 | tm_lfr_tc_exe.c |
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20 | tm_lfr_tc_exe.c | |
21 | tc_acceptance.c |
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21 | tc_acceptance.c | |
22 | processing/fsw_processing.c |
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22 | processing/fsw_processing.c | |
23 | processing/avf0_prc0.c |
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23 | processing/avf0_prc0.c | |
24 | processing/avf1_prc1.c |
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24 | processing/avf1_prc1.c | |
25 | processing/avf2_prc2.c |
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25 | processing/avf2_prc2.c | |
26 | lfr_cpu_usage_report.c |
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26 | lfr_cpu_usage_report.c | |
27 | ${LFR_BP_SRC} |
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27 | ${LFR_BP_SRC} | |
28 | ../header/wf_handler.h |
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28 | ../header/wf_handler.h | |
29 | ../header/tc_handler.h |
|
29 | ../header/tc_handler.h | |
30 | ../header/grlib_regs.h |
|
30 | ../header/grlib_regs.h | |
31 | ../header/fsw_misc.h |
|
31 | ../header/fsw_misc.h | |
32 | ../header/fsw_init.h |
|
32 | ../header/fsw_init.h | |
33 | ../header/fsw_spacewire.h |
|
33 | ../header/fsw_spacewire.h | |
34 | ../header/tc_load_dump_parameters.h |
|
34 | ../header/tc_load_dump_parameters.h | |
35 | ../header/tm_lfr_tc_exe.h |
|
35 | ../header/tm_lfr_tc_exe.h | |
36 | ../header/tc_acceptance.h |
|
36 | ../header/tc_acceptance.h | |
37 | ../header/processing/fsw_processing.h |
|
37 | ../header/processing/fsw_processing.h | |
38 | ../header/processing/avf0_prc0.h |
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38 | ../header/processing/avf0_prc0.h | |
39 | ../header/processing/avf1_prc1.h |
|
39 | ../header/processing/avf1_prc1.h | |
40 | ../header/processing/avf2_prc2.h |
|
40 | ../header/processing/avf2_prc2.h | |
41 | ../header/fsw_params_wf_handler.h |
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41 | ../header/fsw_params_wf_handler.h | |
42 | ../header/lfr_cpu_usage_report.h |
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42 | ../header/lfr_cpu_usage_report.h | |
43 | ../header/lfr_common_headers/ccsds_types.h |
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43 | ../header/lfr_common_headers/ccsds_types.h | |
44 | ../header/lfr_common_headers/fsw_params.h |
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44 | ../header/lfr_common_headers/fsw_params.h | |
45 | ../header/lfr_common_headers/fsw_params_nb_bytes.h |
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45 | ../header/lfr_common_headers/fsw_params_nb_bytes.h | |
46 | ../header/lfr_common_headers/fsw_params_processing.h |
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46 | ../header/lfr_common_headers/fsw_params_processing.h | |
47 | ../header/lfr_common_headers/tm_byte_positions.h |
|
47 | ../header/lfr_common_headers/tm_byte_positions.h | |
48 | ../LFR_basic-parameters/basic_parameters.h |
|
48 | ../LFR_basic-parameters/basic_parameters.h | |
49 | ../LFR_basic-parameters/basic_parameters_params.h |
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49 | ../LFR_basic-parameters/basic_parameters_params.h | |
50 | ../header/GscMemoryLPP.hpp |
|
50 | ../header/GscMemoryLPP.hpp | |
51 | ) |
|
51 | ) | |
52 |
|
52 | |||
53 |
|
53 | |||
54 | option(FSW_verbose "Enable verbose LFR" OFF) |
|
54 | option(FSW_verbose "Enable verbose LFR" OFF) | |
55 | option(FSW_boot_messages "Enable LFR boot messages" OFF) |
|
55 | option(FSW_boot_messages "Enable LFR boot messages" OFF) | |
56 | option(FSW_debug_messages "Enable LFR debug messages" OFF) |
|
56 | option(FSW_debug_messages "Enable LFR debug messages" OFF) | |
57 | option(FSW_cpu_usage_report "Enable LFR cpu usage report" OFF) |
|
57 | option(FSW_cpu_usage_report "Enable LFR cpu usage report" OFF) | |
58 | option(FSW_stack_report "Enable LFR stack report" OFF) |
|
58 | option(FSW_stack_report "Enable LFR stack report" OFF) | |
59 | option(FSW_vhdl_dev "?" OFF) |
|
59 | option(FSW_vhdl_dev "?" OFF) | |
60 | option(FSW_lpp_dpu_destid "Set to debug at LPP" OFF) |
|
60 | option(FSW_lpp_dpu_destid "Set to debug at LPP" OFF) | |
61 | option(FSW_debug_watchdog "Enable debug watchdog" OFF) |
|
61 | option(FSW_debug_watchdog "Enable debug watchdog" OFF) | |
62 | option(FSW_debug_tch "?" OFF) |
|
62 | option(FSW_debug_tch "?" OFF) | |
63 | option(FSW_Instrument_Scrubbing "Enable scrubbing counter" OFF) |
|
63 | option(FSW_Instrument_Scrubbing "Enable scrubbing counter" OFF) | |
64 | option(FSW_Enable_Dead_Code "Enable dead code compilation, this is used to hide by default unused code." OFF) |
|
64 | option(FSW_Enable_Dead_Code "Enable dead code compilation, this is used to hide by default unused code." OFF) | |
65 |
|
65 | |||
66 | set(SW_VERSION_N1 "3" CACHE STRING "Choose N1 FSW Version." FORCE) |
|
66 | set(SW_VERSION_N1 "3" CACHE STRING "Choose N1 FSW Version." FORCE) | |
67 | set(SW_VERSION_N2 "2" CACHE STRING "Choose N2 FSW Version." FORCE) |
|
67 | set(SW_VERSION_N2 "2" CACHE STRING "Choose N2 FSW Version." FORCE) | |
68 | set(SW_VERSION_N3 "0" CACHE STRING "Choose N3 FSW Version." FORCE) |
|
68 | set(SW_VERSION_N3 "0" CACHE STRING "Choose N3 FSW Version." FORCE) | |
69 |
set(SW_VERSION_N4 "2 |
|
69 | set(SW_VERSION_N4 "23" CACHE STRING "Choose N4 FSW Version." FORCE) | |
70 |
|
70 | |||
71 | if(FSW_verbose) |
|
71 | if(FSW_verbose) | |
72 | add_definitions(-DPRINT_MESSAGES_ON_CONSOLE) |
|
72 | add_definitions(-DPRINT_MESSAGES_ON_CONSOLE) | |
73 | endif() |
|
73 | endif() | |
74 | if(FSW_boot_messages) |
|
74 | if(FSW_boot_messages) | |
75 | add_definitions(-DBOOT_MESSAGES) |
|
75 | add_definitions(-DBOOT_MESSAGES) | |
76 | endif() |
|
76 | endif() | |
77 | if(FSW_debug_messages) |
|
77 | if(FSW_debug_messages) | |
78 | add_definitions(-DDEBUG_MESSAGES) |
|
78 | add_definitions(-DDEBUG_MESSAGES) | |
79 | endif() |
|
79 | endif() | |
80 | if(FSW_cpu_usage_report) |
|
80 | if(FSW_cpu_usage_report) | |
81 | add_definitions(-DPRINT_TASK_STATISTICS) |
|
81 | add_definitions(-DPRINT_TASK_STATISTICS) | |
82 | endif() |
|
82 | endif() | |
83 | if(FSW_stack_report) |
|
83 | if(FSW_stack_report) | |
84 | add_definitions(-DPRINT_STACK_REPORT) |
|
84 | add_definitions(-DPRINT_STACK_REPORT) | |
85 | endif() |
|
85 | endif() | |
86 | if(FSW_vhdl_dev) |
|
86 | if(FSW_vhdl_dev) | |
87 | add_definitions(-DVHDL_DEV) |
|
87 | add_definitions(-DVHDL_DEV) | |
88 | endif() |
|
88 | endif() | |
89 | if(FSW_lpp_dpu_destid) |
|
89 | if(FSW_lpp_dpu_destid) | |
90 | add_definitions(-DLPP_DPU_DESTID) |
|
90 | add_definitions(-DLPP_DPU_DESTID) | |
91 | endif() |
|
91 | endif() | |
92 | if(FSW_debug_watchdog) |
|
92 | if(FSW_debug_watchdog) | |
93 | add_definitions(-DDEBUG_WATCHDOG) |
|
93 | add_definitions(-DDEBUG_WATCHDOG) | |
94 | endif() |
|
94 | endif() | |
95 | if(FSW_debug_tch) |
|
95 | if(FSW_debug_tch) | |
96 | add_definitions(-DDEBUG_TCH) |
|
96 | add_definitions(-DDEBUG_TCH) | |
97 | endif() |
|
97 | endif() | |
98 |
|
98 | |||
99 | if(FSW_Enable_Dead_Code) |
|
99 | if(FSW_Enable_Dead_Code) | |
100 | add_definitions(-DENABLE_DEAD_CODE) |
|
100 | add_definitions(-DENABLE_DEAD_CODE) | |
101 | endif() |
|
101 | endif() | |
102 |
|
102 | |||
103 |
|
103 | |||
104 |
|
104 | |||
105 |
|
105 | |||
106 | add_definitions(-DMSB_FIRST_TCH) |
|
106 | add_definitions(-DMSB_FIRST_TCH) | |
107 |
|
107 | |||
108 | add_definitions(-DSWVERSION=-1-0) |
|
108 | add_definitions(-DSWVERSION=-1-0) | |
109 | add_definitions(-DSW_VERSION_N1=${SW_VERSION_N1}) |
|
109 | add_definitions(-DSW_VERSION_N1=${SW_VERSION_N1}) | |
110 | add_definitions(-DSW_VERSION_N2=${SW_VERSION_N2}) |
|
110 | add_definitions(-DSW_VERSION_N2=${SW_VERSION_N2}) | |
111 | add_definitions(-DSW_VERSION_N3=${SW_VERSION_N3}) |
|
111 | add_definitions(-DSW_VERSION_N3=${SW_VERSION_N3}) | |
112 | add_definitions(-DSW_VERSION_N4=${SW_VERSION_N4}) |
|
112 | add_definitions(-DSW_VERSION_N4=${SW_VERSION_N4}) | |
113 |
|
113 | |||
114 | add_executable(fsw ${SOURCES}) |
|
114 | add_executable(fsw ${SOURCES}) | |
115 |
|
115 | |||
116 | if(FSW_Instrument_Scrubbing) |
|
116 | if(FSW_Instrument_Scrubbing) | |
117 | add_definitions(-DENABLE_SCRUBBING_COUNTER) |
|
117 | add_definitions(-DENABLE_SCRUBBING_COUNTER) | |
118 | endif() |
|
118 | endif() | |
119 |
|
119 | |||
120 | if(Coverage) |
|
120 | if(Coverage) | |
121 | target_link_libraries(fsw gcov) |
|
121 | target_link_libraries(fsw gcov) | |
122 | SET_TARGET_PROPERTIES(fsw PROPERTIES COMPILE_FLAGS "-fprofile-arcs -ftest-coverage") |
|
122 | SET_TARGET_PROPERTIES(fsw PROPERTIES COMPILE_FLAGS "-fprofile-arcs -ftest-coverage") | |
123 | endif() |
|
123 | endif() | |
124 |
|
124 | |||
125 |
|
125 | |||
126 | if(fix-b2bst) |
|
126 | if(fix-b2bst) | |
127 | check_b2bst(fsw ${CMAKE_CURRENT_BINARY_DIR}) |
|
127 | check_b2bst(fsw ${CMAKE_CURRENT_BINARY_DIR}) | |
128 | endif() |
|
128 | endif() | |
129 |
|
129 | |||
130 | if(NOT FSW_lpp_dpu_destid) |
|
130 | if(NOT FSW_lpp_dpu_destid) | |
131 | build_srec(fsw ${CMAKE_CURRENT_BINARY_DIR} "${SW_VERSION_N1}-${SW_VERSION_N2}-${SW_VERSION_N3}-${SW_VERSION_N4}") |
|
131 | build_srec(fsw ${CMAKE_CURRENT_BINARY_DIR} "${SW_VERSION_N1}-${SW_VERSION_N2}-${SW_VERSION_N3}-${SW_VERSION_N4}") | |
132 | endif() |
|
132 | endif() | |
133 |
|
133 | |||
134 |
|
134 | |||
135 | #add_test_cppcheck(fsw STYLE UNUSED_FUNCTIONS POSSIBLE_ERROR MISSING_INCLUDE) |
|
135 | #add_test_cppcheck(fsw STYLE UNUSED_FUNCTIONS POSSIBLE_ERROR MISSING_INCLUDE) | |
136 |
|
136 |
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