@@ -1,221 +1,222 | |||
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1 | 1 | #ifndef GSCMEMORY_HPP_ |
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2 | 2 | #define GSCMEMORY_HPP_ |
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3 | 3 | |
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4 | 4 | #ifndef LEON3 |
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5 | 5 | #define LEON3 |
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6 | 6 | #endif |
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7 | 7 | |
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8 | 8 | #define REGS_ADDR_PLUGANDPLAY 0xFFFFF000 |
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9 | 9 | #define ASR16_REG_ADDRESS 0x90400040 // Ancillary State Register 16 = Register protection control register (FT only) |
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10 | 10 | |
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11 | 11 | #define DEVICEID_LEON3 0x003 |
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12 | 12 | #define DEVICEID_LEON3FT 0x053 |
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13 | 13 | #define VENDORID_GAISLER 0x01 |
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14 | 14 | |
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15 | 15 | // CCR |
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16 | 16 | #define POS_FT 19 |
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17 | 17 | // |
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18 | 18 | #define POS_ITE 12 |
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19 | 19 | #define COUNTER_FIELD_ITE 0x00003000 // 0000 0000 0000 0000 0011 0000 0000 0000 |
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20 | 20 | #define COUNTER_MASK_ITE 0xffffcfff // 1111 1111 1111 1111 1100 1111 1111 1111 |
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21 | 21 | #define POS_IDE 10 |
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22 | 22 | #define COUNTER_FIELD_IDE 0x00000c00 // 0000 0000 0000 0000 0000 1100 0000 0000 |
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23 | 23 | #define COUNTER_MASK_IDE 0xfffff3ff // 1111 1111 1111 1111 1111 0011 1111 1111 |
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24 | 24 | // |
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25 | 25 | #define POS_DTE 8 |
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26 | 26 | #define COUNTER_FIELD_DTE 0x00000300 // 0000 0000 0000 0000 0000 0011 0000 0000 |
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27 | 27 | #define COUNTER_MASK_DTE 0xfffffcff // 1111 1111 1111 1111 1111 1100 1111 1111 |
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28 | 28 | #define POS_DDE 6 |
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29 | 29 | #define COUNTER_FIELD_DDE 0x000000c0 // 0000 0000 0000 0000 0000 0000 1100 0000 |
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30 | 30 | #define COUNTER_MASK_DDE 0xffffff3f // 1111 1111 1111 1111 1111 1111 0011 1111 |
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31 | 31 | |
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32 | 32 | // ASR16 |
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33 | 33 | #define POS_FPFTID 30 |
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34 | 34 | #define POS_FPRF 27 |
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35 | 35 | #define POS_FDI 16 // FP RF protection enable/disable |
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36 | 36 | #define POS_IUFTID 14 |
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37 | 37 | #define POS_IURF 11 |
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38 | 38 | #define POS_IDI 0 // IU RF protection enable/disable |
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39 | 39 | |
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40 | 40 | #define COUNTER_FIELD_FPRF 0x38000000 // 0011 1000 0000 0000 0000 0000 0000 0000 |
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41 | 41 | #define COUNTER_MASK_FPRF 0xc7ffffff // 1100 0111 1111 1111 1111 1111 1111 1111 |
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42 | 42 | |
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43 | 43 | #define COUNTER_FIELD_IURF 0x00003800 // 0000 0000 0000 0000 0011 1000 0000 0000 |
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44 | 44 | #define COUNTER_MASK_IURF 0xffffc7ff // 1111 1111 1111 1111 1100 0111 1111 1111 |
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45 | 45 | |
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46 | 46 | volatile unsigned int *asr16Ptr = (volatile unsigned int *) ASR16_REG_ADDRESS; |
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47 | ||
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47 | #ifdef ENABLE_DEAD_CODE | |
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48 | 48 | static inline void flushCache() |
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49 | 49 | { |
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50 | 50 | /** |
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51 | 51 | * Flush the data cache and the instruction cache. |
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52 | 52 | * |
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53 | 53 | * @param void |
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54 | 54 | * |
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55 | 55 | * @return void |
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56 | 56 | */ |
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57 | 57 | |
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58 | 58 | asm("flush"); |
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59 | 59 | } |
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60 | #endif | |
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60 | 61 | |
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61 | 62 | //*************************** |
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62 | 63 | // CCR Cache control register |
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63 | 64 | |
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64 | 65 | static unsigned int CCR_getValue() |
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65 | 66 | { |
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66 | 67 | unsigned int cacheControlRegister = 0; |
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67 | 68 | __asm__ __volatile__("lda [%%g0] 2, %0" : "=r"(cacheControlRegister) : ); |
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68 | 69 | return cacheControlRegister; |
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69 | 70 | } |
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70 | 71 | |
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71 | 72 | static void CCR_setValue(unsigned int cacheControlRegister) |
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72 | 73 | { |
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73 | 74 | __asm__ __volatile__("sta %0, [%%g0] 2" : : "r"(cacheControlRegister)); |
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74 | 75 | } |
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75 | 76 | |
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76 | 77 | static void CCR_resetCacheControlRegister() |
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77 | 78 | { |
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78 | 79 | unsigned int cacheControlRegister; |
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79 | 80 | cacheControlRegister = 0x00; |
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80 | 81 | CCR_setValue(cacheControlRegister); |
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81 | 82 | } |
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82 | 83 | |
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83 | 84 | static void CCR_enableInstructionCache() |
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84 | 85 | { |
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85 | 86 | // [1:0] Instruction Cache state (ICS) |
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86 | 87 | // Indicates the current data cache state according to the following: X0 = disabled, 01 = frozen, 11 = enabled. |
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87 | 88 | unsigned int cacheControlRegister; |
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88 | 89 | cacheControlRegister = CCR_getValue(); |
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89 | 90 | cacheControlRegister = (cacheControlRegister | 0x3); |
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90 | 91 | CCR_setValue(cacheControlRegister); |
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91 | 92 | } |
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92 | 93 | |
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93 | 94 | static void CCR_enableDataCache() |
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94 | 95 | { |
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95 | 96 | // [3:2] Data Cache state (DCS) |
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96 | 97 | // Indicates the current data cache state according to the following: X0 = disabled, 01 = frozen, 11 = enabled. |
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97 | 98 | unsigned int cacheControlRegister; |
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98 | 99 | cacheControlRegister = CCR_getValue(); |
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99 | 100 | cacheControlRegister = (cacheControlRegister | 0xc); |
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100 | 101 | CCR_setValue(cacheControlRegister); |
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101 | 102 | } |
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102 | 103 | |
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103 | 104 | static void CCR_enableInstructionBurstFetch() |
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104 | 105 | { |
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105 | 106 | // [16] Instruction burst fetch (IB). This bit enables burst fill during instruction fetch. |
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106 | 107 | unsigned int cacheControlRegister; |
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107 | 108 | cacheControlRegister = CCR_getValue(); |
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108 | 109 | // set the bit IB to 1 |
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109 | 110 | cacheControlRegister = (cacheControlRegister | 0x10000); |
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110 | 111 | CCR_setValue(cacheControlRegister); |
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111 | 112 | } |
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112 | 113 | |
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113 | 114 | void CCR_getInstructionAndDataErrorCounters( unsigned int* instructionErrorCounter, unsigned int* dataErrorCounter ) |
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114 | 115 | { |
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115 | 116 | // [13:12] Instruction Tag Errors (ITE) - Number of detected parity errors in the instruction tag cache. |
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116 | 117 | // Only available if fault-tolerance is enabled (FT field in this register is non-zero). |
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117 | 118 | // [11:10] Instruction Data Errors (IDE) - Number of detected parity errors in the instruction data cache. |
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118 | 119 | // Only available if fault-tolerance is enabled (FT field in this register is non-zero). |
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119 | 120 | |
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120 | 121 | unsigned int cacheControlRegister; |
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121 | 122 | unsigned int iTE; |
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122 | 123 | unsigned int iDE; |
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123 | 124 | unsigned int dTE; |
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124 | 125 | unsigned int dDE; |
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125 | 126 | |
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126 | 127 | cacheControlRegister = CCR_getValue(); |
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127 | 128 | iTE = (cacheControlRegister & COUNTER_FIELD_ITE) >> POS_ITE; |
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128 | 129 | iDE = (cacheControlRegister & COUNTER_FIELD_IDE) >> POS_IDE; |
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129 | 130 | dTE = (cacheControlRegister & COUNTER_FIELD_DTE) >> POS_DTE; |
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130 | 131 | dDE = (cacheControlRegister & COUNTER_FIELD_DDE) >> POS_DDE; |
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131 | 132 | |
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132 | 133 | *instructionErrorCounter = iTE + iDE; |
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133 | 134 | *dataErrorCounter = dTE + dDE; |
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134 | 135 | |
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135 | 136 | // reset counters |
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136 | 137 | cacheControlRegister = cacheControlRegister |
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137 | 138 | & COUNTER_FIELD_ITE |
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138 | 139 | & COUNTER_FIELD_IDE |
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139 | 140 | & COUNTER_FIELD_DTE |
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140 | 141 | & COUNTER_FIELD_DDE; |
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141 | 142 | |
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142 | 143 | CCR_setValue(cacheControlRegister); |
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143 | 144 | } |
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144 | 145 | |
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145 | 146 | //******************************************* |
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146 | 147 | // ASR16 Register protection control register |
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147 | 148 | |
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148 | 149 | static void ASR16_resetRegisterProtectionControlRegister() |
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149 | 150 | { |
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150 | 151 | *asr16Ptr = 0x00; |
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151 | 152 | } |
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152 | 153 | |
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153 | 154 | void ASR16_get_FPRF_IURF_ErrorCounters( unsigned int* fprfErrorCounter, unsigned int* iurfErrorCounter) |
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154 | 155 | { |
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155 | 156 | /** This function is used to retrieve the integer unit register file error counter and the floating point unit |
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156 | 157 | * register file error counter |
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157 | 158 | * |
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158 | 159 | * @return void |
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159 | 160 | * |
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160 | 161 | * [29:27] FP RF error counter - Number of detected parity errors in the FP register file. |
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161 | 162 | * [13:11] IU RF error counter - Number of detected parity errors in the IU register file. |
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162 | 163 | * |
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163 | 164 | */ |
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164 | 165 | |
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165 | 166 | unsigned int asr16; |
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166 | 167 | |
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167 | 168 | asr16 = *asr16Ptr; |
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168 | 169 | *fprfErrorCounter = ( asr16 & COUNTER_FIELD_FPRF ) >> POS_FPRF; |
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169 | 170 | *iurfErrorCounter = ( asr16 & COUNTER_FIELD_IURF ) >> POS_IURF; |
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170 | 171 | |
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171 | 172 | // reset the counter to 0 |
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172 | 173 | asr16 = asr16 |
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173 | 174 | & COUNTER_MASK_FPRF |
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174 | 175 | & COUNTER_FIELD_IURF; |
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175 | 176 | |
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176 | 177 | *asr16Ptr = asr16; |
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177 | 178 | } |
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178 | 179 | |
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179 | 180 | static void faultTolerantScheme() |
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180 | 181 | { |
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181 | 182 | // [20:19] FT scheme (FT) - β00β = no FT, β01β = 4-bit checking implemented |
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182 | 183 | unsigned int cacheControlRegister; |
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183 | 184 | unsigned int *plugAndPlayRegister; |
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184 | 185 | unsigned int vendorId; |
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185 | 186 | unsigned int deviceId; |
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186 | 187 | |
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187 | 188 | plugAndPlayRegister = (unsigned int*) REGS_ADDR_PLUGANDPLAY; |
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188 | 189 | vendorId = ( (*plugAndPlayRegister) & 0xff000000 ) >> 24; |
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189 | 190 | deviceId = ( (*plugAndPlayRegister) & 0x00fff000 ) >> 12; |
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190 | 191 | |
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191 | 192 | cacheControlRegister = CCR_getValue(); |
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192 | 193 | |
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193 | 194 | if( (vendorId == VENDORID_GAISLER) & (deviceId ==DEVICEID_LEON3FT) ) |
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194 | 195 | { |
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195 | 196 | PRINTF("in faultTolerantScheme *** Leon3FT detected\n"); |
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196 | 197 | PRINTF2(" *** vendorID = 0x%x, deviceId = 0x%x\n", vendorId, deviceId); |
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197 | 198 | PRINTF1("ASR16 IU RF protection, bit 0 (IDI) is: 0x%x (0 => protection enabled)\n", |
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198 | 199 | (*asr16Ptr >> POS_IDI) & 1); |
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199 | 200 | PRINTF1("ASR16 FP RF protection, bit 16 (FDI) is: 0x%x (0 => protection enabled)\n", |
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200 | 201 | (*asr16Ptr >> POS_FDI) & 1); |
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201 | 202 | PRINTF1("ASR16 IU FT ID bits [15:14] is: 0x%x (2 => 8-bit parity without restart)\n", |
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202 | 203 | (*asr16Ptr >> POS_IUFTID) & 0x3); |
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203 | 204 | PRINTF1("ASR16 FP FT ID bits [31:30] is: 0x%x (1 => 4-bit parity with restart)\n", |
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204 | 205 | (*asr16Ptr >> POS_FPFTID) & 0x03); |
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205 | 206 | PRINTF1("CCR FT bits [20:19] are: 0x%x (1 => 4-bit parity with restart)\n", |
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206 | 207 | (cacheControlRegister >> POS_FT) & 0x3 ); |
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207 | 208 | |
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208 | 209 | // CCR The FFT bits are just read, the FT scheme is set to β01β = 4-bit checking implemented by default |
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209 | 210 | |
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210 | 211 | // ASR16 Ancillary State Register configuration (Register protection control register) |
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211 | 212 | // IU RF protection is set by default, bit 0 IDI = 0 |
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212 | 213 | // FP RF protection is set by default, bit 16 FDI = 0 |
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213 | 214 | } |
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214 | 215 | else |
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215 | 216 | { |
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216 | 217 | PRINTF("in faultTolerantScheme *** Leon3FT not detected\n"); |
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217 | 218 | PRINTF2(" *** vendorID = 0x%x, deviceId = 0x%x\n", vendorId, deviceId); |
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218 | 219 | } |
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219 | 220 | } |
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220 | 221 | |
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221 | 222 | #endif /* GSCMEMORY_HPP_ */ |
@@ -1,136 +1,136 | |||
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1 | 1 | cmake_minimum_required (VERSION 3.5) |
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2 | 2 | project (fsw) |
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3 | 3 | |
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4 | 4 | include(sparc-rtems) |
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5 | 5 | include(cppcheck) |
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6 | 6 | |
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7 | 7 | include_directories("../header" |
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8 | 8 | "../header/lfr_common_headers" |
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9 | 9 | "../header/processing" |
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10 | 10 | "../LFR_basic-parameters" |
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11 | 11 | "../src") |
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12 | 12 | |
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13 | 13 | set(SOURCES wf_handler.c |
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14 | 14 | tc_handler.c |
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15 | 15 | fsw_misc.c |
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16 | 16 | fsw_init.c |
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17 | 17 | fsw_globals.c |
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18 | 18 | fsw_spacewire.c |
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19 | 19 | tc_load_dump_parameters.c |
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20 | 20 | tm_lfr_tc_exe.c |
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21 | 21 | tc_acceptance.c |
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22 | 22 | processing/fsw_processing.c |
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23 | 23 | processing/avf0_prc0.c |
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24 | 24 | processing/avf1_prc1.c |
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25 | 25 | processing/avf2_prc2.c |
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26 | 26 | lfr_cpu_usage_report.c |
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27 | 27 | ${LFR_BP_SRC} |
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28 | 28 | ../header/wf_handler.h |
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29 | 29 | ../header/tc_handler.h |
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30 | 30 | ../header/grlib_regs.h |
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31 | 31 | ../header/fsw_misc.h |
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32 | 32 | ../header/fsw_init.h |
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33 | 33 | ../header/fsw_spacewire.h |
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34 | 34 | ../header/tc_load_dump_parameters.h |
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35 | 35 | ../header/tm_lfr_tc_exe.h |
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36 | 36 | ../header/tc_acceptance.h |
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37 | 37 | ../header/processing/fsw_processing.h |
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38 | 38 | ../header/processing/avf0_prc0.h |
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39 | 39 | ../header/processing/avf1_prc1.h |
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40 | 40 | ../header/processing/avf2_prc2.h |
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41 | 41 | ../header/fsw_params_wf_handler.h |
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42 | 42 | ../header/lfr_cpu_usage_report.h |
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43 | 43 | ../header/lfr_common_headers/ccsds_types.h |
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44 | 44 | ../header/lfr_common_headers/fsw_params.h |
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45 | 45 | ../header/lfr_common_headers/fsw_params_nb_bytes.h |
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46 | 46 | ../header/lfr_common_headers/fsw_params_processing.h |
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47 | 47 | ../header/lfr_common_headers/tm_byte_positions.h |
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48 | 48 | ../LFR_basic-parameters/basic_parameters.h |
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49 | 49 | ../LFR_basic-parameters/basic_parameters_params.h |
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50 | 50 | ../header/GscMemoryLPP.hpp |
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51 | 51 | ) |
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52 | 52 | |
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53 | 53 | |
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54 | 54 | option(FSW_verbose "Enable verbose LFR" OFF) |
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55 | 55 | option(FSW_boot_messages "Enable LFR boot messages" OFF) |
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56 | 56 | option(FSW_debug_messages "Enable LFR debug messages" OFF) |
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57 | 57 | option(FSW_cpu_usage_report "Enable LFR cpu usage report" OFF) |
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58 | 58 | option(FSW_stack_report "Enable LFR stack report" OFF) |
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59 | 59 | option(FSW_vhdl_dev "?" OFF) |
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60 | 60 | option(FSW_lpp_dpu_destid "Set to debug at LPP" OFF) |
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61 | 61 | option(FSW_debug_watchdog "Enable debug watchdog" OFF) |
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62 | 62 | option(FSW_debug_tch "?" OFF) |
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63 | 63 | option(FSW_Instrument_Scrubbing "Enable scrubbing counter" OFF) |
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64 | 64 | option(FSW_Enable_Dead_Code "Enable dead code compilation, this is used to hide by default unused code." OFF) |
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65 | 65 | |
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66 | 66 | set(SW_VERSION_N1 "3" CACHE STRING "Choose N1 FSW Version." FORCE) |
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67 | 67 | set(SW_VERSION_N2 "2" CACHE STRING "Choose N2 FSW Version." FORCE) |
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68 | 68 | set(SW_VERSION_N3 "0" CACHE STRING "Choose N3 FSW Version." FORCE) |
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69 |
set(SW_VERSION_N4 "2 |
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69 | set(SW_VERSION_N4 "23" CACHE STRING "Choose N4 FSW Version." FORCE) | |
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70 | 70 | |
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71 | 71 | if(FSW_verbose) |
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72 | 72 | add_definitions(-DPRINT_MESSAGES_ON_CONSOLE) |
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73 | 73 | endif() |
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74 | 74 | if(FSW_boot_messages) |
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75 | 75 | add_definitions(-DBOOT_MESSAGES) |
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76 | 76 | endif() |
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77 | 77 | if(FSW_debug_messages) |
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78 | 78 | add_definitions(-DDEBUG_MESSAGES) |
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79 | 79 | endif() |
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80 | 80 | if(FSW_cpu_usage_report) |
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81 | 81 | add_definitions(-DPRINT_TASK_STATISTICS) |
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82 | 82 | endif() |
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83 | 83 | if(FSW_stack_report) |
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84 | 84 | add_definitions(-DPRINT_STACK_REPORT) |
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85 | 85 | endif() |
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86 | 86 | if(FSW_vhdl_dev) |
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87 | 87 | add_definitions(-DVHDL_DEV) |
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88 | 88 | endif() |
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89 | 89 | if(FSW_lpp_dpu_destid) |
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90 | 90 | add_definitions(-DLPP_DPU_DESTID) |
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91 | 91 | endif() |
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92 | 92 | if(FSW_debug_watchdog) |
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93 | 93 | add_definitions(-DDEBUG_WATCHDOG) |
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94 | 94 | endif() |
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95 | 95 | if(FSW_debug_tch) |
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96 | 96 | add_definitions(-DDEBUG_TCH) |
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97 | 97 | endif() |
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98 | 98 | |
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99 | 99 | if(FSW_Enable_Dead_Code) |
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100 | 100 | add_definitions(-DENABLE_DEAD_CODE) |
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101 | 101 | endif() |
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102 | 102 | |
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103 | 103 | |
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104 | 104 | |
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105 | 105 | |
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106 | 106 | add_definitions(-DMSB_FIRST_TCH) |
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107 | 107 | |
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108 | 108 | add_definitions(-DSWVERSION=-1-0) |
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109 | 109 | add_definitions(-DSW_VERSION_N1=${SW_VERSION_N1}) |
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110 | 110 | add_definitions(-DSW_VERSION_N2=${SW_VERSION_N2}) |
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111 | 111 | add_definitions(-DSW_VERSION_N3=${SW_VERSION_N3}) |
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112 | 112 | add_definitions(-DSW_VERSION_N4=${SW_VERSION_N4}) |
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113 | 113 | |
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114 | 114 | add_executable(fsw ${SOURCES}) |
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115 | 115 | |
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116 | 116 | if(FSW_Instrument_Scrubbing) |
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117 | 117 | add_definitions(-DENABLE_SCRUBBING_COUNTER) |
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118 | 118 | endif() |
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119 | 119 | |
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120 | 120 | if(Coverage) |
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121 | 121 | target_link_libraries(fsw gcov) |
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122 | 122 | SET_TARGET_PROPERTIES(fsw PROPERTIES COMPILE_FLAGS "-fprofile-arcs -ftest-coverage") |
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123 | 123 | endif() |
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124 | 124 | |
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125 | 125 | |
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126 | 126 | if(fix-b2bst) |
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127 | 127 | check_b2bst(fsw ${CMAKE_CURRENT_BINARY_DIR}) |
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128 | 128 | endif() |
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129 | 129 | |
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130 | 130 | if(NOT FSW_lpp_dpu_destid) |
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131 | 131 | build_srec(fsw ${CMAKE_CURRENT_BINARY_DIR} "${SW_VERSION_N1}-${SW_VERSION_N2}-${SW_VERSION_N3}-${SW_VERSION_N4}") |
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132 | 132 | endif() |
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133 | 133 | |
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134 | 134 | |
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135 | 135 | #add_test_cppcheck(fsw STYLE UNUSED_FUNCTIONS POSSIBLE_ERROR MISSING_INCLUDE) |
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136 | 136 |
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