##// END OF EJS Templates
Removed last dead code function found and set FSW ver to 3.2.0.23
jeandet -
r403:56ae035bb062 3.2.0.23 R3++ draft
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@@ -1,221 +1,222
1 1 #ifndef GSCMEMORY_HPP_
2 2 #define GSCMEMORY_HPP_
3 3
4 4 #ifndef LEON3
5 5 #define LEON3
6 6 #endif
7 7
8 8 #define REGS_ADDR_PLUGANDPLAY 0xFFFFF000
9 9 #define ASR16_REG_ADDRESS 0x90400040 // Ancillary State Register 16 = Register protection control register (FT only)
10 10
11 11 #define DEVICEID_LEON3 0x003
12 12 #define DEVICEID_LEON3FT 0x053
13 13 #define VENDORID_GAISLER 0x01
14 14
15 15 // CCR
16 16 #define POS_FT 19
17 17 //
18 18 #define POS_ITE 12
19 19 #define COUNTER_FIELD_ITE 0x00003000 // 0000 0000 0000 0000 0011 0000 0000 0000
20 20 #define COUNTER_MASK_ITE 0xffffcfff // 1111 1111 1111 1111 1100 1111 1111 1111
21 21 #define POS_IDE 10
22 22 #define COUNTER_FIELD_IDE 0x00000c00 // 0000 0000 0000 0000 0000 1100 0000 0000
23 23 #define COUNTER_MASK_IDE 0xfffff3ff // 1111 1111 1111 1111 1111 0011 1111 1111
24 24 //
25 25 #define POS_DTE 8
26 26 #define COUNTER_FIELD_DTE 0x00000300 // 0000 0000 0000 0000 0000 0011 0000 0000
27 27 #define COUNTER_MASK_DTE 0xfffffcff // 1111 1111 1111 1111 1111 1100 1111 1111
28 28 #define POS_DDE 6
29 29 #define COUNTER_FIELD_DDE 0x000000c0 // 0000 0000 0000 0000 0000 0000 1100 0000
30 30 #define COUNTER_MASK_DDE 0xffffff3f // 1111 1111 1111 1111 1111 1111 0011 1111
31 31
32 32 // ASR16
33 33 #define POS_FPFTID 30
34 34 #define POS_FPRF 27
35 35 #define POS_FDI 16 // FP RF protection enable/disable
36 36 #define POS_IUFTID 14
37 37 #define POS_IURF 11
38 38 #define POS_IDI 0 // IU RF protection enable/disable
39 39
40 40 #define COUNTER_FIELD_FPRF 0x38000000 // 0011 1000 0000 0000 0000 0000 0000 0000
41 41 #define COUNTER_MASK_FPRF 0xc7ffffff // 1100 0111 1111 1111 1111 1111 1111 1111
42 42
43 43 #define COUNTER_FIELD_IURF 0x00003800 // 0000 0000 0000 0000 0011 1000 0000 0000
44 44 #define COUNTER_MASK_IURF 0xffffc7ff // 1111 1111 1111 1111 1100 0111 1111 1111
45 45
46 46 volatile unsigned int *asr16Ptr = (volatile unsigned int *) ASR16_REG_ADDRESS;
47
47 #ifdef ENABLE_DEAD_CODE
48 48 static inline void flushCache()
49 49 {
50 50 /**
51 51 * Flush the data cache and the instruction cache.
52 52 *
53 53 * @param void
54 54 *
55 55 * @return void
56 56 */
57 57
58 58 asm("flush");
59 59 }
60 #endif
60 61
61 62 //***************************
62 63 // CCR Cache control register
63 64
64 65 static unsigned int CCR_getValue()
65 66 {
66 67 unsigned int cacheControlRegister = 0;
67 68 __asm__ __volatile__("lda [%%g0] 2, %0" : "=r"(cacheControlRegister) : );
68 69 return cacheControlRegister;
69 70 }
70 71
71 72 static void CCR_setValue(unsigned int cacheControlRegister)
72 73 {
73 74 __asm__ __volatile__("sta %0, [%%g0] 2" : : "r"(cacheControlRegister));
74 75 }
75 76
76 77 static void CCR_resetCacheControlRegister()
77 78 {
78 79 unsigned int cacheControlRegister;
79 80 cacheControlRegister = 0x00;
80 81 CCR_setValue(cacheControlRegister);
81 82 }
82 83
83 84 static void CCR_enableInstructionCache()
84 85 {
85 86 // [1:0] Instruction Cache state (ICS)
86 87 // Indicates the current data cache state according to the following: X0 = disabled, 01 = frozen, 11 = enabled.
87 88 unsigned int cacheControlRegister;
88 89 cacheControlRegister = CCR_getValue();
89 90 cacheControlRegister = (cacheControlRegister | 0x3);
90 91 CCR_setValue(cacheControlRegister);
91 92 }
92 93
93 94 static void CCR_enableDataCache()
94 95 {
95 96 // [3:2] Data Cache state (DCS)
96 97 // Indicates the current data cache state according to the following: X0 = disabled, 01 = frozen, 11 = enabled.
97 98 unsigned int cacheControlRegister;
98 99 cacheControlRegister = CCR_getValue();
99 100 cacheControlRegister = (cacheControlRegister | 0xc);
100 101 CCR_setValue(cacheControlRegister);
101 102 }
102 103
103 104 static void CCR_enableInstructionBurstFetch()
104 105 {
105 106 // [16] Instruction burst fetch (IB). This bit enables burst fill during instruction fetch.
106 107 unsigned int cacheControlRegister;
107 108 cacheControlRegister = CCR_getValue();
108 109 // set the bit IB to 1
109 110 cacheControlRegister = (cacheControlRegister | 0x10000);
110 111 CCR_setValue(cacheControlRegister);
111 112 }
112 113
113 114 void CCR_getInstructionAndDataErrorCounters( unsigned int* instructionErrorCounter, unsigned int* dataErrorCounter )
114 115 {
115 116 // [13:12] Instruction Tag Errors (ITE) - Number of detected parity errors in the instruction tag cache.
116 117 // Only available if fault-tolerance is enabled (FT field in this register is non-zero).
117 118 // [11:10] Instruction Data Errors (IDE) - Number of detected parity errors in the instruction data cache.
118 119 // Only available if fault-tolerance is enabled (FT field in this register is non-zero).
119 120
120 121 unsigned int cacheControlRegister;
121 122 unsigned int iTE;
122 123 unsigned int iDE;
123 124 unsigned int dTE;
124 125 unsigned int dDE;
125 126
126 127 cacheControlRegister = CCR_getValue();
127 128 iTE = (cacheControlRegister & COUNTER_FIELD_ITE) >> POS_ITE;
128 129 iDE = (cacheControlRegister & COUNTER_FIELD_IDE) >> POS_IDE;
129 130 dTE = (cacheControlRegister & COUNTER_FIELD_DTE) >> POS_DTE;
130 131 dDE = (cacheControlRegister & COUNTER_FIELD_DDE) >> POS_DDE;
131 132
132 133 *instructionErrorCounter = iTE + iDE;
133 134 *dataErrorCounter = dTE + dDE;
134 135
135 136 // reset counters
136 137 cacheControlRegister = cacheControlRegister
137 138 & COUNTER_FIELD_ITE
138 139 & COUNTER_FIELD_IDE
139 140 & COUNTER_FIELD_DTE
140 141 & COUNTER_FIELD_DDE;
141 142
142 143 CCR_setValue(cacheControlRegister);
143 144 }
144 145
145 146 //*******************************************
146 147 // ASR16 Register protection control register
147 148
148 149 static void ASR16_resetRegisterProtectionControlRegister()
149 150 {
150 151 *asr16Ptr = 0x00;
151 152 }
152 153
153 154 void ASR16_get_FPRF_IURF_ErrorCounters( unsigned int* fprfErrorCounter, unsigned int* iurfErrorCounter)
154 155 {
155 156 /** This function is used to retrieve the integer unit register file error counter and the floating point unit
156 157 * register file error counter
157 158 *
158 159 * @return void
159 160 *
160 161 * [29:27] FP RF error counter - Number of detected parity errors in the FP register file.
161 162 * [13:11] IU RF error counter - Number of detected parity errors in the IU register file.
162 163 *
163 164 */
164 165
165 166 unsigned int asr16;
166 167
167 168 asr16 = *asr16Ptr;
168 169 *fprfErrorCounter = ( asr16 & COUNTER_FIELD_FPRF ) >> POS_FPRF;
169 170 *iurfErrorCounter = ( asr16 & COUNTER_FIELD_IURF ) >> POS_IURF;
170 171
171 172 // reset the counter to 0
172 173 asr16 = asr16
173 174 & COUNTER_MASK_FPRF
174 175 & COUNTER_FIELD_IURF;
175 176
176 177 *asr16Ptr = asr16;
177 178 }
178 179
179 180 static void faultTolerantScheme()
180 181 {
181 182 // [20:19] FT scheme (FT) - “00” = no FT, “01” = 4-bit checking implemented
182 183 unsigned int cacheControlRegister;
183 184 unsigned int *plugAndPlayRegister;
184 185 unsigned int vendorId;
185 186 unsigned int deviceId;
186 187
187 188 plugAndPlayRegister = (unsigned int*) REGS_ADDR_PLUGANDPLAY;
188 189 vendorId = ( (*plugAndPlayRegister) & 0xff000000 ) >> 24;
189 190 deviceId = ( (*plugAndPlayRegister) & 0x00fff000 ) >> 12;
190 191
191 192 cacheControlRegister = CCR_getValue();
192 193
193 194 if( (vendorId == VENDORID_GAISLER) & (deviceId ==DEVICEID_LEON3FT) )
194 195 {
195 196 PRINTF("in faultTolerantScheme *** Leon3FT detected\n");
196 197 PRINTF2(" *** vendorID = 0x%x, deviceId = 0x%x\n", vendorId, deviceId);
197 198 PRINTF1("ASR16 IU RF protection, bit 0 (IDI) is: 0x%x (0 => protection enabled)\n",
198 199 (*asr16Ptr >> POS_IDI) & 1);
199 200 PRINTF1("ASR16 FP RF protection, bit 16 (FDI) is: 0x%x (0 => protection enabled)\n",
200 201 (*asr16Ptr >> POS_FDI) & 1);
201 202 PRINTF1("ASR16 IU FT ID bits [15:14] is: 0x%x (2 => 8-bit parity without restart)\n",
202 203 (*asr16Ptr >> POS_IUFTID) & 0x3);
203 204 PRINTF1("ASR16 FP FT ID bits [31:30] is: 0x%x (1 => 4-bit parity with restart)\n",
204 205 (*asr16Ptr >> POS_FPFTID) & 0x03);
205 206 PRINTF1("CCR FT bits [20:19] are: 0x%x (1 => 4-bit parity with restart)\n",
206 207 (cacheControlRegister >> POS_FT) & 0x3 );
207 208
208 209 // CCR The FFT bits are just read, the FT scheme is set to “01” = 4-bit checking implemented by default
209 210
210 211 // ASR16 Ancillary State Register configuration (Register protection control register)
211 212 // IU RF protection is set by default, bit 0 IDI = 0
212 213 // FP RF protection is set by default, bit 16 FDI = 0
213 214 }
214 215 else
215 216 {
216 217 PRINTF("in faultTolerantScheme *** Leon3FT not detected\n");
217 218 PRINTF2(" *** vendorID = 0x%x, deviceId = 0x%x\n", vendorId, deviceId);
218 219 }
219 220 }
220 221
221 222 #endif /* GSCMEMORY_HPP_ */
@@ -1,136 +1,136
1 1 cmake_minimum_required (VERSION 3.5)
2 2 project (fsw)
3 3
4 4 include(sparc-rtems)
5 5 include(cppcheck)
6 6
7 7 include_directories("../header"
8 8 "../header/lfr_common_headers"
9 9 "../header/processing"
10 10 "../LFR_basic-parameters"
11 11 "../src")
12 12
13 13 set(SOURCES wf_handler.c
14 14 tc_handler.c
15 15 fsw_misc.c
16 16 fsw_init.c
17 17 fsw_globals.c
18 18 fsw_spacewire.c
19 19 tc_load_dump_parameters.c
20 20 tm_lfr_tc_exe.c
21 21 tc_acceptance.c
22 22 processing/fsw_processing.c
23 23 processing/avf0_prc0.c
24 24 processing/avf1_prc1.c
25 25 processing/avf2_prc2.c
26 26 lfr_cpu_usage_report.c
27 27 ${LFR_BP_SRC}
28 28 ../header/wf_handler.h
29 29 ../header/tc_handler.h
30 30 ../header/grlib_regs.h
31 31 ../header/fsw_misc.h
32 32 ../header/fsw_init.h
33 33 ../header/fsw_spacewire.h
34 34 ../header/tc_load_dump_parameters.h
35 35 ../header/tm_lfr_tc_exe.h
36 36 ../header/tc_acceptance.h
37 37 ../header/processing/fsw_processing.h
38 38 ../header/processing/avf0_prc0.h
39 39 ../header/processing/avf1_prc1.h
40 40 ../header/processing/avf2_prc2.h
41 41 ../header/fsw_params_wf_handler.h
42 42 ../header/lfr_cpu_usage_report.h
43 43 ../header/lfr_common_headers/ccsds_types.h
44 44 ../header/lfr_common_headers/fsw_params.h
45 45 ../header/lfr_common_headers/fsw_params_nb_bytes.h
46 46 ../header/lfr_common_headers/fsw_params_processing.h
47 47 ../header/lfr_common_headers/tm_byte_positions.h
48 48 ../LFR_basic-parameters/basic_parameters.h
49 49 ../LFR_basic-parameters/basic_parameters_params.h
50 50 ../header/GscMemoryLPP.hpp
51 51 )
52 52
53 53
54 54 option(FSW_verbose "Enable verbose LFR" OFF)
55 55 option(FSW_boot_messages "Enable LFR boot messages" OFF)
56 56 option(FSW_debug_messages "Enable LFR debug messages" OFF)
57 57 option(FSW_cpu_usage_report "Enable LFR cpu usage report" OFF)
58 58 option(FSW_stack_report "Enable LFR stack report" OFF)
59 59 option(FSW_vhdl_dev "?" OFF)
60 60 option(FSW_lpp_dpu_destid "Set to debug at LPP" OFF)
61 61 option(FSW_debug_watchdog "Enable debug watchdog" OFF)
62 62 option(FSW_debug_tch "?" OFF)
63 63 option(FSW_Instrument_Scrubbing "Enable scrubbing counter" OFF)
64 64 option(FSW_Enable_Dead_Code "Enable dead code compilation, this is used to hide by default unused code." OFF)
65 65
66 66 set(SW_VERSION_N1 "3" CACHE STRING "Choose N1 FSW Version." FORCE)
67 67 set(SW_VERSION_N2 "2" CACHE STRING "Choose N2 FSW Version." FORCE)
68 68 set(SW_VERSION_N3 "0" CACHE STRING "Choose N3 FSW Version." FORCE)
69 set(SW_VERSION_N4 "22" CACHE STRING "Choose N4 FSW Version." FORCE)
69 set(SW_VERSION_N4 "23" CACHE STRING "Choose N4 FSW Version." FORCE)
70 70
71 71 if(FSW_verbose)
72 72 add_definitions(-DPRINT_MESSAGES_ON_CONSOLE)
73 73 endif()
74 74 if(FSW_boot_messages)
75 75 add_definitions(-DBOOT_MESSAGES)
76 76 endif()
77 77 if(FSW_debug_messages)
78 78 add_definitions(-DDEBUG_MESSAGES)
79 79 endif()
80 80 if(FSW_cpu_usage_report)
81 81 add_definitions(-DPRINT_TASK_STATISTICS)
82 82 endif()
83 83 if(FSW_stack_report)
84 84 add_definitions(-DPRINT_STACK_REPORT)
85 85 endif()
86 86 if(FSW_vhdl_dev)
87 87 add_definitions(-DVHDL_DEV)
88 88 endif()
89 89 if(FSW_lpp_dpu_destid)
90 90 add_definitions(-DLPP_DPU_DESTID)
91 91 endif()
92 92 if(FSW_debug_watchdog)
93 93 add_definitions(-DDEBUG_WATCHDOG)
94 94 endif()
95 95 if(FSW_debug_tch)
96 96 add_definitions(-DDEBUG_TCH)
97 97 endif()
98 98
99 99 if(FSW_Enable_Dead_Code)
100 100 add_definitions(-DENABLE_DEAD_CODE)
101 101 endif()
102 102
103 103
104 104
105 105
106 106 add_definitions(-DMSB_FIRST_TCH)
107 107
108 108 add_definitions(-DSWVERSION=-1-0)
109 109 add_definitions(-DSW_VERSION_N1=${SW_VERSION_N1})
110 110 add_definitions(-DSW_VERSION_N2=${SW_VERSION_N2})
111 111 add_definitions(-DSW_VERSION_N3=${SW_VERSION_N3})
112 112 add_definitions(-DSW_VERSION_N4=${SW_VERSION_N4})
113 113
114 114 add_executable(fsw ${SOURCES})
115 115
116 116 if(FSW_Instrument_Scrubbing)
117 117 add_definitions(-DENABLE_SCRUBBING_COUNTER)
118 118 endif()
119 119
120 120 if(Coverage)
121 121 target_link_libraries(fsw gcov)
122 122 SET_TARGET_PROPERTIES(fsw PROPERTIES COMPILE_FLAGS "-fprofile-arcs -ftest-coverage")
123 123 endif()
124 124
125 125
126 126 if(fix-b2bst)
127 127 check_b2bst(fsw ${CMAKE_CURRENT_BINARY_DIR})
128 128 endif()
129 129
130 130 if(NOT FSW_lpp_dpu_destid)
131 131 build_srec(fsw ${CMAKE_CURRENT_BINARY_DIR} "${SW_VERSION_N1}-${SW_VERSION_N2}-${SW_VERSION_N3}-${SW_VERSION_N4}")
132 132 endif()
133 133
134 134
135 135 #add_test_cppcheck(fsw STYLE UNUSED_FUNCTIONS POSSIBLE_ERROR MISSING_INCLUDE)
136 136
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