##// END OF EJS Templates
3.2.0.9...
paul -
r359:18c114e265c0 R3++ draft
parent child
Show More
@@ -1,235 +1,238
1 #ifndef GRLIB_REGS_H_INCLUDED
1 #ifndef GRLIB_REGS_H_INCLUDED
2 #define GRLIB_REGS_H_INCLUDED
2 #define GRLIB_REGS_H_INCLUDED
3
3
4 #define NB_GPTIMER 3
4 #define NB_GPTIMER 3
5
5
6 #include <stdint.h>
6 #include <stdint.h>
7
7
8 struct apbuart_regs_str{
8 struct apbuart_regs_str{
9 volatile unsigned int data;
9 volatile unsigned int data;
10 volatile unsigned int status;
10 volatile unsigned int status;
11 volatile unsigned int ctrl;
11 volatile unsigned int ctrl;
12 volatile unsigned int scaler;
12 volatile unsigned int scaler;
13 volatile unsigned int fifoDebug;
13 volatile unsigned int fifoDebug;
14 };
14 };
15
15
16 struct grgpio_regs_str{
16 struct grgpio_regs_str{
17 volatile int io_port_data_register;
17 volatile int io_port_data_register;
18 int io_port_output_register;
18 int io_port_output_register;
19 int io_port_direction_register;
19 int io_port_direction_register;
20 int interrupt_mak_register;
20 int interrupt_mak_register;
21 int interrupt_polarity_register;
21 int interrupt_polarity_register;
22 int interrupt_edge_register;
22 int interrupt_edge_register;
23 int bypass_register;
23 int bypass_register;
24 int reserved;
24 int reserved;
25 // 0x20-0x3c interrupt map register(s)
25 // 0x20-0x3c interrupt map register(s)
26 };
26 };
27
27
28 typedef struct {
28 typedef struct {
29 volatile unsigned int counter;
29 volatile unsigned int counter;
30 volatile unsigned int reload;
30 volatile unsigned int reload;
31 volatile unsigned int ctrl;
31 volatile unsigned int ctrl;
32 volatile unsigned int unused;
32 volatile unsigned int unused;
33 } timer_regs_t;
33 } timer_regs_t;
34
34
35 //*************
35 //*************
36 //*************
36 //*************
37 // GPTIMER_REGS
37 // GPTIMER_REGS
38
38
39 #define GPTIMER_CLEAR_IRQ 0x00000010 // clear pending IRQ if any
39 #define GPTIMER_CLEAR_IRQ 0x00000010 // clear pending IRQ if any
40 #define GPTIMER_LD 0x00000004 // LD load value from the reload register
40 #define GPTIMER_LD 0x00000004 // LD load value from the reload register
41 #define GPTIMER_EN 0x00000001 // EN enable the timer
41 #define GPTIMER_EN 0x00000001 // EN enable the timer
42 #define GPTIMER_EN_MASK 0xfffffffe // EN enable the timer
42 #define GPTIMER_EN_MASK 0xfffffffe // EN enable the timer
43 #define GPTIMER_RS 0x00000002 // RS restart
43 #define GPTIMER_RS 0x00000002 // RS restart
44 #define GPTIMER_IE 0x00000008 // IE interrupt enable
44 #define GPTIMER_IE 0x00000008 // IE interrupt enable
45 #define GPTIMER_IE_MASK 0xffffffef // IE interrupt enable
45 #define GPTIMER_IE_MASK 0xffffffef // IE interrupt enable
46
46
47 typedef struct {
47 typedef struct {
48 volatile unsigned int scaler_value;
48 volatile unsigned int scaler_value;
49 volatile unsigned int scaler_reload;
49 volatile unsigned int scaler_reload;
50 volatile unsigned int conf;
50 volatile unsigned int conf;
51 volatile unsigned int unused0;
51 volatile unsigned int unused0;
52 timer_regs_t timer[NB_GPTIMER];
52 timer_regs_t timer[NB_GPTIMER];
53 } gptimer_regs_t;
53 } gptimer_regs_t;
54
54
55 //*********************
55 //*********************
56 //*********************
56 //*********************
57 // TIME_MANAGEMENT_REGS
57 // TIME_MANAGEMENT_REGS
58
58
59 #define VAL_SOFTWARE_RESET 0x02 // [0010] software reset
59 #define VAL_SOFTWARE_RESET 0x02 // [0010] software reset
60 #define VAL_LFR_SYNCHRONIZED 0x80000000
60 #define VAL_LFR_SYNCHRONIZED 0x80000000
61 #define BIT_SYNCHRONIZATION 31
61 #define BIT_SYNCHRONIZATION 31
62 #define COARSE_TIME_MASK 0x7fffffff
62 #define COARSE_TIME_MASK 0x7fffffff
63 #define SYNC_BIT_MASK 0x7f
63 #define SYNC_BIT_MASK 0x7f
64 #define SYNC_BIT 0x80
64 #define SYNC_BIT 0x80
65 #define BIT_CAL_RELOAD 0x00000010
65 #define BIT_CAL_RELOAD 0x00000010
66 #define MASK_CAL_RELOAD 0xffffffef // [1110 1111]
66 #define MASK_CAL_RELOAD 0xffffffef // [1110 1111]
67 #define BIT_CAL_ENABLE 0x00000040
67 #define BIT_CAL_ENABLE 0x00000040
68 #define MASK_CAL_ENABLE 0xffffffbf // [1011 1111]
68 #define MASK_CAL_ENABLE 0xffffffbf // [1011 1111]
69 #define BIT_SET_INTERLEAVED 0x00000020 // [0010 0000]
69 #define BIT_SET_INTERLEAVED 0x00000020 // [0010 0000]
70 #define MASK_SET_INTERLEAVED 0xffffffdf // [1101 1111]
70 #define MASK_SET_INTERLEAVED 0xffffffdf // [1101 1111]
71 #define BIT_SOFT_RESET 0x00000004 // [0100]
71 #define BIT_SOFT_RESET 0x00000004 // [0100]
72 #define MASK_SOFT_RESET 0xfffffffb // [1011]
72 #define MASK_SOFT_RESET 0xfffffffb // [1011]
73
73
74 typedef struct {
74 typedef struct {
75 volatile int ctrl; // bit 0 forces the load of the coarse_time_load value and resets the fine_time
75 volatile int ctrl; // bit 0 forces the load of the coarse_time_load value and resets the fine_time
76 // bit 1 is the soft reset for the time management module
76 // bit 1 is the soft reset for the time management module
77 // bit 2 is the soft reset for the waveform picker and the spectral matrix modules, set to 1 after HW reset
77 // bit 2 is the soft reset for the waveform picker and the spectral matrix modules, set to 1 after HW reset
78 volatile int coarse_time_load;
78 volatile int coarse_time_load;
79 volatile int coarse_time;
79 volatile int coarse_time;
80 volatile int fine_time;
80 volatile int fine_time;
81 // TEMPERATURES
81 // TEMPERATURES
82 volatile int temp_pcb; // SEL1 = 0 SEL0 = 0
82 volatile int temp_pcb; // SEL1 = 0 SEL0 = 0
83 volatile int temp_fpga; // SEL1 = 0 SEL0 = 1
83 volatile int temp_fpga; // SEL1 = 0 SEL0 = 1
84 volatile int temp_scm; // SEL1 = 1 SEL0 = 0
84 volatile int temp_scm; // SEL1 = 1 SEL0 = 0
85 // CALIBRATION
85 // CALIBRATION
86 volatile unsigned int calDACCtrl;
86 volatile unsigned int calDACCtrl;
87 volatile unsigned int calPrescaler;
87 volatile unsigned int calPrescaler;
88 volatile unsigned int calDivisor;
88 volatile unsigned int calDivisor;
89 volatile unsigned int calDataPtr;
89 volatile unsigned int calDataPtr;
90 volatile unsigned int calData;
90 volatile unsigned int calData;
91 } time_management_regs_t;
91 } time_management_regs_t;
92
92
93 //*********************
93 //*********************
94 //*********************
94 //*********************
95 // WAVEFORM_PICKER_REGS
95 // WAVEFORM_PICKER_REGS
96
96
97 #define BITS_WFP_STATUS_F3 0xc0 // [1100 0000] check the f3 full bits
97 #define BITS_WFP_STATUS_F3 0xc0 // [1100 0000] check the f3 full bits
98 #define BIT_WFP_BUF_F3_0 0x40 // [0100 0000] f3 buffer 0 is full
98 #define BIT_WFP_BUF_F3_0 0x40 // [0100 0000] f3 buffer 0 is full
99 #define BIT_WFP_BUF_F3_1 0x80 // [1000 0000] f3 buffer 1 is full
99 #define BIT_WFP_BUF_F3_1 0x80 // [1000 0000] f3 buffer 1 is full
100 #define RST_WFP_F3_0 0x00008840 // [1000 1000 0100 0000]
100 #define RST_WFP_F3_0 0x00008840 // [1000 1000 0100 0000]
101 #define RST_WFP_F3_1 0x00008880 // [1000 1000 1000 0000]
101 #define RST_WFP_F3_1 0x00008880 // [1000 1000 1000 0000]
102
102
103 #define BITS_WFP_STATUS_F2 0x30 // [0011 0000] get the status bits for f2
103 #define BITS_WFP_STATUS_F2 0x30 // [0011 0000] get the status bits for f2
104 #define SHIFT_WFP_STATUS_F2 4
104 #define SHIFT_WFP_STATUS_F2 4
105 #define BIT_WFP_BUF_F2_0 0x10 // [0001 0000] f2 buffer 0 is full
105 #define BIT_WFP_BUF_F2_0 0x10 // [0001 0000] f2 buffer 0 is full
106 #define BIT_WFP_BUF_F2_1 0x20 // [0010 0000] f2 buffer 1 is full
106 #define BIT_WFP_BUF_F2_1 0x20 // [0010 0000] f2 buffer 1 is full
107 #define RST_WFP_F2_0 0x00004410 // [0100 0100 0001 0000]
107 #define RST_WFP_F2_0 0x00004410 // [0100 0100 0001 0000]
108 #define RST_WFP_F2_1 0x00004420 // [0100 0100 0010 0000]
108 #define RST_WFP_F2_1 0x00004420 // [0100 0100 0010 0000]
109
109
110 #define BITS_WFP_STATUS_F1 0x0c // [0000 1100] check the f1 full bits
110 #define BITS_WFP_STATUS_F1 0x0c // [0000 1100] check the f1 full bits
111 #define BIT_WFP_BUF_F1_0 0x04 // [0000 0100] f1 buffer 0 is full
111 #define BIT_WFP_BUF_F1_0 0x04 // [0000 0100] f1 buffer 0 is full
112 #define BIT_WFP_BUF_F1_1 0x08 // [0000 1000] f1 buffer 1 is full
112 #define BIT_WFP_BUF_F1_1 0x08 // [0000 1000] f1 buffer 1 is full
113 #define RST_WFP_F1_0 0x00002204 // [0010 0010 0000 0100] f1 bits = 0
113 #define RST_WFP_F1_0 0x00002204 // [0010 0010 0000 0100] f1 bits = 0
114 #define RST_WFP_F1_1 0x00002208 // [0010 0010 0000 1000] f1 bits = 0
114 #define RST_WFP_F1_1 0x00002208 // [0010 0010 0000 1000] f1 bits = 0
115
115
116 #define BITS_WFP_STATUS_F0 0x03 // [0000 0011] check the f0 full bits
116 #define BITS_WFP_STATUS_F0 0x03 // [0000 0011] check the f0 full bits
117 #define RST_WFP_F0_0 0x00001101 // [0001 0001 0000 0001]
117 #define RST_WFP_F0_0 0x00001101 // [0001 0001 0000 0001]
118 #define RST_WFP_F0_1 0x00001102 // [0001 0001 0000 0010]
118 #define RST_WFP_F0_1 0x00001102 // [0001 0001 0000 0010]
119
119
120 #define BIT_WFP_BUFFER_0 0x01
120 #define BIT_WFP_BUFFER_0 0x01
121 #define BIT_WFP_BUFFER_1 0x02
121 #define BIT_WFP_BUFFER_1 0x02
122
122
123 #define RST_BITS_RUN_BURST_EN 0x80 // [1000 0000] burst f2, f1, f0 enable f3, f2, f1, f0
123 #define RST_BITS_RUN_BURST_EN 0x80 // [1000 0000] burst f2, f1, f0 enable f3, f2, f1, f0
124 #define BITS_WFP_ENABLE_ALL 0x0f // [0000 1111] enable f3, f2, f1, f0
124 #define BITS_WFP_ENABLE_ALL 0x0f // [0000 1111] enable f3, f2, f1, f0
125 #define BITS_WFP_ENABLE_BURST 0x0c // [0000 1100] enable f3, f2
125 #define BITS_WFP_ENABLE_BURST 0x0c // [0000 1100] enable f3, f2
126 #define RUN_BURST_ENABLE_SBM2 0x60 // [0110 0000] enable f2 and f1 burst
126 #define RUN_BURST_ENABLE_SBM2 0x60 // [0110 0000] enable f2 and f1 burst
127 #define RUN_BURST_ENABLE_BURST 0x40 // [0100 0000] f2 burst enabled
127 #define RUN_BURST_ENABLE_BURST 0x40 // [0100 0000] f2 burst enabled
128
128
129 #define DFLT_WFP_NB_DATA_BY_BUFFER 0xa7f // 0x30 *** 2688 - 1 => nb samples -1
129 #define DFLT_WFP_NB_DATA_BY_BUFFER 0xa7f // 0x30 *** 2688 - 1 => nb samples -1
130 #define DFLT_WFP_SNAPSHOT_PARAM 0xa80 // 0x34 *** 2688 => nb samples
130 #define DFLT_WFP_SNAPSHOT_PARAM 0xa80 // 0x34 *** 2688 => nb samples
131 #define DFLT_WFP_BUFFER_LENGTH 0x1f8 // buffer length in burst = 3 * 2688 / 16 = 504 = 0x1f8
131 #define DFLT_WFP_BUFFER_LENGTH 0x1f8 // buffer length in burst = 3 * 2688 / 16 = 504 = 0x1f8
132 #define DFLT_WFP_DELTA_F0_2 0x30 // 48 = 11 0000, max 7 bits
132 #define DFLT_WFP_DELTA_F0_2 0x30 // 48 = 11 0000, max 7 bits
133
133
134 // PDB >= 0.1.28, 0x80000f54
134 // PDB >= 0.1.28, 0x80000f54
135 typedef struct{
135 typedef struct{
136 int data_shaping; // 0x00 00 *** R2 R1 R0 SP1 SP0 BW
136 int data_shaping; // 0x00 00 *** R2 R1 R0 SP1 SP0 BW
137 int run_burst_enable; // 0x04 01 *** [run *** burst f2, f1, f0 *** enable f3, f2, f1, f0 ]
137 int run_burst_enable; // 0x04 01 *** [run *** burst f2, f1, f0 *** enable f3, f2, f1, f0 ]
138 int addr_data_f0_0; // 0x08
138 int addr_data_f0_0; // 0x08
139 int addr_data_f0_1; // 0x0c
139 int addr_data_f0_1; // 0x0c
140 int addr_data_f1_0; // 0x10
140 int addr_data_f1_0; // 0x10
141 int addr_data_f1_1; // 0x14
141 int addr_data_f1_1; // 0x14
142 int addr_data_f2_0; // 0x18
142 int addr_data_f2_0; // 0x18
143 int addr_data_f2_1; // 0x1c
143 int addr_data_f2_1; // 0x1c
144 int addr_data_f3_0; // 0x20
144 int addr_data_f3_0; // 0x20
145 int addr_data_f3_1; // 0x24
145 int addr_data_f3_1; // 0x24
146 volatile int status; // 0x28
146 volatile int status; // 0x28
147 volatile int delta_snapshot; // 0x2c
147 volatile int delta_snapshot; // 0x2c
148 int delta_f0; // 0x30
148 int delta_f0; // 0x30
149 int delta_f0_2; // 0x34
149 int delta_f0_2; // 0x34
150 int delta_f1; // 0x38
150 int delta_f1; // 0x38
151 int delta_f2; // 0x3c
151 int delta_f2; // 0x3c
152 int nb_data_by_buffer; // 0x40 number of samples in a buffer = 2688
152 int nb_data_by_buffer; // 0x40 number of samples in a buffer = 2688
153 int snapshot_param; // 0x44
153 int snapshot_param; // 0x44
154 int start_date; // 0x48
154 int start_date; // 0x48
155 //
155 //
156 volatile unsigned int f0_0_coarse_time; // 0x4c
156 volatile unsigned int f0_0_coarse_time; // 0x4c
157 volatile unsigned int f0_0_fine_time; // 0x50
157 volatile unsigned int f0_0_fine_time; // 0x50
158 volatile unsigned int f0_1_coarse_time; // 0x54
158 volatile unsigned int f0_1_coarse_time; // 0x54
159 volatile unsigned int f0_1_fine_time; // 0x58
159 volatile unsigned int f0_1_fine_time; // 0x58
160 //
160 //
161 volatile unsigned int f1_0_coarse_time; // 0x5c
161 volatile unsigned int f1_0_coarse_time; // 0x5c
162 volatile unsigned int f1_0_fine_time; // 0x60
162 volatile unsigned int f1_0_fine_time; // 0x60
163 volatile unsigned int f1_1_coarse_time; // 0x64
163 volatile unsigned int f1_1_coarse_time; // 0x64
164 volatile unsigned int f1_1_fine_time; // 0x68
164 volatile unsigned int f1_1_fine_time; // 0x68
165 //
165 //
166 volatile unsigned int f2_0_coarse_time; // 0x6c
166 volatile unsigned int f2_0_coarse_time; // 0x6c
167 volatile unsigned int f2_0_fine_time; // 0x70
167 volatile unsigned int f2_0_fine_time; // 0x70
168 volatile unsigned int f2_1_coarse_time; // 0x74
168 volatile unsigned int f2_1_coarse_time; // 0x74
169 volatile unsigned int f2_1_fine_time; // 0x78
169 volatile unsigned int f2_1_fine_time; // 0x78
170 //
170 //
171 volatile unsigned int f3_0_coarse_time; // 0x7c => 0x7c + 0xf54 = 0xd0
171 volatile unsigned int f3_0_coarse_time; // 0x7c => 0x7c + 0xf54 = 0xd0
172 volatile unsigned int f3_0_fine_time; // 0x80
172 volatile unsigned int f3_0_fine_time; // 0x80
173 volatile unsigned int f3_1_coarse_time; // 0x84
173 volatile unsigned int f3_1_coarse_time; // 0x84
174 volatile unsigned int f3_1_fine_time; // 0x88
174 volatile unsigned int f3_1_fine_time; // 0x88
175 //
175 //
176 unsigned int buffer_length; // 0x8c = buffer length in burst 2688 / 16 = 168
176 unsigned int buffer_length; // 0x8c = buffer length in burst 2688 / 16 = 168
177 //
177 //
178 volatile int v; // 0x90
178 volatile int16_t v_dummy; // 0x90
179 volatile int e1; // 0x94
179 volatile int16_t v; // 0x90
180 volatile int e2; // 0x98
180 volatile int16_t e1_dummy; // 0x94
181 volatile int16_t e1; // 0x94
182 volatile int16_t e2_dummy; // 0x98
183 volatile int16_t e2; // 0x98
181 } waveform_picker_regs_0_1_18_t;
184 } waveform_picker_regs_0_1_18_t;
182
185
183 //*********************
186 //*********************
184 //*********************
187 //*********************
185 // SPECTRAL_MATRIX_REGS
188 // SPECTRAL_MATRIX_REGS
186
189
187 #define BITS_STATUS_F0 0x03 // [0011]
190 #define BITS_STATUS_F0 0x03 // [0011]
188 #define BITS_STATUS_F1 0x0c // [1100]
191 #define BITS_STATUS_F1 0x0c // [1100]
189 #define BITS_STATUS_F2 0x30 // [0011 0000]
192 #define BITS_STATUS_F2 0x30 // [0011 0000]
190 #define BITS_HK_AA_SM 0x780 // [0111 1000 0000]
193 #define BITS_HK_AA_SM 0x780 // [0111 1000 0000]
191 #define BITS_SM_ERR 0x7c0 // [0111 1100 0000]
194 #define BITS_SM_ERR 0x7c0 // [0111 1100 0000]
192 #define BITS_STATUS_REG 0x7ff // [0111 1111 1111]
195 #define BITS_STATUS_REG 0x7ff // [0111 1111 1111]
193 #define BIT_READY_0 0x1 // [01]
196 #define BIT_READY_0 0x1 // [01]
194 #define BIT_READY_1 0x2 // [10]
197 #define BIT_READY_1 0x2 // [10]
195 #define BIT_READY_0_1 0x3 // [11]
198 #define BIT_READY_0_1 0x3 // [11]
196 #define BIT_STATUS_F1_0 0x04 // [0100]
199 #define BIT_STATUS_F1_0 0x04 // [0100]
197 #define BIT_STATUS_F1_1 0x08 // [1000]
200 #define BIT_STATUS_F1_1 0x08 // [1000]
198 #define BIT_STATUS_F2_0 0x10 // [0001 0000]
201 #define BIT_STATUS_F2_0 0x10 // [0001 0000]
199 #define BIT_STATUS_F2_1 0x20 // [0010 0000]
202 #define BIT_STATUS_F2_1 0x20 // [0010 0000]
200 #define DEFAULT_MATRIX_LENGTH 0xc8 // 25 * 128 / 16 = 200 = 0xc8
203 #define DEFAULT_MATRIX_LENGTH 0xc8 // 25 * 128 / 16 = 200 = 0xc8
201 #define BIT_IRQ_ON_NEW_MATRIX 0x01
204 #define BIT_IRQ_ON_NEW_MATRIX 0x01
202 #define MASK_IRQ_ON_NEW_MATRIX 0xfffffffe
205 #define MASK_IRQ_ON_NEW_MATRIX 0xfffffffe
203 #define BIT_IRQ_ON_ERROR 0x02
206 #define BIT_IRQ_ON_ERROR 0x02
204 #define MASK_IRQ_ON_ERROR 0xfffffffd
207 #define MASK_IRQ_ON_ERROR 0xfffffffd
205
208
206 typedef struct {
209 typedef struct {
207 volatile int config; // 0x00
210 volatile int config; // 0x00
208 volatile int status; // 0x04
211 volatile int status; // 0x04
209 volatile int f0_0_address; // 0x08
212 volatile int f0_0_address; // 0x08
210 volatile int f0_1_address; // 0x0C
213 volatile int f0_1_address; // 0x0C
211 //
214 //
212 volatile int f1_0_address; // 0x10
215 volatile int f1_0_address; // 0x10
213 volatile int f1_1_address; // 0x14
216 volatile int f1_1_address; // 0x14
214 volatile int f2_0_address; // 0x18
217 volatile int f2_0_address; // 0x18
215 volatile int f2_1_address; // 0x1C
218 volatile int f2_1_address; // 0x1C
216 //
219 //
217 volatile unsigned int f0_0_coarse_time; // 0x20
220 volatile unsigned int f0_0_coarse_time; // 0x20
218 volatile unsigned int f0_0_fine_time; // 0x24
221 volatile unsigned int f0_0_fine_time; // 0x24
219 volatile unsigned int f0_1_coarse_time; // 0x28
222 volatile unsigned int f0_1_coarse_time; // 0x28
220 volatile unsigned int f0_1_fine_time; // 0x2C
223 volatile unsigned int f0_1_fine_time; // 0x2C
221 //
224 //
222 volatile unsigned int f1_0_coarse_time; // 0x30
225 volatile unsigned int f1_0_coarse_time; // 0x30
223 volatile unsigned int f1_0_fine_time; // 0x34
226 volatile unsigned int f1_0_fine_time; // 0x34
224 volatile unsigned int f1_1_coarse_time; // 0x38
227 volatile unsigned int f1_1_coarse_time; // 0x38
225 volatile unsigned int f1_1_fine_time; // 0x3C
228 volatile unsigned int f1_1_fine_time; // 0x3C
226 //
229 //
227 volatile unsigned int f2_0_coarse_time; // 0x40
230 volatile unsigned int f2_0_coarse_time; // 0x40
228 volatile unsigned int f2_0_fine_time; // 0x44
231 volatile unsigned int f2_0_fine_time; // 0x44
229 volatile unsigned int f2_1_coarse_time; // 0x48
232 volatile unsigned int f2_1_coarse_time; // 0x48
230 volatile unsigned int f2_1_fine_time; // 0x4C
233 volatile unsigned int f2_1_fine_time; // 0x4C
231 //
234 //
232 unsigned int matrix_length; // 0x50, length of a spectral matrix in burst 3200 / 16 = 200 = 0xc8
235 unsigned int matrix_length; // 0x50, length of a spectral matrix in burst 3200 / 16 = 200 = 0xc8
233 } spectral_matrix_regs_t;
236 } spectral_matrix_regs_t;
234
237
235 #endif // GRLIB_REGS_H_INCLUDED
238 #endif // GRLIB_REGS_H_INCLUDED
@@ -1,9 +1,10
1 set(CMAKE_SYSTEM_NAME rtems)
1 set(CMAKE_SYSTEM_NAME rtems)
2
2
3 set(CMAKE_C_COMPILER /opt/rtems-4.10/bin/sparc-rtems-gcc)
3 set(CMAKE_C_COMPILER /opt/rtems-4.10/bin/sparc-rtems-gcc)
4 set(CMAKE_CXX_COMPILER /opt/rtems-4.10/bin/sparc-rtems-g++)
4 set(CMAKE_CXX_COMPILER /opt/rtems-4.10/bin/sparc-rtems-g++)
5 set(CMAKE_LINKER /opt/rtems-4.10/bin/sparc-rtems-g++)
5 set(CMAKE_LINKER /opt/rtems-4.10/bin/sparc-rtems-g++)
6 SET(CMAKE_EXE_LINKER_FLAGS "-static")
6 SET(CMAKE_EXE_LINKER_FLAGS "-static")
7 set(CMAKE_C_FLAGS_RELEASE "-O3 -mfix-b2bst")
7 set(CMAKE_C_FLAGS_RELEASE "-O3 -mfix-b2bst")
8 #set(CMAKE_C_FLAGS_RELEASE "-O3")
8 set(CMAKE_C_LINK_EXECUTABLE "<CMAKE_LINKER> <FLAGS> <CMAKE_CXX_LINK_FLAGS> <LINK_FLAGS> <OBJECTS> -o <TARGET> <LINK_LIBRARIES>")
9 set(CMAKE_C_LINK_EXECUTABLE "<CMAKE_LINKER> <FLAGS> <CMAKE_CXX_LINK_FLAGS> <LINK_FLAGS> <OBJECTS> -o <TARGET> <LINK_LIBRARIES>")
9 include_directories("/opt/rtems-4.10/sparc-rtems/leon3/lib/include")
10 include_directories("/opt/rtems-4.10/sparc-rtems/leon3/lib/include")
@@ -1,107 +1,107
1 cmake_minimum_required (VERSION 2.6)
1 cmake_minimum_required (VERSION 2.6)
2 project (fsw)
2 project (fsw)
3
3
4 include(sparc-rtems)
4 include(sparc-rtems)
5 include(cppcheck)
5 include(cppcheck)
6
6
7 include_directories("../header"
7 include_directories("../header"
8 "../header/lfr_common_headers"
8 "../header/lfr_common_headers"
9 "../header/processing"
9 "../header/processing"
10 "../LFR_basic-parameters"
10 "../LFR_basic-parameters"
11 "../src")
11 "../src")
12
12
13 set(SOURCES wf_handler.c
13 set(SOURCES wf_handler.c
14 tc_handler.c
14 tc_handler.c
15 fsw_misc.c
15 fsw_misc.c
16 fsw_init.c
16 fsw_init.c
17 fsw_globals.c
17 fsw_globals.c
18 fsw_spacewire.c
18 fsw_spacewire.c
19 tc_load_dump_parameters.c
19 tc_load_dump_parameters.c
20 tm_lfr_tc_exe.c
20 tm_lfr_tc_exe.c
21 tc_acceptance.c
21 tc_acceptance.c
22 processing/fsw_processing.c
22 processing/fsw_processing.c
23 processing/avf0_prc0.c
23 processing/avf0_prc0.c
24 processing/avf1_prc1.c
24 processing/avf1_prc1.c
25 processing/avf2_prc2.c
25 processing/avf2_prc2.c
26 lfr_cpu_usage_report.c
26 lfr_cpu_usage_report.c
27 ${LFR_BP_SRC}
27 ${LFR_BP_SRC}
28 ../header/wf_handler.h
28 ../header/wf_handler.h
29 ../header/tc_handler.h
29 ../header/tc_handler.h
30 ../header/grlib_regs.h
30 ../header/grlib_regs.h
31 ../header/fsw_misc.h
31 ../header/fsw_misc.h
32 ../header/fsw_init.h
32 ../header/fsw_init.h
33 ../header/fsw_spacewire.h
33 ../header/fsw_spacewire.h
34 ../header/tc_load_dump_parameters.h
34 ../header/tc_load_dump_parameters.h
35 ../header/tm_lfr_tc_exe.h
35 ../header/tm_lfr_tc_exe.h
36 ../header/tc_acceptance.h
36 ../header/tc_acceptance.h
37 ../header/processing/fsw_processing.h
37 ../header/processing/fsw_processing.h
38 ../header/processing/avf0_prc0.h
38 ../header/processing/avf0_prc0.h
39 ../header/processing/avf1_prc1.h
39 ../header/processing/avf1_prc1.h
40 ../header/processing/avf2_prc2.h
40 ../header/processing/avf2_prc2.h
41 ../header/fsw_params_wf_handler.h
41 ../header/fsw_params_wf_handler.h
42 ../header/lfr_cpu_usage_report.h
42 ../header/lfr_cpu_usage_report.h
43 ../header/lfr_common_headers/ccsds_types.h
43 ../header/lfr_common_headers/ccsds_types.h
44 ../header/lfr_common_headers/fsw_params.h
44 ../header/lfr_common_headers/fsw_params.h
45 ../header/lfr_common_headers/fsw_params_nb_bytes.h
45 ../header/lfr_common_headers/fsw_params_nb_bytes.h
46 ../header/lfr_common_headers/fsw_params_processing.h
46 ../header/lfr_common_headers/fsw_params_processing.h
47 ../header/lfr_common_headers/tm_byte_positions.h
47 ../header/lfr_common_headers/tm_byte_positions.h
48 ../LFR_basic-parameters/basic_parameters.h
48 ../LFR_basic-parameters/basic_parameters.h
49 ../LFR_basic-parameters/basic_parameters_params.h
49 ../LFR_basic-parameters/basic_parameters_params.h
50 ../header/GscMemoryLPP.hpp
50 ../header/GscMemoryLPP.hpp
51 )
51 )
52
52
53
53
54 option(FSW_verbose "Enable verbose LFR" OFF)
54 option(FSW_verbose "Enable verbose LFR" OFF)
55 option(FSW_boot_messages "Enable LFR boot messages" OFF)
55 option(FSW_boot_messages "Enable LFR boot messages" OFF)
56 option(FSW_debug_messages "Enable LFR debug messages" OFF)
56 option(FSW_debug_messages "Enable LFR debug messages" OFF)
57 option(FSW_cpu_usage_report "Enable LFR cpu usage report" OFF)
57 option(FSW_cpu_usage_report "Enable LFR cpu usage report" OFF)
58 option(FSW_stack_report "Enable LFR stack report" OFF)
58 option(FSW_stack_report "Enable LFR stack report" OFF)
59 option(FSW_vhdl_dev "?" OFF)
59 option(FSW_vhdl_dev "?" OFF)
60 option(FSW_lpp_dpu_destid "Set to debug at LPP" ON)
60 option(FSW_lpp_dpu_destid "Set to debug at LPP" ON)
61 option(FSW_debug_watchdog "Enable debug watchdog" OFF)
61 option(FSW_debug_watchdog "Enable debug watchdog" OFF)
62 option(FSW_debug_tch "?" OFF)
62 option(FSW_debug_tch "?" OFF)
63
63
64 set(SW_VERSION_N1 "3" CACHE STRING "Choose N1 FSW Version." FORCE)
64 set(SW_VERSION_N1 "3" CACHE STRING "Choose N1 FSW Version." FORCE)
65 set(SW_VERSION_N2 "2" CACHE STRING "Choose N2 FSW Version." FORCE)
65 set(SW_VERSION_N2 "2" CACHE STRING "Choose N2 FSW Version." FORCE)
66 set(SW_VERSION_N3 "0" CACHE STRING "Choose N3 FSW Version." FORCE)
66 set(SW_VERSION_N3 "0" CACHE STRING "Choose N3 FSW Version." FORCE)
67 set(SW_VERSION_N4 "8" CACHE STRING "Choose N4 FSW Version." FORCE)
67 set(SW_VERSION_N4 "9" CACHE STRING "Choose N4 FSW Version." FORCE)
68
68
69 if(FSW_verbose)
69 if(FSW_verbose)
70 add_definitions(-DPRINT_MESSAGES_ON_CONSOLE)
70 add_definitions(-DPRINT_MESSAGES_ON_CONSOLE)
71 endif()
71 endif()
72 if(FSW_boot_messages)
72 if(FSW_boot_messages)
73 add_definitions(-DBOOT_MESSAGES)
73 add_definitions(-DBOOT_MESSAGES)
74 endif()
74 endif()
75 if(FSW_debug_messages)
75 if(FSW_debug_messages)
76 add_definitions(-DDEBUG_MESSAGES)
76 add_definitions(-DDEBUG_MESSAGES)
77 endif()
77 endif()
78 if(FSW_cpu_usage_report)
78 if(FSW_cpu_usage_report)
79 add_definitions(-DPRINT_TASK_STATISTICS)
79 add_definitions(-DPRINT_TASK_STATISTICS)
80 endif()
80 endif()
81 if(FSW_stack_report)
81 if(FSW_stack_report)
82 add_definitions(-DPRINT_STACK_REPORT)
82 add_definitions(-DPRINT_STACK_REPORT)
83 endif()
83 endif()
84 if(FSW_vhdl_dev)
84 if(FSW_vhdl_dev)
85 add_definitions(-DVHDL_DEV)
85 add_definitions(-DVHDL_DEV)
86 endif()
86 endif()
87 if(FSW_lpp_dpu_destid)
87 if(FSW_lpp_dpu_destid)
88 add_definitions(-DLPP_DPU_DESTID)
88 add_definitions(-DLPP_DPU_DESTID)
89 endif()
89 endif()
90 if(FSW_debug_watchdog)
90 if(FSW_debug_watchdog)
91 add_definitions(-DDEBUG_WATCHDOG)
91 add_definitions(-DDEBUG_WATCHDOG)
92 endif()
92 endif()
93 if(FSW_debug_tch)
93 if(FSW_debug_tch)
94 add_definitions(-DDEBUG_TCH)
94 add_definitions(-DDEBUG_TCH)
95 endif()
95 endif()
96
96
97 add_definitions(-DMSB_FIRST_TCH)
97 add_definitions(-DMSB_FIRST_TCH)
98
98
99 add_definitions(-DSWVERSION=-1-0)
99 add_definitions(-DSWVERSION=-1-0)
100 add_definitions(-DSW_VERSION_N1=${SW_VERSION_N1})
100 add_definitions(-DSW_VERSION_N1=${SW_VERSION_N1})
101 add_definitions(-DSW_VERSION_N2=${SW_VERSION_N2})
101 add_definitions(-DSW_VERSION_N2=${SW_VERSION_N2})
102 add_definitions(-DSW_VERSION_N3=${SW_VERSION_N3})
102 add_definitions(-DSW_VERSION_N3=${SW_VERSION_N3})
103 add_definitions(-DSW_VERSION_N4=${SW_VERSION_N4})
103 add_definitions(-DSW_VERSION_N4=${SW_VERSION_N4})
104
104
105 add_executable(fsw ${SOURCES})
105 add_executable(fsw ${SOURCES})
106 add_test_cppcheck(fsw STYLE UNUSED_FUNCTIONS POSSIBLE_ERROR MISSING_INCLUDE)
106 add_test_cppcheck(fsw STYLE UNUSED_FUNCTIONS POSSIBLE_ERROR MISSING_INCLUDE)
107
107
@@ -1,1040 +1,1023
1 /** General usage functions and RTEMS tasks.
1 /** General usage functions and RTEMS tasks.
2 *
2 *
3 * @file
3 * @file
4 * @author P. LEROY
4 * @author P. LEROY
5 *
5 *
6 */
6 */
7
7
8 #include "fsw_misc.h"
8 #include "fsw_misc.h"
9
9
10 int16_t hk_lfr_sc_v_f3_as_int16 = 0;
10 int16_t hk_lfr_sc_v_f3_as_int16 = 0;
11 int16_t hk_lfr_sc_e1_f3_as_int16 = 0;
11 int16_t hk_lfr_sc_e1_f3_as_int16 = 0;
12 int16_t hk_lfr_sc_e2_f3_as_int16 = 0;
12 int16_t hk_lfr_sc_e2_f3_as_int16 = 0;
13
13
14 void timer_configure(unsigned char timer, unsigned int clock_divider,
14 void timer_configure(unsigned char timer, unsigned int clock_divider,
15 unsigned char interrupt_level, rtems_isr (*timer_isr)() )
15 unsigned char interrupt_level, rtems_isr (*timer_isr)() )
16 {
16 {
17 /** This function configures a GPTIMER timer instantiated in the VHDL design.
17 /** This function configures a GPTIMER timer instantiated in the VHDL design.
18 *
18 *
19 * @param gptimer_regs points to the APB registers of the GPTIMER IP core.
19 * @param gptimer_regs points to the APB registers of the GPTIMER IP core.
20 * @param timer is the number of the timer in the IP core (several timers can be instantiated).
20 * @param timer is the number of the timer in the IP core (several timers can be instantiated).
21 * @param clock_divider is the divider of the 1 MHz clock that will be configured.
21 * @param clock_divider is the divider of the 1 MHz clock that will be configured.
22 * @param interrupt_level is the interrupt level that the timer drives.
22 * @param interrupt_level is the interrupt level that the timer drives.
23 * @param timer_isr is the interrupt subroutine that will be attached to the IRQ driven by the timer.
23 * @param timer_isr is the interrupt subroutine that will be attached to the IRQ driven by the timer.
24 *
24 *
25 * Interrupt levels are described in the SPARC documentation sparcv8.pdf p.76
25 * Interrupt levels are described in the SPARC documentation sparcv8.pdf p.76
26 *
26 *
27 */
27 */
28
28
29 rtems_status_code status;
29 rtems_status_code status;
30 rtems_isr_entry old_isr_handler;
30 rtems_isr_entry old_isr_handler;
31
31
32 old_isr_handler = NULL;
32 old_isr_handler = NULL;
33
33
34 gptimer_regs->timer[timer].ctrl = INIT_CHAR; // reset the control register
34 gptimer_regs->timer[timer].ctrl = INIT_CHAR; // reset the control register
35
35
36 status = rtems_interrupt_catch( timer_isr, interrupt_level, &old_isr_handler) ; // see sparcv8.pdf p.76 for interrupt levels
36 status = rtems_interrupt_catch( timer_isr, interrupt_level, &old_isr_handler) ; // see sparcv8.pdf p.76 for interrupt levels
37 if (status!=RTEMS_SUCCESSFUL)
37 if (status!=RTEMS_SUCCESSFUL)
38 {
38 {
39 PRINTF("in configure_timer *** ERR rtems_interrupt_catch\n")
39 PRINTF("in configure_timer *** ERR rtems_interrupt_catch\n")
40 }
40 }
41
41
42 timer_set_clock_divider( timer, clock_divider);
42 timer_set_clock_divider( timer, clock_divider);
43 }
43 }
44
44
45 void timer_start(unsigned char timer)
45 void timer_start(unsigned char timer)
46 {
46 {
47 /** This function starts a GPTIMER timer.
47 /** This function starts a GPTIMER timer.
48 *
48 *
49 * @param gptimer_regs points to the APB registers of the GPTIMER IP core.
49 * @param gptimer_regs points to the APB registers of the GPTIMER IP core.
50 * @param timer is the number of the timer in the IP core (several timers can be instantiated).
50 * @param timer is the number of the timer in the IP core (several timers can be instantiated).
51 *
51 *
52 */
52 */
53
53
54 gptimer_regs->timer[timer].ctrl = gptimer_regs->timer[timer].ctrl | GPTIMER_CLEAR_IRQ;
54 gptimer_regs->timer[timer].ctrl = gptimer_regs->timer[timer].ctrl | GPTIMER_CLEAR_IRQ;
55 gptimer_regs->timer[timer].ctrl = gptimer_regs->timer[timer].ctrl | GPTIMER_LD;
55 gptimer_regs->timer[timer].ctrl = gptimer_regs->timer[timer].ctrl | GPTIMER_LD;
56 gptimer_regs->timer[timer].ctrl = gptimer_regs->timer[timer].ctrl | GPTIMER_EN;
56 gptimer_regs->timer[timer].ctrl = gptimer_regs->timer[timer].ctrl | GPTIMER_EN;
57 gptimer_regs->timer[timer].ctrl = gptimer_regs->timer[timer].ctrl | GPTIMER_RS;
57 gptimer_regs->timer[timer].ctrl = gptimer_regs->timer[timer].ctrl | GPTIMER_RS;
58 gptimer_regs->timer[timer].ctrl = gptimer_regs->timer[timer].ctrl | GPTIMER_IE;
58 gptimer_regs->timer[timer].ctrl = gptimer_regs->timer[timer].ctrl | GPTIMER_IE;
59 }
59 }
60
60
61 void timer_stop(unsigned char timer)
61 void timer_stop(unsigned char timer)
62 {
62 {
63 /** This function stops a GPTIMER timer.
63 /** This function stops a GPTIMER timer.
64 *
64 *
65 * @param gptimer_regs points to the APB registers of the GPTIMER IP core.
65 * @param gptimer_regs points to the APB registers of the GPTIMER IP core.
66 * @param timer is the number of the timer in the IP core (several timers can be instantiated).
66 * @param timer is the number of the timer in the IP core (several timers can be instantiated).
67 *
67 *
68 */
68 */
69
69
70 gptimer_regs->timer[timer].ctrl = gptimer_regs->timer[timer].ctrl & GPTIMER_EN_MASK;
70 gptimer_regs->timer[timer].ctrl = gptimer_regs->timer[timer].ctrl & GPTIMER_EN_MASK;
71 gptimer_regs->timer[timer].ctrl = gptimer_regs->timer[timer].ctrl & GPTIMER_IE_MASK;
71 gptimer_regs->timer[timer].ctrl = gptimer_regs->timer[timer].ctrl & GPTIMER_IE_MASK;
72 gptimer_regs->timer[timer].ctrl = gptimer_regs->timer[timer].ctrl | GPTIMER_CLEAR_IRQ;
72 gptimer_regs->timer[timer].ctrl = gptimer_regs->timer[timer].ctrl | GPTIMER_CLEAR_IRQ;
73 }
73 }
74
74
75 void timer_set_clock_divider(unsigned char timer, unsigned int clock_divider)
75 void timer_set_clock_divider(unsigned char timer, unsigned int clock_divider)
76 {
76 {
77 /** This function sets the clock divider of a GPTIMER timer.
77 /** This function sets the clock divider of a GPTIMER timer.
78 *
78 *
79 * @param gptimer_regs points to the APB registers of the GPTIMER IP core.
79 * @param gptimer_regs points to the APB registers of the GPTIMER IP core.
80 * @param timer is the number of the timer in the IP core (several timers can be instantiated).
80 * @param timer is the number of the timer in the IP core (several timers can be instantiated).
81 * @param clock_divider is the divider of the 1 MHz clock that will be configured.
81 * @param clock_divider is the divider of the 1 MHz clock that will be configured.
82 *
82 *
83 */
83 */
84
84
85 gptimer_regs->timer[timer].reload = clock_divider; // base clock frequency is 1 MHz
85 gptimer_regs->timer[timer].reload = clock_divider; // base clock frequency is 1 MHz
86 }
86 }
87
87
88 // WATCHDOG
88 // WATCHDOG
89
89
90 rtems_isr watchdog_isr( rtems_vector_number vector )
90 rtems_isr watchdog_isr( rtems_vector_number vector )
91 {
91 {
92 rtems_status_code status_code;
92 rtems_status_code status_code;
93
93
94 status_code = rtems_event_send( Task_id[TASKID_DUMB], RTEMS_EVENT_12 );
94 status_code = rtems_event_send( Task_id[TASKID_DUMB], RTEMS_EVENT_12 );
95
95
96 PRINTF("watchdog_isr *** this is the end, exit(0)\n");
96 PRINTF("watchdog_isr *** this is the end, exit(0)\n");
97
97
98 exit(0);
98 exit(0);
99 }
99 }
100
100
101 void watchdog_configure(void)
101 void watchdog_configure(void)
102 {
102 {
103 /** This function configure the watchdog.
103 /** This function configure the watchdog.
104 *
104 *
105 * @param gptimer_regs points to the APB registers of the GPTIMER IP core.
105 * @param gptimer_regs points to the APB registers of the GPTIMER IP core.
106 * @param timer is the number of the timer in the IP core (several timers can be instantiated).
106 * @param timer is the number of the timer in the IP core (several timers can be instantiated).
107 *
107 *
108 * The watchdog is a timer provided by the GPTIMER IP core of the GRLIB.
108 * The watchdog is a timer provided by the GPTIMER IP core of the GRLIB.
109 *
109 *
110 */
110 */
111
111
112 LEON_Mask_interrupt( IRQ_GPTIMER_WATCHDOG ); // mask gptimer/watchdog interrupt during configuration
112 LEON_Mask_interrupt( IRQ_GPTIMER_WATCHDOG ); // mask gptimer/watchdog interrupt during configuration
113
113
114 timer_configure( TIMER_WATCHDOG, CLKDIV_WATCHDOG, IRQ_SPARC_GPTIMER_WATCHDOG, watchdog_isr );
114 timer_configure( TIMER_WATCHDOG, CLKDIV_WATCHDOG, IRQ_SPARC_GPTIMER_WATCHDOG, watchdog_isr );
115
115
116 LEON_Clear_interrupt( IRQ_GPTIMER_WATCHDOG ); // clear gptimer/watchdog interrupt
116 LEON_Clear_interrupt( IRQ_GPTIMER_WATCHDOG ); // clear gptimer/watchdog interrupt
117 }
117 }
118
118
119 void watchdog_stop(void)
119 void watchdog_stop(void)
120 {
120 {
121 LEON_Mask_interrupt( IRQ_GPTIMER_WATCHDOG ); // mask gptimer/watchdog interrupt line
121 LEON_Mask_interrupt( IRQ_GPTIMER_WATCHDOG ); // mask gptimer/watchdog interrupt line
122 timer_stop( TIMER_WATCHDOG );
122 timer_stop( TIMER_WATCHDOG );
123 LEON_Clear_interrupt( IRQ_GPTIMER_WATCHDOG ); // clear gptimer/watchdog interrupt
123 LEON_Clear_interrupt( IRQ_GPTIMER_WATCHDOG ); // clear gptimer/watchdog interrupt
124 }
124 }
125
125
126 void watchdog_reload(void)
126 void watchdog_reload(void)
127 {
127 {
128 /** This function reloads the watchdog timer counter with the timer reload value.
128 /** This function reloads the watchdog timer counter with the timer reload value.
129 *
129 *
130 * @param void
130 * @param void
131 *
131 *
132 * @return void
132 * @return void
133 *
133 *
134 */
134 */
135
135
136 gptimer_regs->timer[TIMER_WATCHDOG].ctrl = gptimer_regs->timer[TIMER_WATCHDOG].ctrl | GPTIMER_LD;
136 gptimer_regs->timer[TIMER_WATCHDOG].ctrl = gptimer_regs->timer[TIMER_WATCHDOG].ctrl | GPTIMER_LD;
137 }
137 }
138
138
139 void watchdog_start(void)
139 void watchdog_start(void)
140 {
140 {
141 /** This function starts the watchdog timer.
141 /** This function starts the watchdog timer.
142 *
142 *
143 * @param gptimer_regs points to the APB registers of the GPTIMER IP core.
143 * @param gptimer_regs points to the APB registers of the GPTIMER IP core.
144 * @param timer is the number of the timer in the IP core (several timers can be instantiated).
144 * @param timer is the number of the timer in the IP core (several timers can be instantiated).
145 *
145 *
146 */
146 */
147
147
148 LEON_Clear_interrupt( IRQ_GPTIMER_WATCHDOG );
148 LEON_Clear_interrupt( IRQ_GPTIMER_WATCHDOG );
149
149
150 gptimer_regs->timer[TIMER_WATCHDOG].ctrl = gptimer_regs->timer[TIMER_WATCHDOG].ctrl | GPTIMER_CLEAR_IRQ;
150 gptimer_regs->timer[TIMER_WATCHDOG].ctrl = gptimer_regs->timer[TIMER_WATCHDOG].ctrl | GPTIMER_CLEAR_IRQ;
151 gptimer_regs->timer[TIMER_WATCHDOG].ctrl = gptimer_regs->timer[TIMER_WATCHDOG].ctrl | GPTIMER_LD;
151 gptimer_regs->timer[TIMER_WATCHDOG].ctrl = gptimer_regs->timer[TIMER_WATCHDOG].ctrl | GPTIMER_LD;
152 gptimer_regs->timer[TIMER_WATCHDOG].ctrl = gptimer_regs->timer[TIMER_WATCHDOG].ctrl | GPTIMER_EN;
152 gptimer_regs->timer[TIMER_WATCHDOG].ctrl = gptimer_regs->timer[TIMER_WATCHDOG].ctrl | GPTIMER_EN;
153 gptimer_regs->timer[TIMER_WATCHDOG].ctrl = gptimer_regs->timer[TIMER_WATCHDOG].ctrl | GPTIMER_IE;
153 gptimer_regs->timer[TIMER_WATCHDOG].ctrl = gptimer_regs->timer[TIMER_WATCHDOG].ctrl | GPTIMER_IE;
154
154
155 LEON_Unmask_interrupt( IRQ_GPTIMER_WATCHDOG );
155 LEON_Unmask_interrupt( IRQ_GPTIMER_WATCHDOG );
156
156
157 }
157 }
158
158
159 int enable_apbuart_transmitter( void ) // set the bit 1, TE Transmitter Enable to 1 in the APBUART control register
159 int enable_apbuart_transmitter( void ) // set the bit 1, TE Transmitter Enable to 1 in the APBUART control register
160 {
160 {
161 struct apbuart_regs_str *apbuart_regs = (struct apbuart_regs_str *) REGS_ADDR_APBUART;
161 struct apbuart_regs_str *apbuart_regs = (struct apbuart_regs_str *) REGS_ADDR_APBUART;
162
162
163 apbuart_regs->ctrl = APBUART_CTRL_REG_MASK_TE;
163 apbuart_regs->ctrl = APBUART_CTRL_REG_MASK_TE;
164
164
165 return 0;
165 return 0;
166 }
166 }
167
167
168 void set_apbuart_scaler_reload_register(unsigned int regs, unsigned int value)
168 void set_apbuart_scaler_reload_register(unsigned int regs, unsigned int value)
169 {
169 {
170 /** This function sets the scaler reload register of the apbuart module
170 /** This function sets the scaler reload register of the apbuart module
171 *
171 *
172 * @param regs is the address of the apbuart registers in memory
172 * @param regs is the address of the apbuart registers in memory
173 * @param value is the value that will be stored in the scaler register
173 * @param value is the value that will be stored in the scaler register
174 *
174 *
175 * The value shall be set by the software to get data on the serial interface.
175 * The value shall be set by the software to get data on the serial interface.
176 *
176 *
177 */
177 */
178
178
179 struct apbuart_regs_str *apbuart_regs = (struct apbuart_regs_str *) regs;
179 struct apbuart_regs_str *apbuart_regs = (struct apbuart_regs_str *) regs;
180
180
181 apbuart_regs->scaler = value;
181 apbuart_regs->scaler = value;
182
182
183 BOOT_PRINTF1("OK *** apbuart port scaler reload register set to 0x%x\n", value)
183 BOOT_PRINTF1("OK *** apbuart port scaler reload register set to 0x%x\n", value)
184 }
184 }
185
185
186 //************
186 //************
187 // RTEMS TASKS
187 // RTEMS TASKS
188
188
189 rtems_task load_task(rtems_task_argument argument)
189 rtems_task load_task(rtems_task_argument argument)
190 {
190 {
191 BOOT_PRINTF("in LOAD *** \n")
191 BOOT_PRINTF("in LOAD *** \n")
192
192
193 rtems_status_code status;
193 rtems_status_code status;
194 unsigned int i;
194 unsigned int i;
195 unsigned int j;
195 unsigned int j;
196 rtems_name name_watchdog_rate_monotonic; // name of the watchdog rate monotonic
196 rtems_name name_watchdog_rate_monotonic; // name of the watchdog rate monotonic
197 rtems_id watchdog_period_id; // id of the watchdog rate monotonic period
197 rtems_id watchdog_period_id; // id of the watchdog rate monotonic period
198
198
199 watchdog_period_id = RTEMS_ID_NONE;
199 watchdog_period_id = RTEMS_ID_NONE;
200
200
201 name_watchdog_rate_monotonic = rtems_build_name( 'L', 'O', 'A', 'D' );
201 name_watchdog_rate_monotonic = rtems_build_name( 'L', 'O', 'A', 'D' );
202
202
203 status = rtems_rate_monotonic_create( name_watchdog_rate_monotonic, &watchdog_period_id );
203 status = rtems_rate_monotonic_create( name_watchdog_rate_monotonic, &watchdog_period_id );
204 if( status != RTEMS_SUCCESSFUL ) {
204 if( status != RTEMS_SUCCESSFUL ) {
205 PRINTF1( "in LOAD *** rtems_rate_monotonic_create failed with status of %d\n", status )
205 PRINTF1( "in LOAD *** rtems_rate_monotonic_create failed with status of %d\n", status )
206 }
206 }
207
207
208 i = 0;
208 i = 0;
209 j = 0;
209 j = 0;
210
210
211 watchdog_configure();
211 watchdog_configure();
212
212
213 watchdog_start();
213 watchdog_start();
214
214
215 set_sy_lfr_watchdog_enabled( true );
215 set_sy_lfr_watchdog_enabled( true );
216
216
217 while(1){
217 while(1){
218 status = rtems_rate_monotonic_period( watchdog_period_id, WATCHDOG_PERIOD );
218 status = rtems_rate_monotonic_period( watchdog_period_id, WATCHDOG_PERIOD );
219 watchdog_reload();
219 watchdog_reload();
220 i = i + 1;
220 i = i + 1;
221 if ( i == WATCHDOG_LOOP_PRINTF )
221 if ( i == WATCHDOG_LOOP_PRINTF )
222 {
222 {
223 i = 0;
223 i = 0;
224 j = j + 1;
224 j = j + 1;
225 PRINTF1("%d\n", j)
225 PRINTF1("%d\n", j)
226 }
226 }
227 #ifdef DEBUG_WATCHDOG
227 #ifdef DEBUG_WATCHDOG
228 if (j == WATCHDOG_LOOP_DEBUG )
228 if (j == WATCHDOG_LOOP_DEBUG )
229 {
229 {
230 status = rtems_task_delete(RTEMS_SELF);
230 status = rtems_task_delete(RTEMS_SELF);
231 }
231 }
232 #endif
232 #endif
233 }
233 }
234 }
234 }
235
235
236 rtems_task hous_task(rtems_task_argument argument)
236 rtems_task hous_task(rtems_task_argument argument)
237 {
237 {
238 rtems_status_code status;
238 rtems_status_code status;
239 rtems_status_code spare_status;
239 rtems_status_code spare_status;
240 rtems_id queue_id;
240 rtems_id queue_id;
241 rtems_rate_monotonic_period_status period_status;
241 rtems_rate_monotonic_period_status period_status;
242 bool isSynchronized;
242 bool isSynchronized;
243
243
244 queue_id = RTEMS_ID_NONE;
244 queue_id = RTEMS_ID_NONE;
245 memset(&period_status, 0, sizeof(rtems_rate_monotonic_period_status));
245 memset(&period_status, 0, sizeof(rtems_rate_monotonic_period_status));
246 isSynchronized = false;
246 isSynchronized = false;
247
247
248 status = get_message_queue_id_send( &queue_id );
248 status = get_message_queue_id_send( &queue_id );
249 if (status != RTEMS_SUCCESSFUL)
249 if (status != RTEMS_SUCCESSFUL)
250 {
250 {
251 PRINTF1("in HOUS *** ERR get_message_queue_id_send %d\n", status)
251 PRINTF1("in HOUS *** ERR get_message_queue_id_send %d\n", status)
252 }
252 }
253
253
254 BOOT_PRINTF("in HOUS ***\n");
254 BOOT_PRINTF("in HOUS ***\n");
255
255
256 if (rtems_rate_monotonic_ident( name_hk_rate_monotonic, &HK_id) != RTEMS_SUCCESSFUL) {
256 if (rtems_rate_monotonic_ident( name_hk_rate_monotonic, &HK_id) != RTEMS_SUCCESSFUL) {
257 status = rtems_rate_monotonic_create( name_hk_rate_monotonic, &HK_id );
257 status = rtems_rate_monotonic_create( name_hk_rate_monotonic, &HK_id );
258 if( status != RTEMS_SUCCESSFUL ) {
258 if( status != RTEMS_SUCCESSFUL ) {
259 PRINTF1( "rtems_rate_monotonic_create failed with status of %d\n", status );
259 PRINTF1( "rtems_rate_monotonic_create failed with status of %d\n", status );
260 }
260 }
261 }
261 }
262
262
263 status = rtems_rate_monotonic_cancel(HK_id);
263 status = rtems_rate_monotonic_cancel(HK_id);
264 if( status != RTEMS_SUCCESSFUL ) {
264 if( status != RTEMS_SUCCESSFUL ) {
265 PRINTF1( "ERR *** in HOUS *** rtems_rate_monotonic_cancel(HK_id) ***code: %d\n", status );
265 PRINTF1( "ERR *** in HOUS *** rtems_rate_monotonic_cancel(HK_id) ***code: %d\n", status );
266 }
266 }
267 else {
267 else {
268 DEBUG_PRINTF("OK *** in HOUS *** rtems_rate_monotonic_cancel(HK_id)\n");
268 DEBUG_PRINTF("OK *** in HOUS *** rtems_rate_monotonic_cancel(HK_id)\n");
269 }
269