HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/JEANDET/LFR_FSW Files · header/GscMemoryLPP.hpp

TM_LFR_SCIENCE_NORMA_ASM_ packets modified, 32 bits values instead of 16 bits...

TM_LFR_SCIENCE_NORMA_ASM_ packets modified, 32 bits values instead of 16 bits resetCacheControlRegister function added txHdrSize changed (34 instead of 32)

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             GscMemoryLPP.hpp
        
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        paul
    
sync

              r181
            
      #ifndef GSCMEMORY_HPP_

      #define GSCMEMORY_HPP_

      #ifndef LEON3

      #define LEON3

      #endif

        paul
    
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              r187
            
      static unsigned int getCacheControlRegister(){

        paul
    
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              r181
            
      #ifdef LEON3

          unsigned int cacheControlRegister = 0;

          __asm__ __volatile__("lda [%%g0] 2, %0" : "=r"(cacheControlRegister) : );

          return cacheControlRegister;

      #endif

      }

        paul
    
2.0.2.2...

              r187
            
      static void setCacheControlRegister(unsigned int cacheControlRegister)

      {

        paul
    
sync

              r181
            
      #ifdef LEON3

          __asm__ __volatile__("sta %0, [%%g0] 2" : : "r"(cacheControlRegister));

      #endif

      }

      /**

        paul
    
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              r187
            
      * Flush the data cache and the instruction cache.

      *

      * @return

      */

        paul
    
sync

              r181
            
      static inline void flushCache() {

          asm("flush");

      }

        paul
    
TM_LFR_SCIENCE_NORMA_ASM_ packets modified, 32 bits values instead of 16 bits...

              r196
            
      static void resetCacheControlRegister() {

      #ifdef LEON3

          unsigned int cacheControlRegister;

          cacheControlRegister = 0x00;

          setCacheControlRegister(cacheControlRegister);

      #endif

      }

        paul
    
sync

              r181
            
      static void enableInstructionCache() {

      #ifdef LEON3

          unsigned int cacheControlRegister;

          cacheControlRegister = getCacheControlRegister();

          cacheControlRegister = (cacheControlRegister | 0x3);

          setCacheControlRegister(cacheControlRegister);

      #endif

      }

      static void enableDataCache() {

      #ifdef LEON3

          unsigned int cacheControlRegister;

          cacheControlRegister = getCacheControlRegister();

          cacheControlRegister = (cacheControlRegister | 0xc);

          setCacheControlRegister(cacheControlRegister);

      #endif

      }

      static void enableInstructionBurstFetch() {

      #ifdef LEON3

          unsigned int cacheControlRegister;

          cacheControlRegister = getCacheControlRegister();

          // set the bit IB to 1

          cacheControlRegister = (cacheControlRegister | 0x10000);

          setCacheControlRegister(cacheControlRegister);

      #endif

      }

      #endif /* GSCMEMORY_HPP_ */

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paul sync	r181	#ifndef GSCMEMORY_HPP_
		#define GSCMEMORY_HPP_

		#ifndef LEON3
		#define LEON3
		#endif

paul 2.0.2.2...	r187	static unsigned int getCacheControlRegister(){
paul sync	r181	#ifdef LEON3
		unsigned int cacheControlRegister = 0;
		__asm__ __volatile__("lda [%%g0] 2, %0" : "=r"(cacheControlRegister) : );
		return cacheControlRegister;
		#endif
		}

paul 2.0.2.2...	r187	static void setCacheControlRegister(unsigned int cacheControlRegister)
		{
paul sync	r181	#ifdef LEON3
		__asm__ __volatile__("sta %0, [%%g0] 2" : : "r"(cacheControlRegister));
		#endif
		}


		/**
paul 2.0.2.2...	r187	* Flush the data cache and the instruction cache.
		*
		* @return
		*/
paul sync	r181	static inline void flushCache() {
		asm("flush");
		}

paul TM_LFR_SCIENCE_NORMA_ASM_ packets modified, 32 bits values instead of 16 bits...	r196	static void resetCacheControlRegister() {
		#ifdef LEON3
		unsigned int cacheControlRegister;
		cacheControlRegister = 0x00;
		setCacheControlRegister(cacheControlRegister);
		#endif
		}
paul sync	r181
		static void enableInstructionCache() {
		#ifdef LEON3
		unsigned int cacheControlRegister;
		cacheControlRegister = getCacheControlRegister();
		cacheControlRegister = (cacheControlRegister \| 0x3);
		setCacheControlRegister(cacheControlRegister);
		#endif
		}

		static void enableDataCache() {
		#ifdef LEON3
		unsigned int cacheControlRegister;
		cacheControlRegister = getCacheControlRegister();
		cacheControlRegister = (cacheControlRegister \| 0xc);
		setCacheControlRegister(cacheControlRegister);
		#endif
		}

		static void enableInstructionBurstFetch() {
		#ifdef LEON3
		unsigned int cacheControlRegister;
		cacheControlRegister = getCacheControlRegister();
		// set the bit IB to 1
		cacheControlRegister = (cacheControlRegister \| 0x10000);
		setCacheControlRegister(cacheControlRegister);
		#endif
		}

		#endif /* GSCMEMORY_HPP_ */