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1 | 1 | <?xml version='1.0' encoding='utf-8'?> |
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2 | 2 | <soc name="Leon"> |
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3 | 3 | <peripheral vid="1" name="AHBUART" pid="7"> |
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4 | 4 | <register name="STATUS" addOffset="4"> |
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5 | 5 | <bitField size="1" name="DR" mode="1" desc="Data ready (DR) - indicates that new data has been received by the AMBA AHB master interface. Read only. Reset
value: ‘0’.
"/> |
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6 | 6 | <bitField size="1" name="TS" mode="3" desc="Transmitter shift register empty (TS) - indicates that the transmitter shift register is empty. Read only. Reset value:
‘1’"/> |
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7 | 7 | <bitField name="TH" size="1" mode="1" desc="Transmitter hold register empty (TH) - indicates that the transmitter hold register is empty. Read only. Reset value:
‘1’"/> |
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8 | 8 | <bitField name="BR" size="1" mode="1" desc="Break (BR) - indicates that a BREAKE has been received. Reset value: ‘0’"/> |
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9 | 9 | <bitField name="OV" size="1" mode="1" desc="Overflow (OV) - indicates that one or more character have been lost due to receiver overflow. Reset value: ‘0’"/> |
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10 | 10 | <bitField name="FE" size="1" mode="1" desc="Frame error (FE) - indicates that a framing error was detected. Reset value: ‘0’"/> |
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11 | 11 | </register> |
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12 | 12 | <register name="CONTROL" addOffset="8"> |
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13 | 13 | <bitField name="EN" size="1" mode="3" desc="Receiver enable (EN) - if set, enables both the transmitter and receiver. Reset value: ‘0’."/> |
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14 | 14 | <bitField name="BL" size="1" mode="3" desc="Baud rate locked (BL) - is automatically set when the baud rate is locked. Reset value: ‘0’."/> |
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15 | 15 | </register> |
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16 | 16 | <register name="SCALE" addOffset="12"> |
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17 | 17 | <bitField name="SCALER RELOAD VALUE" size="18" mode="3" desc="Baudrate scaler reload value = (((system_clk*10)/(baudrate*8))-5)/10. Reset value: “3FFFF“."/> |
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18 | 18 | </register> |
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19 | 19 | </peripheral> |
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20 | 20 | <peripheral vid="1" name="APBUART" pid="12"> |
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21 | 21 | <register name="DATA"> |
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22 | 22 | <bitField name="DATA" size="8" mode="3" desc="Receiver holding register or FIFO (read access)
Transmitter holding register or FIFO (write access)
"/> |
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23 | 23 | </register> |
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24 | 24 | <register name="STATUS" addOffset="4"> |
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25 | 25 | <bitField name="DR" size="1" mode="1" desc="Data ready (DR) - indicates that new data is available in the receiver holding register. Reset: 0
"/> |
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26 | 26 | <bitField name="TS" size="1" mode="1" desc="Transmitter shift register empty (TS) - indicates that the transmitter shift register is empty. Reset: 1"/> |
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27 | 27 | <bitField name="TE" size="1" mode="1" desc="Transmitter FIFO empty (TE) - indicates that the transmitter FIFO is empty. Reset: 1
"/> |
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28 | 28 | <bitField name="BR" size="1" mode="1" desc="Break received (BR) - indicates that a BREAK has been received. Reset: 0
"/> |
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29 | 29 | <bitField name="OV" size="1" mode="1" desc="Overrun (OV) - indicates that one or more character have been lost due to overrun. Reset: 0
"/> |
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30 | 30 | <bitField name="PE" size="1" mode="1" desc="Parity error (PE) - indicates that a parity error was detected. Reset: 0
"/> |
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31 | 31 | <bitField name="FE" size="1" mode="1" desc="Framing error (FE) - indicates that a framing error was detected. Reset: 0
"/> |
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32 | 32 | <bitField name="TH" size="1" mode="1" desc="Transmitter FIFO half-full (TH) - indicates that the FIFO is less than half-full. Reset: 0
"/> |
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33 | 33 | <bitField name="RH" size="1" mode="1" desc="Receiver FIFO half-full (RH) -indicates that at least half of the FIFO is holding data. Reset: 0
"/> |
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34 | 34 | <bitField name="TF" size="1" mode="1" desc="Transmitter FIFO full (TF) - indicates that the Transmitter FIFO is full. Reset: 0
"/> |
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35 | 35 | <bitField name="RF" size="1" mode="1" desc="Receiver FIFO full (RF) - indicates that the Receiver FIFO is full. Reset: 0
"/> |
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36 | 36 | <bitField name="TCNT" size="6" mode="1" desc="Transmitter FIFO count (TCNT) - shows the number of data frames in the transmitter FIFO. Reset: 0
"/> |
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37 | 37 | <bitField name="RCNT" size="6" mode="1" desc="Receiver FIFO count (RCNT) - shows the number of data frames in the receiver FIFO. Reset: 0"/> |
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38 | 38 | </register> |
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39 | 39 | <register name="CONTROL" addOffset="8"> |
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40 | 40 | <bitField name="RE" size="1" mode="3" desc="Receiver enable (RE) - if set, enables the receiver. Reset: 0
"/> |
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41 | 41 | <bitField name="TE" size="1" mode="3" desc="Transmitter enable (TE) - if set, enables the transmitter. Reset: 0
"/> |
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42 | 42 | <bitField name="RI" size="1" mode="3" desc="Receiver interrupt enable (RI) - if set, interrupts are generated when characters are received (see sec-
tion 15.6 for details). Not Reset.
"/> |
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43 | 43 | <bitField name="TI" size="1" mode="3" desc="Transmitter interrupt enable (TI) - if set, interrupts are generated when characters are transmitted
(see section 15.6 for details). Not Reset.
"/> |
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44 | 44 | <bitField name="PS" size="1" mode="3" desc="Parity select (PS) - selects parity polarity (0 = even parity, 1 = odd parity) (when implemented). Not
Reset.
"/> |
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45 | 45 | <bitField name="PE" size="1" mode="3" desc="Parity enable (PE) - if set, enables parity generation and checking (when implemented). Not Reset.
"/> |
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46 | 46 | <bitField name="FL" size="1" mode="3" desc="Flow control (FL) - if set, enables flow control using CTS/RTS (when implemented). Reset: 0
"/> |
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47 | 47 | <bitField name="LB" size="1" mode="3" desc="Loop back (LB) - if set, loop back mode will be enabled. Not Reset.
"/> |
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48 | 48 | <bitField name="EC" size="1" mode="3" desc="External Clock (EC) - if set, the UART scaler will be clocked by UARTI.EXTCLK. Reset: 0
"/> |
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49 | 49 | <bitField name="TF" size="1" mode="3" desc="Transmitter FIFO interrupt enable (TF) - when set, Transmitter FIFO level interrupts are enabled.
Not Reset.
"/> |
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50 | 50 | <bitField name="RF" size="1" mode="3" desc="Receiver FIFO interrupt enable (RF) - when set, Receiver FIFO level interrupts are enabled. Not
Reset.
"/> |
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51 | 51 | <bitField name="DB" size="1" mode="3" desc="FIFO debug mode enable (DB) - when set, it is possible to read and write the FIFO debug register.
Not Reset.
"/> |
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52 | 52 | <bitField name="BI" size="1" mode="3" desc="Break interrupt enable (BI) - When set, an interrupt will be generated each time a break character is
received. See section 16.6 for more details. Not Reset.
"/> |
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53 | 53 | <bitField name="DI" size="1" mode="3" desc="Delayed interrupt enable (DI) - When set, delayed receiver interrupts will be enabled and an inter-
rupt will only be generated for received characters after a delay of 4 character times + 4 bits if no
new character has been received during that interval. This is only applicable if receiver interrupt
enable is set.
"/> |
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54 | 54 | <bitField name="SI" size="1" mode="3" desc="Transmitter shift register empty interrupt enable (SI) - When set, an interrupt will be generated when
the transmitter shift register becomes empty.
"/> |
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55 | 55 | <bitField name="FA" size="1" mode="3" desc="FIFOs available (FA) - Set to 1 when receiver and transmitter FIFOs are available. When 0, only
holding register are available. Read only.
"/> |
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56 | 56 | </register> |
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57 | 57 | <register name="SCALE" addOffset="12"> |
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58 | 58 | <bitField name="SCALER RELOAD VALUE" size="31" mode="3" desc="sbits-1:0 Scaler reload value"/> |
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59 | 59 | </register> |
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60 | 60 | <register name="FIFO Debug" addOffset="16"> |
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61 | 61 | <bitField name="DATA" size="8" mode="3" desc="Transmitter holding register or FIFO (read access)
Receiver holding register or FIFO (write access)
"/> |
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62 | 62 | </register> |
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63 | 63 | </peripheral> |
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64 | 64 | <peripheral vid="1" name="LEON3" pid="3"/> |
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65 | 65 | <peripheral vid="1" name="DSU3" pid="4"> |
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66 | 66 | <register name="Control"> |
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67 | 67 | <bitField name="UNUSED" size="20" mode="1" desc="UNUSED" offset="12"/> |
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68 | 68 | <bitField name="PW" size="1" mode="1" offset="11" desc="Power down (PW). Returns ‘1’ when processor in in power-down mode."/> |
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69 | 69 | <bitField name="HL" size="1" mode="1" offset="10" desc="Processor halt (HL). Returns ‘1’ on read when processor is halted. If the processor is in debug mode, setting this bit will put the processor in halt mode."/> |
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70 | 70 | <bitField name="PE" size="1" mode="3" offset="9" desc="Processor error mode (PE) - returns ‘1’ on read when processor is in error mode, else ‘0’. If written with ‘1’, it will clear the error and halt mode."/> |
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71 | 71 | <bitField name="EB" size="1" mode="1" offset="8" desc="EB - value of the external DSUBRE signal (read-only)"/> |
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72 | 72 | <bitField name="EE" size="1" mode="1" offset="7" desc="EE - value of the external DSUEN signal (read-only)"/> |
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73 | 73 | <bitField name="DM" size="1" mode="1" offset="6" desc="Debug mode (DM). Indicates when the processor has entered debug mode (read-only)."/> |
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74 | 74 | <bitField name="BZ" size="1" mode="3" offset="5" desc="Break on error traps (BZ) - if set, will force the processor into debug mode on all except the following traps: priviledged_instruction, fpu_disabled, window_overflow, window_underflow, asynchronous_interrupt, ticc_trap."/> |
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75 | 75 | <bitField name="BX" size="1" mode="3" offset="4" desc="Break on trap (BX) - if set, will force the processor into debug mode when any trap occurs."/> |
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76 | 76 | <bitField name="BS" size="1" mode="3" offset="3" desc="Break on S/W breakpoint (BS) - if set, debug mode will be forced when an breakpoint instruction (ta 1) is executed."/> |
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77 | 77 | <bitField name="BW" size="1" mode="3" offset="2" desc="Break on IU watchpoint (BW)- if set, debug mode will be forced on a IU watchpoint (trap 0xb)."/> |
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78 | 78 | <bitField name="BE" size="1" mode="3" offset="1" desc="Break on error (BE) - if set, will force the processor to debug mode when the processor would have entered error condition (trap in trap)."/> |
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79 | 79 | <bitField name="TE" size="1" mode="3" offset="0" desc="Trace enable (TE). Enables instruction tracing. If set the instructions will be stored in the trace buffer. Remains set
when then processor enters debug or error mode."/> |
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80 | 80 | </register> |
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81 | 81 | <register name="Time tag counter" addOffset="8"> |
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82 | 82 | <bitField name="UNUSED" size="2" mode="1" offset="30" desc=""/> |
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83 | 83 | <bitField name="DSU TIME TAG VALUE" size="30" mode="1" offset="0" desc="The value is used as time tag in the instruction and AHB trace buffer. The width of the timer (up to 30 bits) is configurable through the DSU generic port."/> |
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84 | 84 | </register> |
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85 | 85 | <register name="Break and Single Step" addOffset="32"> |
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86 | 86 | <bitField name="SSx" size="16" mode="3" offset="16" desc="[31:16] : Single step (SSx) - if set, the processor x will execute one instruction and return to debug mode. The bit remains set after the processor goes into the debug mode."/> |
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87 | 87 | <bitField name="BNx" size="16" mode="3" offset="0" desc="[15:0] : Break now (BNx) -Force processor x into debug mode if the Break on watchpoint (BW) bit in the processors DSU control register is set. If cleared, the processor x will resume execution."/> |
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88 | 88 | </register> |
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89 | 89 | <register name="Debug Mode Mask" addOffset="36"> |
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90 | 90 | <bitField name="DMx" size="16" mode="3" offset="16" desc="[31:16]: Debug mode mask. If set, the corresponding processor will not be able to force running processors into debug mode even if it enters debug mode."/> |
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91 | 91 | <bitField name="EDx" size="16" mode="3" offset="0" desc="[15:0] : Enter debug mode (EDx) - Force processor x into debug mode if any of processors in a multiprocessor system enters the debug mode. If 0, the processor x will not enter the debug mode."/> |
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92 | 92 | </register> |
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93 | 93 | <register name="AHB Trace buffer control" addOffset="64"> |
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94 | 94 | <bitField name="DCNT" size="16" mode="1" offset="16" desc="Trace buffer delay counter (DCNT). Note that the number of bits actually implemented depends on the size of the trace buffer."/> |
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95 | 95 | <bitField name="RESERVED" size="13" mode="1" offset="3" desc=""/> |
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96 | 96 | <bitField name="BR" size="1" mode="3" offset="2" desc="Break (BR). If set, the processor will be put in debug mode when AHB trace buffer stops due to AHB breakpoint hit."/> |
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97 | 97 | <bitField name="DM" size="1" mode="1" offset="1" desc="Delay counter mode (DM). Indicates that the trace buffer is in delay counter mode."/> |
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98 | 98 | <bitField name="EN" size="1" mode="3" offset="0" desc="Trace enable (EN). Enables the trace buffer."/> |
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99 | 99 | </register> |
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100 | 100 | <register name="AHB trace buffer index" addOffset="68"> |
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101 | 101 | <bitField name="INDEX" size="28" mode="3" offset="4" desc="Trace buffer index counter (INDEX). Note that the number of bits actually implemented depends on the size of the trace buffer."/> |
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102 | 102 | <bitField name="UNUSED" size="4" mode="1" offset="0" desc=""/> |
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103 | 103 | </register> |
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104 | 104 | <register name="AHB breakpoint address 1" addOffset="80"> |
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105 | 105 | <bitField name="BADDR[31:2]" size="30" mode="3" offset="2" desc="Breakpoint address (bits 31:2)"/> |
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106 | 106 | <bitField name="UNUSED" size="2" mode="1" offset="0" desc=""/> |
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107 | 107 | </register> |
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108 | 108 | <register name="AHB mask register 1" addOffset="84"> |
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109 | 109 | <bitField name="BMASK[31:2]" size="30" mode="3" offset="2" desc="Breakpoint mask"/> |
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110 | 110 | <bitField name="LD" size="1" mode="3" offset="1" desc="LD - break on data load address"/> |
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111 | 111 | <bitField name="ST" size="1" mode="3" offset="0" desc="ST - break on data store address"/> |
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112 | 112 | </register> |
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113 | 113 | <register name="AHB breakpoint address 2" addOffset="88"> |
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114 | 114 | <bitField name="BADDR[31:2]" size="30" mode="3" offset="2" desc="Breakpoint address (bits 31:2)"/> |
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115 | 115 | <bitField name="UNUSED" size="2" mode="1" offset="0" desc=""/> |
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116 | 116 | </register> |
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117 | 117 | <register name="AHB mask register 2" addOffset="92"> |
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118 | 118 | <bitField name="BMASK[31:2]" size="30" mode="3" offset="2" desc="Breakpoint mask "/> |
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119 | 119 | <bitField name="LD" size="1" mode="3" offset="1" desc="LD - break on data load address"/> |
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120 | 120 | <bitField name="ST" size="1" mode="3" offset="0" desc="ST - beak on data store address"/> |
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121 | 121 | </register> |
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122 | 122 | <register name="Instruction Trace buffer control" addOffset="1114112"> |
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123 | 123 | <bitField name="RESERVED" size="16" mode="1" offset="16" desc=""/> |
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124 | 124 | <bitField name="IT POINTER" size="16" mode="3" offset="0" desc="Instruction trace pointer. Note that the number of bits actually implemented depends on the size of the trace buffer."/> |
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125 | 125 | </register> |
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126 | 126 | <register name="SP" addOffset="3145784"> |
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127 | 127 | <bitField name="SP" size="32" mode="3" offset="0" desc="IU Window 0 Stack Pointer"/> |
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128 | 128 | </register> |
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129 | 129 | <register name="Y" addOffset="4194304"/> |
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130 | 130 | <register name="PSR" addOffset="4194308"> |
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131 | 131 | <bitField name="IMPL" size="4" mode="3" offset="28" desc="Bits 31 through 28 are hardwired to identify an implementation or class of implementations of the architecture. The hardware should not change this field in response to a WRPSR instruction. Together, the PSR.impl and PSR.ver fields define a unique implementation or class of implementations of the architecture. See Appendix L, “Implementation Characteristics.”"/> |
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132 | 132 | <bitField name="VER" size="4" mode="3" offset="24" desc="Bits 27 through 24 are implementation-dependent. The ver field is either hardwired to identify one or more particular implementations or is a readable and writable state field whose properties are implementation-dependent. See Appendix L, “Implementation Characteristics.”"/> |
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133 | 133 | <bitField name="NEGATIVE" size="1" mode="3" offset="23" desc="Bit 23 indicates whether the 32-bit 2’s complement ALU result was negative for the last instruction that modified the icc field. 1 = negative, 0 = not negative."/> |
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134 | 134 | <bitField name="ZERO" size="1" mode="3" offset="22" desc="Bit 22 indicates whether the 32-bit ALU result was zero for the last instruction that modified the icc field. 1 = zero, 0 = nonzero."/> |
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135 | 135 | <bitField name="OVERFLOW" size="1" mode="3" offset="21" desc="Bit 21 indicates whether the ALU result was within the range of (was representable in) 32-bit 2’s complement notation for the last instruction that modified the icc field. 1 = overflow, 0 = no overflow."/> |
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136 | 136 | <bitField name="CARRY" size="1" mode="3" offset="20" desc="Bit 21 indicates whether the ALU result was within the range of (was representable in) 32-bit 2’s complement notation for the last instruction that modified the icc field. 1 = overflow, 0 = no overflow."/> |
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137 | 137 | <bitField name="RESERVED" size="6" mode="1" offset="14" desc="Bits 19 through 14 are reserved. When read by a RDPSR instruction, these bits deliver zeros. For future compatibility, supervisor software should only issue WRPSR instructions with zero values in this field."/> |
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138 | 138 | <bitField name="EC" size="1" mode="3" offset="13" desc="Bit 13 determines whether the implementation-dependent coprocessor is enabled. If disabled, a coprocessor instruction will trap. 1 = enabled, 0 = disabled. If an implementation does not support a coprocessor in hardware, PSR.EC should always read as 0 and writes to it should be ignored."/> |
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139 | 139 | <bitField name="EF" size="1" mode="3" offset="12" desc="Bit 12 determines whether the FPU is enabled. If disabled, a floating-point instruction will trap. 1 = enabled, 0 = disabled. If an implementation does not support a hardware FPU, PSR.EF should always read as 0 and writes to it should be ignored. 
 Programming Note Software can use the EF and EC bits to determine whether a particular process uses the FPU or CP. If a process does not use the FPU/CP, its registers do not need to be saved across a context switch."/> |
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140 | 140 | <bitField name="PIL" size="1" mode="3" offset="11" desc="Bits 11 (the most significant bit) through 8 (the least significant bit) identify the interrupt level above which the processor will accept an interrupt. See Chapter 7, “Traps.”"/> |
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141 | 141 | <bitField name="S" size="1" mode="3" offset="7" desc="Bit 7 determines whether the processor is in supervisor or user mode. 1 = supervisor mode, 0 = user mode."/> |
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142 | 142 | <bitField name="PS" size="1" mode="3" offset="6" desc="Bit 6 contains the value of the S bit at the time of the most recent trap."/> |
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143 | 143 | <bitField name="ET" size="1" mode="3" offset="5" desc="Bit 5 determines whether traps are enabled. A trap automatically resets ET to 0. When ET=0, an interrupt request is ignored and an exception trap causes the IU to halt execution, which typically results in a reset trap that resumes execution at address 0. 1 = traps enabled, 0 = traps disabled. See Chapter 7, “Traps.”"/> |
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144 | 144 | <bitField name="CWP" size="5" mode="3" offset="0" desc="Bits 4 (the MSB) through 0 (the LSB) comprise the current window pointer, a counter that identifies the current window into the r registers. The hardware decrements the CWP on traps and SAVE instructions, and increments it on RESTORE and RETT instructions (modulo NWINDOWS )."/> |
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145 | 145 | </register> |
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146 | 146 | <register name="WIM" addOffset="4194312"/> |
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147 | 147 | <register name="TBR" addOffset="4194316"/> |
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148 | 148 | <register name="PC" addOffset="4194320"/> |
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149 | 149 | <register name="NPC" addOffset="4194324"/> |
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150 | 150 | <register name="FSR" addOffset="4194328"/> |
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151 | 151 | <register name="CPSR" addOffset="4194332"/> |
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152 | 152 | <register name="DSU trap" addOffset="4194336"> |
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153 | 153 | <bitField name="RESERVED" size="19" mode="1" offset="13" desc=""/> |
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154 | 154 | <bitField name="EM" size="1" mode="1" offset="12" desc="Error mode (EM). Set if the trap would have cause the processor to enter error mode."/> |
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155 | 155 | <bitField name="TRAP TYPE" size="8" mode="1" offset="4" desc="8-bit SPARC trap type"/> |
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156 | 156 | <bitField name="UNUSED" size="4" mode="1" offset="0" desc=""/> |
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157 | 157 | </register> |
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158 | 158 | <register name="DSU ASI" addOffset="4194340"> |
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159 | 159 | <bitField name="UNUSED" size="24" mode="1" offset="8" desc=""/> |
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160 | 160 | <bitField name="ASI" size="8" mode="1" offset="0" desc="ASI to be used on diagnostic ASI access"/> |
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161 | 161 | </register> |
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162 | 162 | <register name="ASR16" addOffset="4194368"/> |
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163 | 163 | <register name="ASR17" addOffset="4194372"/> |
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164 | 164 | <register name="ASR18" addOffset="4194376"/> |
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165 | 165 | <register name="ASR19" addOffset="4194380"/> |
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166 | 166 | <register name="ASR20" addOffset="4194384"/> |
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167 | 167 | <register name="ASR21" addOffset="4194388"/> |
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168 | 168 | <register name="ASR22" addOffset="4194392"/> |
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169 | 169 | <register name="ASR23" addOffset="4194396"/> |
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170 | 170 | <register name="ASR24" addOffset="4194400"/> |
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171 | 171 | <register name="ASR25" addOffset="4194404"/> |
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172 | 172 | <register name="ASR26" addOffset="4194408"/> |
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173 | 173 | <register name="ASR27" addOffset="4194412"/> |
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174 | 174 | <register name="ASR28" addOffset="4194416"/> |
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175 | 175 | <register name="ASR29" addOffset="4194420"/> |
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176 | 176 | <register name="ASR30" addOffset="4194424"/> |
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177 | 177 | <register name="ASR31" addOffset="4194428"/> |
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178 | 178 | </peripheral> |
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179 | 179 | <peripheral vid="1" name="GPTIMER" pid="17"> |
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180 | 180 | <register name="Scaler value"> |
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181 | 181 | <bitField name="SCALER VALUE" size="16" mode="3" desc="Scaler value
Any unused most significant bits are reserved. Always reads as ‘000...0’."/> |
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182 | 182 | </register> |
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183 | 183 | <register name="Scaler reload value" addOffset="4"> |
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184 | 184 | <bitField name="SCALER RELOAD VALUE" size="16" mode="3" desc="Scaler reload value
Any unused most significant bits are reserved. Always read as ‘000...0’."/> |
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185 | 185 | </register> |
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186 | 186 | <register name="Configuration" addOffset="8"> |
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187 | 187 | <bitField name="TIMERS" size="3" mode="1" desc="Number of implemented timers. Read-only.
"/> |
|
|
188 | 188 | <bitField name="IRQ" size="5" mode="1" desc="APB Interrupt: If configured to use common interrupt all timers will drive APB interrupt nr. IRQ,
otherwise timer nwill drive APB Interrupt IRQ+n (has to be less the MAXIRQ). Read-only.
"/> |
|
|
189 | 189 | <bitField name="SI" size="1" mode="1" desc="Separate interrupts (SI). Reads ‘1’ if the timer unit generates separate interrupts for each timer, oth-erwise ‘0’. Read-only.
"/> |
|
|
190 | 190 | <bitField name="DF" size="1" mode="3" desc="Disable timer freeze (DF). If set the timer unit can not be freezed, otherwise signal GPTI.DHALT
freezes the timer unit.
"/> |
|
|
191 | 191 | </register> |
|
|
192 | 192 | <register name="Unused" addOffset="12"/> |
|
|
193 | 193 | <register name="Timer 1 counter value" addOffset="16"> |
|
|
194 | 194 | <bitField name="TIMER COUNTER VALUE" size="32" mode="3" desc="Timer Counter value. Decremented by 1 for each prescaler tick.
Any unused most significant bits are reserved. Always reads as ‘000...0’."/> |
|
|
195 | 195 | </register> |
|
|
196 | 196 | <register name="Timer 1 reload value" addOffset="20"> |
|
|
197 | 197 | <bitField name="TIMER RELOAD VALUE" size="32" mode="3" desc="Timer Reload value. This value is loaded into the timer counter value register when ‘1’ is written to
load bit in the timers control register or when the RS bit is set in the control register and the timer
underflows.
Any unused most significant bits are reserved. Always reads as ‘000...0’."/> |
|
|
198 | 198 | </register> |
|
|
199 | 199 | <register name="Timer 1 control" addOffset="24"> |
|
|
200 | 200 | <bitField name="EN" size="1" mode="3" desc="Enable (EN): Enable the timer."/> |
|
|
201 | 201 | <bitField name="RS" size="1" mode="3" desc="Restart (RS): If set, the timer counter value register is reloaded with the value of the reload register when the timer underflows"/> |
|
|
202 | 202 | <bitField name="LD"/> |
|
|
203 | 203 | <bitField name="IE" size="1" mode="3" desc="Interrupt Enable (IE): If set the timer signals interrupt when it underflows.
"/> |
|
|
204 | 204 | <bitField name="IP" size="1" mode="3" desc="Interrupt Pending (IP): The core sets this bit to ‘1’ when an interrupt is signalled. This bit remains ‘1’ until cleared by writing ‘1’ to this bit, writes of ‘0’ have no effect.
"/> |
|
|
205 | 205 | <bitField name="CH" size="1" mode="3" desc="Chain (CH): Chain with preceding timer. If set for timer n, timer n will be decremented each time when timer (n-1) underflows.
"/> |
|
|
206 | 206 | <bitField name="DH" size="1" mode="1" desc="Debug Halt (DH): Value of GPTI.DHALT signal which is used to freeze counters (e.g. when a sys-tem is in debug mode). Read-only.
"/> |
|
|
207 | 207 | </register> |
|
|
208 | 208 | </peripheral> |
|
|
209 | 209 | <peripheral vid="1" name="GRTIMER" pid="56"> |
|
|
210 | 210 | <register name="Scaler value"> |
|
|
211 | 211 | <bitField name="SCALER Value" size="16" mode="3" desc="Scaler value"/> |
|
|
212 | 212 | </register> |
|
|
213 | 213 | <register name="Scaler reload value" addOffset="4"> |
|
|
214 | 214 | <bitField name="SCALER Reload Value" size="32" mode="3" desc="SCALER Reload Value"/> |
|
|
215 | 215 | </register> |
|
|
216 | 216 | <register name="Configuration" addOffset="8"> |
|
|
217 | 217 | <bitField name="TIMERS" size="3" mode="1" desc="Number of implemented timers. Read-only.
"/> |
|
|
218 | 218 | <bitField name="IRQ" size="5" mode="1" desc="APB Interrupt: If configured to use common interrupt all timers will drive APB interrupt nr. IRQ,
otherwise timer nwill drive APB Interrupt IRQ+n (has to be less the MAXIRQ). Read-only.
"/> |
|
|
219 | 219 | <bitField name="SI" size="1" mode="1" desc="Separate interrupts (SI). Reads ‘1’ if the timer unit generates separate interrupts for each timer, oth-erwise ‘0’. Read-only.
"/> |
|
|
220 | 220 | <bitField name="DF" size="1" mode="3" desc="Disable timer freeze (DF). If set the timer unit can not be freezed, otherwise signal GPTI.DHALT
freezes the timer unit.
"/> |
|
|
221 | 221 | <bitField name="EE" size="1" mode="3" desc="Enable external clock source (EE). If set the prescaler is clocked from the external clock source."/> |
|
|
222 | 222 | <bitField name="EL" size="1" mode="3" desc="Enable latching (EL). If set, on the next matching interrupt, the latches will be loaded with the corresponding timer
values. The bit is then automatically cleared, not to load a timer value until set again."/> |
|
|
223 | 223 | <bitField name="ES" size="1" mode="3" desc="Enable set (ES). If set, on the next matching interrupt, the timers will be loaded with the corresponding timer reload
values. The bit is then automatically cleared, not to reload the timer values until set again. (Added to revision 2)."/> |
|
|
224 | 224 | </register> |
|
|
225 | 225 | <register name="Timer latch configuration" addOffset="12"> |
|
|
226 | 226 | <bitField name="LTCV" size="32" mode="3" desc="[nbits-1:0] Latched Timer Counter Value (LTCV). Value latch from corresponding timer."/> |
|
|
227 | 227 | </register> |
|
|
228 | 228 | <register name="Timer 1 counter value" addOffset="16"> |
|
|
229 | 229 | <bitField name="TIMER COUNTER VALUE" size="32" mode="3" desc="[nbits-1:0] Timer Counter value. Decremented by 1 for each prescaler tick."/> |
|
|
230 | 230 | </register> |
|
|
231 | 231 | <register name="Timer 1 reload value" addOffset="20"> |
|
|
232 | 232 | <bitField name="TIMER RELOAD VALUE" size="32" mode="3" desc="[nbits-1:0] Timer Reload value. This value is loaded into the timer counter value register when ‘1’ is written to load bit in the timers control register."/> |
|
|
233 | 233 | </register> |
|
|
234 | 234 | <register name="Timer 1 control" addOffset="24"> |
|
|
235 | 235 | <bitField name="EN" size="1" mode="3" desc="Enable (EN): Enable the timer."/> |
|
|
236 | 236 | <bitField name="RS" size="1" mode="3" desc="Restart (RS): If set the value from the timer reload register is loaded to the timer counter value register and
decrementing the timer is restarted."/> |
|
|
237 | 237 | <bitField name="LD" size="1" mode="3" desc="Load (LD): Load value from the timer reload register to the timer counter value register."/> |
|
|
238 | 238 | <bitField name="IE" size="1" mode="3" desc="Interrupt Enable (IE): If set the timer signals interrupt when it underflows."/> |
|
|
239 | 239 | <bitField name="IP" size="1" mode="3" desc="Interrupt Pending (IP): The core sets this bit to ‘1’ when an interrupt is signalled. This bit remains ‘1’ until cleared
by writing ‘1’ to this bit, writes of ‘0’ have no effect."/> |
|
|
240 | 240 | <bitField name="CH" size="1" mode="3" desc="Chain (CH): Chain with preceding timer. If set for timer n, timer n will be decremented each time when timer (n-1)
underflows."/> |
|
|
241 | 241 | <bitField name="DH" size="1" mode="3" desc="Debug Halt (DH): Value of GPTI.DHALT signal which is used to freeze counters (e.g. when a system is in debug
mode). Read-only."/> |
|
|
242 | 242 | </register> |
|
|
243 | 243 | <register name="Timer 1 latch" addOffset="28"> |
|
|
244 | 244 | <bitField name="LTCV" size="32" mode="3" desc="[nbits-1:0] Latched Timer Counter Value (LTCV). Value latch from corresponding timer."/> |
|
|
245 | 245 | </register> |
|
|
246 | 246 | </peripheral> |
|
|
247 | 247 | <peripheral vid="4" name="MCTRL" pid="15"> |
|
|
248 | 248 | <register name="MCFG1"> |
|
|
249 | 249 | <bitField name="PROM READ WS" size="4" mode="3" desc="PROM read waitstates (PROM READ WS) - Sets the number of wait states for PROM read cycles (“0000”=0, “0001”=1, “0010”=2,...,”1111”=15). Reset to “1111”.
"/> |
|
|
250 | 250 | <bitField name="PROM WRITE WS" size="4" mode="3" desc="PROM write waitstates (PROM WRITE WS) - Sets the number of wait states for PROM write cycles
(“0000”=0, “0001”=1, “0010”=2,..., “1111”=15).
"/> |
|
|
251 | 251 | <bitField name="PROM WIDTH" size="2" mode="3" desc="PROM width (PROM WIDTH) - Sets the data width of the PROM area (“00”=8, “01”=16,
 “10”=32).
"/> |
|
|
252 | 252 | <bitField name="PWEN" size="1" mode="3" desc="PROM write enable (PWEN) - Enables write cycles to the PROM area.
"/> |
|
|
253 | 253 | <bitField name="RESERVED"/> |
|
|
254 | 254 | <bitField name="IOEN" size="1" mode="3" desc="I/O enable (IOEN) - Enables accesses to the memory bus I/O area.
"/> |
|
|
255 | 255 | <bitField name="IO WAITSTATES" size="4" mode="3" desc="I/O waitstates (IO WAITSTATES) - Sets the number of waitstates during I/O accesses (“0000”=0, “0001”=1, “0010”=2,..., “1111”=15).
"/> |
|
|
256 | 256 | <bitField name="BEXCN" size="1" mode="3" desc="Bus error enable (BEXCN) - Enables bus error signalling. Reset to ‘0’.
"/> |
|
|
257 | 257 | <bitField name="IBRDY" size="1" mode="3" desc="I/O bus ready enable (IBRDY) - Enables bus ready (BRDYN) signalling for the I/O area. Reset to ‘0’.
"/> |
|
|
258 | 258 | <bitField name="IOBUSW" size="1" mode="3" desc="I/O bus width (IOBUSW) - Sets the data width of the I/O area (“00”=8, “01”=16, “10” =32).
"/> |
|
|
259 | 259 | </register> |
|
|
260 | 260 | <register name="MCFG2" addOffset="4"> |
|
|
261 | 261 | <bitField name="RAM READ WS" size="2" mode="3" desc="RAM read waitstates (RAM READ WS) - Sets the number of wait states for RAM read cycles (“00”=0, “01”=1, “10”=2, “11”=3).
"/> |
|
|
262 | 262 | <bitField name="RAM WRITE WS" size="2" mode="3" desc="RAM write waitstates (RAM WRITE WS) - Sets the number of wait states for RAM write cycles (“00”=0, “01”=1, “10”=2, “11”=3).
"/> |
|
|
263 | 263 | <bitField name="RAM WIDTH" size="2" mode="3" desc="RAM width (RAM WIDTH) - Sets the data width of the RAM area (“00”=8, “01”=16, “1X”=32).
"/> |
|
|
264 | 264 | <bitField name="RMW" size="1" mode="3" desc="Read-modify-write enable (RMW) - Enables read-modify-write cycles for sub-word writes to 16- bit 32-bit areas with common write strobe (no byte write strobe).
"/> |
|
|
265 | 265 | <bitField name="RBRDY" size="1" mode="3" desc="RAM bus ready enable (RBRDY) - Enables bus ready signalling for the RAM area.
"/> |
|
|
266 | 266 | <bitField name="RAM BANK SIZE" size="4" mode="3" desc="RAM bank size (RAM BANK SIZE) - Sets the size of each RAM bank (“0000”=8 kbyte, “0001”=16 kbyte, ..., “1111”=256 Mbyte).
"/> |
|
|
267 | 267 | <bitField name="SI" size="1" mode="3" desc="SRAM disable (SI) - Disables accesses RAM if bit 14 (SE) is set to ‘1’.
"/> |
|
|
268 | 268 | <bitField name="SE" size="1" mode="3" desc="SDRAM enable (SE) - Enables the SDRAM controller.
"/> |
|
|
269 | 269 | <bitField name="RESERVED" size="1" mode="1" desc=""/> |
|
|
270 | 270 | <bitField name="MS" size="1" mode="1" desc="Mobile SDR support enabled. ‘1’ = Enabled, ‘0’ = Disabled (read-only)"/> |
|
|
271 | 271 | <bitField name="RESERVED" size="1" mode="1" desc=""/> |
|
|
272 | 272 | <bitField name="D64" size="1" mode="1" desc="64-bit SDRAM data bus (D64) - Reads ‘1’ if the memory controller is configured for 64-bit SDRAM data bus width, ‘0’ otherwise. Read-only.
"/> |
|
|
273 | 273 | <bitField name="SDRAM CMD" size="2" mode="3" desc="SDRAM command (SDRAM CMD) - Writing a non-zero value will generate a SDRAM command. “01”=PRECHARGE, “10”=AUTO-REFRESH, “11”=LOAD-COMMAND-REGISTER. The field is reset after the command has been executed.
"/> |
|
|
274 | 274 | <bitField name="SDRAM COLSZ" size="2" mode="3" desc="SDRAM column size (SDRAM COLSZ) - “00”=256, “01”=512, “10”=1024, “11”=4096 when bit 25:23=”111” 2048 otherwise.
"/> |
|
|
275 | 275 | <bitField name="SDRAM BANKSZ" size="3" mode="3" desc="SDRAM bank size (SDRAM BANKSZ) - Sets the bank size for SDRAM chip selects (“000”=4 Mbyte, “001”=8 Mbyte, “010”=16 Mbyte.... “111”=512 Mbyte).
"/> |
|
|
276 | 276 | <bitField name="TCAS" size="1" mode="3" desc="SDRAM TCAS parameter (TCAS) - Selects 2 or 3 cycle CAS delay (0/1). When changed, a LOAD-COMMAND-REGISTER command must be issued at the same time. Also sets RAS/CAS delay (tRCD).
"/> |
|
|
277 | 277 | <bitField name="SDRAM TRFC" size="3" mode="3" desc="SDRAM TRFC parameter (SDRAM TRFC) - tRFC will be equal to 3+field-value system clocks.
"/> |
|
|
278 | 278 | <bitField name="TRP" size="1" mode="3" desc="SDRAM TRP parameter (TRP) - tRP will be equal to 2 or 3 system clocks (0/1).
"/> |
|
|
279 | 279 | <bitField name="SDRF" size="1" mode="3" desc="SDRAM refresh (SDRF) - Enables SDRAM refresh.
"/> |
|
|
280 | 280 | </register> |
|
|
281 | 281 | <register name="MCFG3" addOffset="8"> |
|
|
282 | 282 | <bitField name="SDRAM REFRESH RELOAD VALUE" size="15" mode="3" desc="SDRAM refresh counter reload value (SDRAM REFRESH RELOAD VALUE)

The period between each AUTO-REFRESH command is calculated as follows:
tREFRESH = ((reload value) + 1) / SYSCLK"/> |
|
|
283 | 283 | </register> |
|
|
284 | 284 | <register name="MCFG4(Power-Saving configuration)" addOffset="12"> |
|
|
285 | 285 | <bitField name="PASR" size="3" mode="3" desc="Partial Array Self Refresh (Read only when Mobile SDR support is disabled).
“000”: Full array (Banks 0, 1, 2 and 3)
“001”: Half array (Banks 0 and 1)
“010”: Quarter array (Bank 0)
“101”: One-eighth array (Bank 0 with row MSB = 0)
“110”: One-sixteenth array (Bank 0 with row MSB = 00)
"/> |
|
|
286 | 286 | <bitField name="TCSR" size="2" mode="3" desc="Reserved for Temperature-Compensated Self Refresh (Read only when Mobile SDR support is disa-bled).
“00”: 70aC
“01”: 45aC
“10”: 15aC
“11”: 85aC
"/> |
|
|
287 | 287 | <bitField name="DS" size="2" mode="3" desc="Selectable output drive strength (Read only when Mobile SDR support is disabled).
“00”: Full
“01”: One-half
“10”: One-quarter
“11”: Three-quarter
"/> |
|
|
288 | 288 | <bitField name="PMODE" size="3" mode="3" desc="Power-Saving mode (Read only when Mobile SDR support is disabled).
“000”: none
“001”: Power-Down (PD)
“010”: Self-Refresh (SR)
“101”: Deep Power-Down (DPD)
"/> |
|
|
289 | 289 | <bitField name="tXSR" size="4" mode="3" desc="SDRAM tXSR timing. tXSR will be equal to field-value system clocks. (Read only when Mobile SDR support is disabled).
"/> |
|
|
290 | 290 | <bitField name="EM" size="1" mode="3" desc="EMR. When set, the LOAD-COMMAND-REGISTER command issued by the SDRAM command filed in MCFG2 will be interpret as a LOAD-EXTENDED-COMMAND-REGISTER command.
"/> |
|
|
291 | 291 | <bitField name="CE" size="1" mode="3" desc="Clock enable (CE). This value is driven on the CKE inputs of the SDRAM. Should be set to ‘1’ for correct operation. This register bit is read only when Power-Saving mode is other then none.
"/> |
|
|
292 | 292 | <bitField name="ME" size="1" mode="3" desc="Mobile SDRAM functionality enabled. ‘1’ = Enabled (support for Mobile SDRAM), ‘0’ = disabled (support for standard SDRAM)
"/> |
|
|
293 | 293 | </register> |
|
|
294 | 294 | </peripheral> |
|
|
295 | 295 | <peripheral vid="1" name="IRQMP" pid="13"> |
|
|
296 | 296 | <register name="Interrupt level"/> |
|
|
297 | 297 | <register name="Interrupt pending" addOffset="4"/> |
|
|
298 | 298 | <register name="Interrupt force (NCPU=0)" addOffset="8"/> |
|
|
299 | 299 | <register name="Interrupt clear" addOffset="12"/> |
|
|
300 | 300 | <register name="Multiprocessor status" addOffset="16"/> |
|
|
301 | 301 | <register name="Broadcast" addOffset="20"/> |
|
|
302 | 302 | <register name="Processor interrupt mask" addOffset="64"/> |
|
|
303 | 303 | <register name="Processor 1 interrupt mask" addOffset="68"/> |
|
|
304 | 304 | <register name="Processor interrupt force" addOffset="128"/> |
|
|
305 | 305 | <register name="Processor 1 interrupt force" addOffset="132"/> |
|
|
306 | 306 | <register name="Processor extended interrupt acknowledge" addOffset="192"/> |
|
|
307 | 307 | <register name="Processor 1 extended interrupt acknowledge" addOffset="196"/> |
|
|
308 | 308 | </peripheral> |
|
|
309 | 309 | <peripheral vid="1" name="GRSPW2" pid="41"> |
|
|
310 | 310 | <register name="Control"/> |
|
|
311 | 311 | <register name="Status/Interrupt-source" addOffset="4"/> |
|
|
312 | 312 | <register name="Node address" addOffset="8"/> |
|
|
313 | 313 | <register name="Clock divisor" addOffset="12"/> |
|
|
314 | 314 | <register name="Destination key" addOffset="16"/> |
|
|
315 | 315 | <register name="Time" addOffset="20"/> |
|
|
316 | 316 | <register name="DMA channel 1 control/status" addOffset="32"/> |
|
|
317 | 317 | <register name="DMA channel 1 rx maximum length" addOffset="36"/> |
|
|
318 | 318 | <register name="DMA channel 1 transmit descriptor table address" addOffset="40"/> |
|
|
319 | 319 | <register name="DMA channel 1 receive descriptor table address" addOffset="44"/> |
|
|
320 | 320 | <register name="DMA channel 1 address" addOffset="48"/> |
|
|
321 | 321 | <register name="DMA channel 2 control/status" addOffset="64"/> |
|
|
322 | 322 | <register name="DMA channel 2 rx maximum length" addOffset="68"/> |
|
|
323 | 323 | <register name="DMA channel 2 transmit descriptor table address" addOffset="72"/> |
|
|
324 | 324 | <register name="DMA channel 2 receive descriptor table address" addOffset="76"/> |
|
|
325 | 325 | <register name="DMA channel 2 address" addOffset="80"/> |
|
|
326 | 326 | <register name="DMA channel 3 control/status" addOffset="96"/> |
|
|
327 | 327 | <register name="DMA channel 3 rx maximum length" addOffset="100"/> |
|
|
328 | 328 | <register name="DMA channel 3 transmit descriptor table address" addOffset="104"/> |
|
|
329 | 329 | <register name="DMA channel 3 receive descriptor table address" addOffset="108"/> |
|
|
330 | 330 | <register name="DMA channel 3 address" addOffset="112"/> |
|
|
331 | 331 | <register name="DMA channel 4 control/status" addOffset="128"/> |
|
|
332 | 332 | <register name="DMA channel 4 rx maximum length" addOffset="132"/> |
|
|
333 | 333 | <register name="DMA channel 4 transmit descriptor table address" addOffset="136"/> |
|
|
334 | 334 | <register name="DMA channel 4 receive descriptor table address" addOffset="140"/> |
|
|
335 | 335 | <register name="DMA channel 4 address" addOffset="144"/> |
|
|
336 | 336 | </peripheral> |
|
|
337 | 337 | <peripheral vid="1" name="SRCTRL" pid="8"/> |
|
|
338 | 338 | <peripheral vid="1" name="SSRCTRL" pid="10"> |
|
|
339 | 339 | <register name="Memory configuration"/> |
|
|
340 | 340 | </peripheral> |
|
|
341 | 341 | <peripheral vid="1" name="AHBDPRAM" pid="15"/> |
|
|
342 | 342 | <peripheral vid="1" name="GRGPIO" pid="26"> |
|
|
343 | 343 | <register name="Data"> |
|
|
344 | 344 | <bitField name="DATA" size="32" mode="1" desc=""/> |
|
|
345 | 345 | </register> |
|
|
346 | 346 | <register name="Output" addOffset="4"> |
|
|
347 | 347 | <bitField name="OUTPUT" size="32" mode="3" desc=""/> |
|
|
348 | 348 | </register> |
|
|
349 | 349 | <register name="Direction" addOffset="8"> |
|
|
350 | 350 | <bitField name="DIRECTION" size="32" mode="3" desc=""/> |
|
|
351 | 351 | </register> |
|
|
352 | 352 | <register name="Interrupt mask" addOffset="12"/> |
|
|
353 | 353 | <register name="Interrupt polarity" addOffset="16"/> |
|
|
354 | 354 | <register name="Interrupt edge" addOffset="20"/> |
|
|
355 | 355 | <register name="Bypass" addOffset="24"/> |
|
|
356 | 356 | <register name="Capability" addOffset="28"/> |
|
|
357 | 357 | <register name="IRQ map 0" addOffset="32"/> |
|
|
358 | 358 | <register name="IRQ map 1" addOffset="36"/> |
|
|
359 | 359 | <register name="IRQ map 2" addOffset="40"/> |
|
|
360 | 360 | <register name="IRQ map 3" addOffset="44"/> |
|
|
361 | 361 | <register name="IRQ map 4" addOffset="48"/> |
|
|
362 | 362 | <register name="IRQ map 5" addOffset="52"/> |
|
|
363 | 363 | <register name="IRQ map 6" addOffset="56"/> |
|
|
364 | 364 | <register name="IRQ map 7" addOffset="60"/> |
|
|
365 | 365 | </peripheral> |
|
|
366 | 366 | <peripheral vid="1" name="GRSPW" pid="31"> |
|
|
367 | 367 | <register name="Control"> |
|
|
368 | 368 | <bitField name="RA" size="1" offset="31" mode="1" desc="RMAP available (RA) - Set to one if the RMAP command handler is available. Only readable."/> |
|
|
369 | 369 | <bitField name="RX" size="1" offset="30" mode="1" desc="RX unaligned access (RX) - Set to one if unaligned writes are available for the receiver. Only read- |
|
|
370 | 370 | able."/> |
|
|
371 | 371 | <bitField name="RC" size="1" offset="29" mode="1" desc="RMAP CRC available (RC) - Set to one if RMAP CRC is enabled in the core. Only readable."/> |
|
|
372 | 372 | <bitField name="PO" size="1" offset="26" mode="1" desc="The number of available SpaceWire ports minus one. Only readable."/> |
|
|
373 | 373 | <bitField name="PS" size="1" offset="21" mode="3" desc="Port select (PS) - Selects the active port when the no port force bit is zero. ‘0’ selects the port connected to data and strobe on index 0 while ‘1’ selects index 1. Only available if the ports VHDL |
|
|
374 | 374 | generic is set to 2. Reset value: ‘0’."/> |
|
|
375 | 375 | <bitField name="NP" size="1" offset="20" mode="3" desc="No port force (NP) - Disable port force. When disabled the port select bit cannot be used to select the active port. Instead, it is automatically selected by checking the activity on the respective receive links. Only available if the ports VHDL generic is set to 2. Reset value: ‘0’ if the RMAP command handler is not available. If available the reset value is set to the value of the rmapen input signal."/> |
|
|
376 | 376 | <bitField name="RD" size="1" offset="17" mode="3" desc="RMAP buffer disable (RD) - Unused. If set only one RMAP buffer is used. This ensures that all RMAP commands will be executed consecutively. Only available if the rmap VHDL generic is set to1. Reset value: ‘0’."/> |
|
|
377 | 377 | <bitField name="RE" size="1" offset="16" mode="3" desc="RMAP Enable (RE) - Unused. Enable RMAP command handler. Only available if rmap VHDL generic is set to 1. Reset value: ‘1’."/> |
|
|
378 | 378 | <bitField name="TR" size="1" offset="11" mode="3" desc="Time Rx Enable (TR) - Enable time-code receptions. Reset value: ‘0’."/> |
|
|
379 | 379 | <bitField name="TT" size="1" offset="10" mode="3" desc="Time Tx Enable (TT) - Enable time-code transmissions. Reset value: ‘0’."/> |
|
|
380 | 380 | <bitField name="LI" size="1" offset="9" mode="3" desc="Link error IRQ (LI) - Generate interrupt when a link error occurs. Not reset."/> |
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381 | 381 | <bitField name="TQ" size="1" offset="8" mode="3" desc="Tick-out IRQ (TQ) - Generate interrupt when a valid time-code is received. Not reset."/> |
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382 | 382 | <bitField name="RS" size="1" offset="6" mode="3" desc="Reset (RS) - Make complete reset of the SpaceWire node. Self clearing. Reset value: ‘0’."/> |
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383 | 383 | <bitField name="PM" size="1" offset="5" mode="3" desc="Promiscuous Mode (PM) - Enable Promiscuous mode. Reset value: ‘0’."/> |
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384 | 384 | <bitField name="TI" size="1" offset="4" mode="3" desc="Tick In (TI) - The host can generate a tick by writing a one to this field. This will increment the timer counter and the new value is transmitted after the current character is transferred. A tick can also be generated by asserting the tick_in signal. Reset value: ‘0’."/> |
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385 | 385 | <bitField name="IE" size="1" offset="3" mode="3" desc="Interrupt Enable (IE) - If set, an interrupt is generated when one or both of bit 8 to 9 is set and its corresponding event occurs. Reset value: ‘0’."/> |
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386 | 386 | <bitField name="AS" size="1" offset="2" mode="3" desc="Autostart (AS) - Automatically start the link when a NULL has been received. Reset value: ‘0’ if the RMAP command handler is not available. If available the reset value is set to the value of the rmapen input signal."/> |
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387 | 387 | <bitField name="LS" size="1" offset="1" mode="3" desc="Link Start (LS) - Start the link, i.e. allow a transition from ready to started state. Reset value: ‘0’."/> |
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388 | 388 | <bitField name="LD" size="1" offset="0" mode="3" desc="Link Disable (LD) - Disable the SpaceWire codec. Reset value: ‘0’."/> |
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389 | 389 | </register> |
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390 | 390 | <register name="Status/Interrupt-source"> |
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391 | 391 | <bitField name="LS" size="3" offset="21" mode="1" desc="Link State (LS) - The current state of the start-up sequence. 0 = Error-reset, 1 = Error-wait, 2 = Ready, 3 = Started, 4 = Connecting, 5 = Run. Reset value: 0."/> |
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392 | 392 | <bitField name="AP" size="1" offset="9" mode="1" desc="Active port (AP) - Shows the currently active port. ‘0’ = Port 0 and ‘1’ = Port 1 where the port numbers refer to the index number of the data and strobe signals. Only available if the ports generic is set to 2."/> |
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393 | 393 | <bitField name="EE" size="1" offset="8" mode="1" desc="Early EOP/EEP (EE) - Set to one when a packet is received with an EOP after the first byte for a non-rmap packet and after the second byte for a RMAP packet. Cleared when written with a one. Reset value: ‘0’."/> |
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394 | 394 | <bitField name="IA" size="1" offset="7" mode="1" desc="Invalid Address (IA) - Set to one when a packet is received with an invalid destination address field, i.e it does not match the nodeaddr register. Cleared when written with a one. Reset value: ‘0’."/> |
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395 | 395 | <bitField name="WE" size="1" offset="6" mode="1" desc="Write synchronization Error (WE) - A synchronization problem has occurred when receiving NChars. Cleared when written with a one. Reset value: ‘0’."/> |
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396 | 396 | <bitField name="PE" size="1" offset="4" mode="1" desc="Parity Error (PE) - A parity error has occurred. Cleared when written with a one. Reset value: ‘0’."/> |
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397 | 397 | <bitField name="DE" size="1" offset="3" mode="1" desc="Disconnect Error (DE) - A disconnection error has occurred. Cleared when written with a one. Reset value: ‘0’."/> |
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398 | 398 | <bitField name="ER" size="1" offset="2" mode="1" desc="Escape Error (ER) - An escape error has occurred. Cleared when written with a one. Reset value: ‘0’."/> |
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399 | 399 | <bitField name="CE" size="1" offset="1" mode="1" desc="Credit Error (CE) - A credit has occurred. Cleared when written with a one. Reset value: ‘0’."/> |
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400 | 400 | <bitField name="TO" size="1" offset="0" mode="1" desc="Tick Out (TO) - A new time count value was received and is stored in the time counter field. Cleared when written with a one. Reset value: ‘0’."/> |
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401 | 401 | </register> |
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402 | 402 | <register name="Node address"> |
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403 | 403 | <bitField name="NODEADDR" size="8" offset="0" mode="3" desc="Node address (NODEADDR) - 8-bit node address used for node identification on the SpaceWire network. Reset value: 254 (taken from the nodeaddr VHDL generic when /= 255, else from the rmapnodeaddr input signal)"/> |
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404 | 404 | </register> |
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405 | 405 | <register name="Clock divisor"> |
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406 | 406 | <bitField name="DATA" size="32" mode="1" desc=""/> |
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407 | 407 | </register> |
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408 | 408 | <register name="Destination key"> |
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409 | 409 | <bitField name="DESTKEY" size="8" offset="0" mode="3" desc="Destination key (DESTKEY) - RMAP destination key. Only available if the rmap VHDL generic is set to 1. Reset value: 0 (taken from the deskey VHDL generic)"/> |
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410 | 410 | </register> |
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411 | 411 | <register name="Time"> |
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412 | 412 | <bitField name="DATA" size="32" mode="1" desc=""/> |
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413 | 413 | </register> |
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414 | 414 | <register name="Timer end Disconnect"> |
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415 | 415 | <bitField name="DATA" size="32" mode="1" desc=""/> |
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416 | 416 | </register> |
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417 | 417 | <register name="DMA channel 1 control/status"> |
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418 | 418 | <bitField name="DATA" size="32" mode="1" desc=""/> |
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419 | 419 | </register> |
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420 | 420 | <register name="DMA channel 1 rx maximum length"> |
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421 | 421 | <bitField name="DATA" size="32" mode="1" desc=""/> |
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422 | 422 | </register> |
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423 | 423 | <register name="DMA channel 1 transmit descriptor table address"> |
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424 | 424 | <bitField name="DATA" size="32" mode="1" desc=""/> |
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425 | 425 | </register> |
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426 | 426 | <register name="DMA channel 1 control/status"> |
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427 | 427 | <bitField name="DATA" size="32" mode="1" desc=""/> |
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428 | 428 | </register> |
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429 | 429 | <register name="DMA channel 1 receive descriptor table address"> |
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430 | 430 | <bitField name="DATA" size="32" mode="1" desc=""/> |
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431 | 431 | </register> |
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432 | 432 | </peripheral> |
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433 | <peripheral vid="1" name="SDCTRL" pid="9"> | |
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434 | <register name="configuration" addOffset="0"> | |
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435 | <bitField size="1" name="Refresh" offset="31" mode="3" desc="SDRAM refresh. If set, the SDRAM refresh will be enabled."/> | |
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436 | <bitField size="1" name="tRP" offset="30" mode="3" desc="SDRAM tRP timing. tRP will be equal to 2 or 3 system clocks (0/1). When mobile SDRAM support is enabled, this bit also represent the MSB in the tRFC timing."/> | |
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437 | <bitField name="tRFC" size="3" offset="27" mode="3" desc="SDRAM tRFC timing. tRFC will be equal to 3 + field-value system clocks. When mobile SDRAM support is enabled, this field is extended with the bit 30."/> | |
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438 | <bitField name="tCD" size="1" offset="26" mode="3" desc="SDRAM CAS delay. Selects 2 or 3 cycle CAS delay (0/1). When changed, a LOAD-COMMAND-REGISTER command must be issued at the same time. Also sets RAS/CAS delay (tRCD)."/> | |
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439 | <bitField name="SDRAM bank size" offset="23" size="3" mode="3" desc="SDRAM banks size. Defines the decoded memory size for each SDRAM chip select: “000”= 4 Mbyte, “001”= 8 Mbyte, “010”= 16 Mbyte .... “111”= 512 Mbyte."/> | |
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440 | <bitField name="SDRAM col. size" offset="21" size="2" mode="3" desc="SDRAM column size. “00”=256, “01”=512, “10”=1024, “11”=2048 except when bit[25:23]= ̆111 ̆then ̆11 ̆=4096"/> | |
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441 | <bitField name="SDRAM command" offset="18" size="3" mode="3" desc="SDRAM command. Writing a non-zero value will generate an SDRAM command: “010”=PRE-CHARGE, “100”=AUTO-REFRESH, “110”=LOAD-COMMAND-REGISTER, “111”=LOAD-EXTENDED-COMMAND-REGISTER. The field is reset after command has been executed."/> | |
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442 | <bitField name="Page-Burst" offset="17" size="1" mode="3" desc="1 = pageburst is used for read operations, 0 = line burst of length 8 is used for read operations. (Only available when VHDL generic pageburst i set to 2)"/> | |
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443 | <bitField name="MS" offset="16" size="1" mode="3" desc="Mobile SDR support enabled. ‘1’ = Enabled, ‘0’ = Disabled (read-only)"/> | |
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444 | <bitField name="D64" offset="15" size="1" mode="3" desc="64-bit data bus (D64) - Reads ‘1’ if memory controller is configured for 64-bit data bus, otherwise‘0’. Read-only."/> | |
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445 | <bitField name="SDRAM refresh load value" offset="0" size="15" mode="3" desc="The period between each AUTO-REFRESH command - Calculated as follows: tREFRESH = ((reload value) + 1) / SYSCLK"/> | |
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446 | </register> | |
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447 | <register name="Power-Saving configuration" addOffset="4"> | |
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448 | </register> | |
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449 | </peripheral> | |
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433 | 450 | </soc> |
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434 | 451 | |
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435 | 452 | |
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436 | 453 | |
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437 | 454 | |
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438 | 455 | |
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439 | 456 | |
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440 | 457 | |
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441 | 458 | |
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442 | 459 | |
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