##// END OF EJS Templates
DEFAULT modulus, tbad, offset and shift in finetime...
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1 1 #ifndef FSW_PARAMS_H_INCLUDED
2 2 #define FSW_PARAMS_H_INCLUDED
3 3
4 4 #include "fsw_params_processing.h"
5 5 #include "fsw_params_nb_bytes.h"
6 6 #include "tm_byte_positions.h"
7 7 #include "ccsds_types.h"
8 #include "stdint.h"
8 9
9 10 #define GRSPW_DEVICE_NAME "/dev/grspw0"
10 11 #define UART_DEVICE_NAME "/dev/console"
11 12
12 13 //*******
13 14 // MACROS
14 15 #ifdef PRINT_MESSAGES_ON_CONSOLE
15 16 #define PRINTF(x) printf(x);
16 17 #define PRINTF1(x,y) printf(x,y);
17 18 #define PRINTF2(x,y,z) printf(x,y,z);
18 19 #else
19 20 #define PRINTF(x) ;
20 21 #define PRINTF1(x,y) ;
21 22 #define PRINTF2(x,y,z) ;
22 23 #endif
23 24
24 25 #ifdef BOOT_MESSAGES
25 26 #define BOOT_PRINTF(x) printf(x);
26 27 #define BOOT_PRINTF1(x,y) printf(x,y);
27 28 #define BOOT_PRINTF2(x,y,z) printf(x,y,z);
28 29 #else
29 30 #define BOOT_PRINTF(x) ;
30 31 #define BOOT_PRINTF1(x,y) ;
31 32 #define BOOT_PRINTF2(x,y,z) ;
32 33 #endif
33 34
34 35 #ifdef DEBUG_MESSAGES
35 36 #define DEBUG_PRINTF(x) printf(x);
36 37 #define DEBUG_PRINTF1(x,y) printf(x,y);
37 38 #define DEBUG_PRINTF2(x,y,z) printf(x,y,z);
38 39 #else
39 40 #define DEBUG_PRINTF(x) ;
40 41 #define DEBUG_PRINTF1(x,y) ;
41 42 #define DEBUG_PRINTF2(x,y,z) ;
42 43 #endif
43 44
44 45 #define CONST_65536 65536 // 2^16
45 46 #define CONST_2048 2048 // 2^11
46 47 #define CONST_512 512 // 2^9
47 48 #define CONST_256 256 // 2^8
48 49 #define CONST_128 128 // 2^7
49 50 #define UINT8_MAX 255
50 51
51 52 #define FLOAT_MSBYTE 0
52 53 #define FLOAT_LSBYTE 3
53 54 #define BITS_PER_BYTE 8
54 55 #define INIT_FLOAT 0.
55 56 #define INIT_CHAR 0x00
56 57 #define INIT_INT 0
57 58 #define INT8_ALL_F 0xff
58 59 #define INT16_ALL_F 0xffff
59 60 #define INT32_ALL_F 0xffffffff
60 61 #define INT32_ALL_0 0x00000000
61 62 #define SHIFT_1_BYTE 8
62 63 #define SHIFT_2_BYTES 16
63 64 #define SHIFT_3_BYTES 24
64 65 #define SHIFT_4_BYTES 32
65 66 #define SHIFT_5_BYTES 40
66 67 #define SHIFT_2_BITS 2
67 68 #define SHIFT_3_BITS 3
68 69 #define SHIFT_4_BITS 4
69 70 #define SHIFT_5_BITS 5
70 71 #define SHIFT_6_BITS 6
71 72 #define SHIFT_7_BITS 7
72 73 #define BYTE_0 0
73 74 #define BYTE_1 1
74 75 #define BYTE_2 2
75 76 #define BYTE_3 3
76 77 #define BYTE_4 4
77 78 #define BYTE_5 5
78 79 #define BYTE_6 6
79 80 #define BYTE_7 7
80 81 #define BYTE0_MASK 0xff00
81 82 #define BYTE1_MASK 0x00ff
82 83
83 84 enum lfr_transition_type_t{
84 85 TRANSITION_NOT_SPECIFIC,
85 86 TRANSITION_NORM_TO_S1,
86 87 TRANSITION_NORM_TO_S2,
87 88 TRANSITION_S1_TO_NORM,
88 89 TRANSITION_S2_TO_NORM,
89 90 TRANSITION_S1_TO_S2,
90 91 TRANSITION_S2_TO_S1
91 92 };
92 93
93 94 typedef struct ring_node
94 95 {
95 96 struct ring_node *previous;
96 97 struct ring_node *next;
97 98 unsigned int sid;
98 99 unsigned int coarseTime;
99 100 unsigned int fineTime;
100 101 int buffer_address;
101 102 unsigned int status;
102 103 } ring_node;
103 104
104 105 //************************
105 106 // flight software version
106 107 // this parameters is handled by the Qt project options
107 108
108 109 #define NB_PACKETS_PER_GROUP_OF_CWF 8 // 8 packets containing 336 blk
109 110 #define NB_PACKETS_PER_GROUP_OF_CWF_LIGHT 4 // 4 packets containing 672 blk
110 111 #define NB_SAMPLES_PER_SNAPSHOT 2688 // 336 * 8 = 672 * 4 = 2688
111 112 #define TIME_OFFSET 2
112 113 #define TIME_OFFSET_IN_BYTES 8
113 114 //#define WAVEFORM_EXTENDED_HEADER_OFFSET 22
114 115 #define NB_BYTES_SWF_BLK (2 * 6)
115 116 #define NB_WORDS_SWF_BLK 3
116 117 #define NB_BYTES_CWF3_LIGHT_BLK 6
117 118 //#define WFRM_INDEX_OF_LAST_PACKET 6 // waveforms are transmitted in groups of 2048 blocks, 6 packets of 340 and 1 of 8
118 119 #define NB_RING_NODES_F0 3 // AT LEAST 3
119 120 #define NB_RING_NODES_F1 5 // AT LEAST 3
120 121 #define NB_RING_NODES_F2 5 // AT LEAST 3
121 122 #define NB_RING_NODES_F3 3 // AT LEAST 3
122 123
123 124 //**********
124 125 // LFR MODES
125 126 #define LFR_MODE_STANDBY 0
126 127 #define LFR_MODE_NORMAL 1
127 128 #define LFR_MODE_BURST 2
128 129 #define LFR_MODE_SBM1 3
129 130 #define LFR_MODE_SBM2 4
130 131
131 132 #define TDS_MODE_LFM 5
132 133 #define TDS_MODE_STANDBY 0
133 134 #define TDS_MODE_NORMAL 1
134 135 #define TDS_MODE_BURST 2
135 136 #define TDS_MODE_SBM1 3
136 137 #define TDS_MODE_SBM2 4
137 138
138 139 #define THR_MODE_STANDBY 0
139 140 #define THR_MODE_NORMAL 1
140 141 #define THR_MODE_BURST 2
141 142
142 143 #define RTEMS_EVENT_MODE_STANDBY RTEMS_EVENT_0
143 144 #define RTEMS_EVENT_MODE_NORMAL RTEMS_EVENT_1
144 145 #define RTEMS_EVENT_MODE_BURST RTEMS_EVENT_2
145 146 #define RTEMS_EVENT_MODE_SBM1 RTEMS_EVENT_3
146 147 #define RTEMS_EVENT_MODE_SBM2 RTEMS_EVENT_4
147 148 #define RTEMS_EVENT_MODE_NORM_S1_S2 RTEMS_EVENT_5
148 149 #define RTEMS_EVENT_NORM_BP1_F0 RTEMS_EVENT_6
149 150 #define RTEMS_EVENT_NORM_BP2_F0 RTEMS_EVENT_7
150 151 #define RTEMS_EVENT_NORM_ASM_F0 RTEMS_EVENT_8 // ASM only in NORM mode
151 152 #define RTEMS_EVENT_NORM_BP1_F1 RTEMS_EVENT_9
152 153 #define RTEMS_EVENT_NORM_BP2_F1 RTEMS_EVENT_10
153 154 #define RTEMS_EVENT_NORM_ASM_F1 RTEMS_EVENT_11 // ASM only in NORM mode
154 155 #define RTEMS_EVENT_NORM_BP1_F2 RTEMS_EVENT_12
155 156 #define RTEMS_EVENT_NORM_BP2_F2 RTEMS_EVENT_13
156 157 #define RTEMS_EVENT_NORM_ASM_F2 RTEMS_EVENT_14 // ASM only in NORM mode
157 158 #define RTEMS_EVENT_SBM_BP1_F0 RTEMS_EVENT_15
158 159 #define RTEMS_EVENT_SBM_BP2_F0 RTEMS_EVENT_16
159 160 #define RTEMS_EVENT_SBM_BP1_F1 RTEMS_EVENT_17
160 161 #define RTEMS_EVENT_SBM_BP2_F1 RTEMS_EVENT_18
161 162 #define RTEMS_EVENT_BURST_BP1_F0 RTEMS_EVENT_19
162 163 #define RTEMS_EVENT_BURST_BP2_F0 RTEMS_EVENT_20
163 164 #define RTEMS_EVENT_BURST_BP1_F1 RTEMS_EVENT_21
164 165 #define RTEMS_EVENT_BURST_BP2_F1 RTEMS_EVENT_22
165 166 #define RTEMS_EVENT_SWF_RESYNCH RTEMS_EVENT_23
166 167
167 168 //********************************************
168 169 //********************************************
169 170 // LFR PARAMETERS: DEFAULT, MIN AND MAX VALUES
170 171
171 172 #define DEFAULT_LAST_VALID_TRANSITION_DATE 0xffffffff
172 173
173 174 // COMMON
174 175 #define DEFAULT_SY_LFR_COMMON0 0x00
175 176 #define DEFAULT_SY_LFR_COMMON1 0x20 // default value bw sp0 sp1 r0 r1 r2 = 1 0 0 0 0 0
176 177
177 178 // NORM
178 179 #define DFLT_SY_LFR_N_SWF_L 2048 // nb sample
179 180 #define DFLT_SY_LFR_N_SWF_P 300 // sec
180 181 #define MIN_SY_LFR_N_SWF_P 22 // sec
181 182 #define DFLT_SY_LFR_N_ASM_P 3600 // sec
182 183 #define DFLT_SY_LFR_N_BP_P0 4 // sec
183 184 #define DFLT_SY_LFR_N_BP_P1 20 // sec
184 185 #define DFLT_SY_LFR_N_CWF_LONG_F3 0 // 0 => production of light continuous waveforms at f3
185 186 #define MIN_DELTA_SNAPSHOT 16 // sec
186 187
187 188 // BURST
188 189 #define DEFAULT_SY_LFR_B_BP_P0 1 // sec
189 190 #define DEFAULT_SY_LFR_B_BP_P1 5 // sec
190 191
191 192 // SBM1
192 193 #define S1_BP_P0_SCALE 0.25
193 194 #define DEFAULT_SY_LFR_S1_BP_P0 1 // 0.25 sec
194 195 #define DEFAULT_SY_LFR_S1_BP_P1 1 // sec
195 196
196 197 // SBM2
197 198 #define DEFAULT_SY_LFR_S2_BP_P0 1 // sec
198 199 #define DEFAULT_SY_LFR_S2_BP_P1 5 // sec
199 200
200 201 // ADDITIONAL PARAMETERS
201 202 #define TIME_BETWEEN_TWO_SWF_PACKETS 30 // nb x 10 ms => 300 ms
202 203 #define TIME_BETWEEN_TWO_CWF3_PACKETS 1000 // nb x 10 ms => 10 s
203 204
204 205 // STATUS WORD
205 206 #define DEFAULT_STATUS_WORD_BYTE0 0x0d // [0000] [1] [101] mode 4 bits / SPW enabled 1 bit / state is run 3 bits
206 207
207 208 #define DEFAULT_STATUS_WORD_BYTE1 0x00
208 209 // TC_LFR_LOAD_FILTER_PAR
209 210 #define MIN_PAS_FILTER_MODULUS 4
210 211 #define MAX_PAS_FILTER_MODULUS 8
211 212 #define MIN_PAS_FILTER_TBAD 0.0
212 213 #define MAX_PAS_FILTER_TBAD 4.0
213 214 #define MIN_PAS_FILTER_OFFSET 0
214 215 #define MAX_PAS_FILTER_OFFSET 7
215 216 #define MIN_PAS_FILTER_SHIFT 0.0
216 217 #define MAX_PAS_FILTER_SHIFT 1.0
217 218 #define MIN_SY_LFR_SC_RW_DELTA_F 0
218 219 #define MIN_SY_LFR_RW_K 0
219 220 #define MIN_SY_LFR_RW_F 0
220 221 //
221 222 #define SY_LFR_DPU_CONNECT_TIMEOUT 100 // 100 * 10 ms = 1 s
222 223 #define SY_LFR_DPU_CONNECT_ATTEMPT 3
223 224 //****************************
224 225
225 226 //*****************************
226 227 // APB REGISTERS BASE ADDRESSES
227 228 #define REGS_ADDR_APBUART 0x80000100
228 229 #define REGS_ADDR_GPTIMER 0x80000300
229 230 #define REGS_ADDR_GRSPW 0x80000500
230 231 #define APB_OFFSET_GRSPW_STATUS_REGISTER 0x04
231 232 #define APB_OFFSET_GRSPW_TIME_REGISTER 0x14
232 233 #define REGS_ADDR_TIME_MANAGEMENT 0x80000600
233 234 #define REGS_ADDR_GRGPIO 0x80000b00
234 235
235 236 #define REGS_ADDR_SPECTRAL_MATRIX 0x80000f00
236 237 #define REGS_ADDR_WAVEFORM_PICKER 0x80000f54 // PDB >= 0.1.28
237 238 #define APB_OFFSET_VHDL_REV 0xb0
238 239 #define REGS_ADDR_VHDL_VERSION 0x80000ff0
239 240
240 241 #define APBUART_CTRL_REG_MASK_DB 0xfffff7ff
241 242 #define APBUART_CTRL_REG_MASK_TE 0x00000002
242 243 // scaler value = system_clock_frequency / ( baud_rate * 8 ) - 1
243 244 #define APBUART_SCALER_RELOAD_VALUE 0x00000050 // 25 MHz => about 38400
244 245
245 246 //**********
246 247 // IRQ LINES
247 248 #define IRQ_GPTIMER_WATCHDOG 9
248 249 #define IRQ_SPARC_GPTIMER_WATCHDOG 0x19 // see sparcv8.pdf p.76 for interrupt levels
249 250 #define IRQ_WAVEFORM_PICKER 14
250 251 #define IRQ_SPARC_WAVEFORM_PICKER 0x1e // see sparcv8.pdf p.76 for interrupt levels
251 252 #define IRQ_SPECTRAL_MATRIX 6
252 253 #define IRQ_SPARC_SPECTRAL_MATRIX 0x16 // see sparcv8.pdf p.76 for interrupt levels
253 254
254 255 //*****
255 256 // TIME
256 257 #define CLKDIV_WATCHDOG (10000000 - 1) // 10.0s => 10 000 000
257 258 #define TIMER_WATCHDOG 1
258 259 #define WATCHDOG_PERIOD 100 // 1s
259 260 #define HK_PERIOD 100 // 100 * 10ms => 1s
260 261 #define AVGV_PERIOD 6 // 6 * 10ms => 60ms (1 / 16 = 62.5ms)
261 262 #define SY_LFR_TIME_SYN_TIMEOUT_in_ticks 200 // 200 * 10 ms = 2 s
262 263 #define HK_SYNC_WAIT 10 // 10 * 10 ms = 100 ms
263 264 #define SPW_LINK_WAIT 10 // 10 * 10 ms = 100 ms
264 265 #define TIMECODE_TIMER_TIMEOUT 120 // 120 * 10 ms = 1.2 s
265 266 #define TIMECODE_TIMER_TIMEOUT_INIT 200 // 200 * 10 ms = 2.0 s
266 267 #define TIMECODE_MASK 0x3f // 0011 1111
267 268
268 269 //**********
269 270 // LPP CODES
270 271 #define LFR_SUCCESSFUL 0
271 272 #define LFR_DEFAULT 1
272 273 #define LFR_EXE_ERROR 2
273 274 #define LFR_DEFAULT_ALT -1
274 275
275 276 //******
276 277 // RTEMS
277 278 #define STACK_SIZE_MULT 2
278 279
279 280 #define TASKID_AVGV 0
280 281 #define TASKID_RECV 1
281 282 #define TASKID_ACTN 2
282 283 #define TASKID_SPIQ 3
283 284 #define TASKID_LOAD 4
284 285 #define TASKID_AVF0 5
285 286 #define TASKID_SWBD 6
286 287 #define TASKID_WFRM 7
287 288 #define TASKID_DUMB 8
288 289 #define TASKID_HOUS 9
289 290 #define TASKID_PRC0 10
290 291 #define TASKID_CWF3 11
291 292 #define TASKID_CWF2 12
292 293 #define TASKID_CWF1 13
293 294 #define TASKID_SEND 14
294 295 #define TASKID_LINK 15
295 296 #define TASKID_AVF1 16
296 297 #define TASKID_PRC1 17
297 298 #define TASKID_AVF2 18
298 299 #define TASKID_PRC2 19
299 300
300 301 #define TASK_PRIORITY_SPIQ 5
301 302 #define TASK_PRIORITY_LINK 20
302 303 #define TASK_PRIORITY_AVGV 25
303 304 #define TASK_PRIORITY_HOUS 30
304 305 #define TASK_PRIORITY_CWF1 35 // CWF1 and CWF2 are never running together
305 306 #define TASK_PRIORITY_CWF2 35 //
306 307 #define TASK_PRIORITY_SWBD 37 // SWBD has a lower priority than WFRM, this is to extract the snapshot before sending it
307 308 #define TASK_PRIORITY_WFRM 40
308 309 #define TASK_PRIORITY_CWF3 40 // there is a printf in this function, be careful with its priority wrt CWF1
309 310 #define TASK_PRIORITY_SEND 45
310 311 #define TASK_PRIORITY_RECV 50
311 312 #define TASK_PRIORITY_ACTN 50
312 313 #define TASK_PRIORITY_AVF0 60
313 314 #define TASK_PRIORITY_AVF1 70
314 315 #define TASK_PRIORITY_PRC0 100
315 316 #define TASK_PRIORITY_PRC1 100
316 317 #define TASK_PRIORITY_AVF2 110
317 318 #define TASK_PRIORITY_PRC2 110
318 319 #define TASK_PRIORITY_LOAD 190
319 320 #define TASK_PRIORITY_DUMB 200
320 321
321 322 #define MSG_QUEUE_COUNT_RECV 10
322 323 #define MSG_QUEUE_COUNT_SEND 50
323 324 #define MSG_QUEUE_COUNT_PRC0 10
324 325 #define MSG_QUEUE_COUNT_PRC1 10
325 326 #define MSG_QUEUE_COUNT_PRC2 5
326 327 #define MSG_QUEUE_SIZE_SEND 812 // 808 + 4 => TM_LFR_SCIENCE_BURST_BP2_F1
327 328 #define ACTION_MSG_SPW_IOCTL_SEND_SIZE 24 // hlen *hdr dlen *data sent options
328 329 #define MSG_QUEUE_SIZE_PRC0 36 // two pointers, one rtems_event + 6 integers
329 330 #define MSG_QUEUE_SIZE_PRC1 36 // two pointers, one rtems_event + 6 integers
330 331 #define MSG_QUEUE_SIZE_PRC2 36 // two pointers, one rtems_event + 6 integers
331 332
332 333 #define QUEUE_RECV 0
333 334 #define QUEUE_SEND 1
334 335 #define QUEUE_PRC0 2
335 336 #define QUEUE_PRC1 3
336 337 #define QUEUE_PRC2 4
337 338
338 339 #define CPU_USAGE_REPORT_PERIOD 6 // * 10 s = period
339 340
340 341 struct param_local_str{
341 342 unsigned int local_sbm1_nb_cwf_sent;
342 343 unsigned int local_sbm1_nb_cwf_max;
343 344 unsigned int local_sbm2_nb_cwf_sent;
344 345 unsigned int local_sbm2_nb_cwf_max;
345 346 };
346 347
347 348 //************
348 349 // FBINS MASKS
349 350
350 351 #define BYTES_PER_FBINS_MASK 16
351 352
352 353 typedef struct {
353 354 unsigned char merged_fbins_mask_f0[BYTES_PER_FBINS_MASK];
354 355 unsigned char merged_fbins_mask_f1[BYTES_PER_FBINS_MASK];
355 356 unsigned char merged_fbins_mask_f2[BYTES_PER_FBINS_MASK];
356 357 } fbins_masks_t;
357 358
358 359 #define DEFAULT_SY_LFR_PAS_FILTER_ENABLED 0
359 360 #define DEFAULT_SY_LFR_PAS_FILTER_MODULUS 4
360 361 #define DEFAULT_SY_LFR_PAS_FILTER_TBAD 1.0
361 362 #define DEFAULT_SY_LFR_PAS_FILTER_OFFSET 0
362 363 #define DEFAULT_SY_LFR_PAS_FILTER_SHIFT 0.5
364 #define DEFAULT_MODULUS 262144 // 65536 * 4
365 #define DEFAULT_TBAD 65536 // 65536
366 #define DEFAULT_OFFSET 0 // 65536 * 0
367 #define DEFAULT_SHIFT 32768 // 65536 / 2
363 368 #define DEFAULT_SY_LFR_SC_RW_DELTA_F 0.045
364 369 #define DEFAULT_SY_LFR_RW_K1 1.
365 370 #define DEFAULT_SY_LFR_RW_K2 8.
366 371 #define DEFAULT_SY_LFR_RW_K3 24.
367 372 #define DEFAULT_SY_LFR_RW_K4 48.
368 373
369 374 typedef struct{
370 375 unsigned char spare_sy_lfr_pas_filter_enabled;
371 unsigned char sy_lfr_pas_filter_modulus;
372 376 float sy_lfr_pas_filter_tbad;
373 unsigned char sy_lfr_pas_filter_offset;
374 377 float sy_lfr_pas_filter_shift;
378 uint64_t modulus_in_finetime;
379 uint64_t tbad_in_finetime;
380 uint64_t offset_in_finetime;
381 uint64_t shift_in_finetime;
375 382 float sy_lfr_sc_rw_delta_f;
376 383 // rw1_k
377 384 float sy_lfr_rw1_k1;
378 385 float sy_lfr_rw1_k2;
379 386 float sy_lfr_rw1_k3;
380 387 float sy_lfr_rw1_k4;
381 388 // rw2_k
382 389 float sy_lfr_rw2_k1;
383 390 float sy_lfr_rw2_k2;
384 391 float sy_lfr_rw2_k3;
385 392 float sy_lfr_rw2_k4;
386 393 // rw3_k
387 394 float sy_lfr_rw3_k1;
388 395 float sy_lfr_rw3_k2;
389 396 float sy_lfr_rw3_k3;
390 397 float sy_lfr_rw3_k4;
391 398 // rw4_k
392 399 float sy_lfr_rw4_k1;
393 400 float sy_lfr_rw4_k2;
394 401 float sy_lfr_rw4_k3;
395 402 float sy_lfr_rw4_k4;
396 403 } filterPar_t;
397 404
398 405 typedef struct{
399 406 // rw1_f
400 407 float cp_rpw_sc_rw1_f1;
401 408 float cp_rpw_sc_rw1_f2;
402 409 float cp_rpw_sc_rw1_f3;
403 410 float cp_rpw_sc_rw1_f4;
404 411 // rw2_f
405 412 float cp_rpw_sc_rw2_f1;
406 413 float cp_rpw_sc_rw2_f2;
407 414 float cp_rpw_sc_rw2_f3;
408 415 float cp_rpw_sc_rw2_f4;
409 416 // rw3_f
410 417 float cp_rpw_sc_rw3_f1;
411 418 float cp_rpw_sc_rw3_f2;
412 419 float cp_rpw_sc_rw3_f3;
413 420 float cp_rpw_sc_rw3_f4;
414 421 // rw4_f
415 422 float cp_rpw_sc_rw4_f1;
416 423 float cp_rpw_sc_rw4_f2;
417 424 float cp_rpw_sc_rw4_f3;
418 425 float cp_rpw_sc_rw4_f4;
419 426 } rw_f_t;
420 427
421 428 #define MATRIX_IS_POLLUTED 0
422 429 #define MATRIX_IS_NOT_POLLUTED 1
423 430 #define ACQUISITION_DURATION_F0 683 // 256 / 24576 * 65536
424 431 #define ACQUISITION_DURATION_F1 4096 // 256 / 4096 * 65536
425 432 #define ACQUISITION_DURATION_F2 65536 // 256 / 256 * 65536
426 433 #define HALF_ACQUISITION_DURATION_F0 341 // 256 / 24576 * 65536 / 2
427 434 #define HALF_ACQUISITION_DURATION_F1 2048 // 256 / 4096 * 65536 / 2
428 435 #define HALF_ACQUISITION_DURATION_F2 32768 // 256 / 256 * 65536 / 2
429 436
430 437 #endif // FSW_PARAMS_H_INCLUDED
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