##// END OF EJS Templates
min values for rw_delta_f and rw_k added
paul -
r64:e01ac8bd125a R3++
parent child
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@@ -1,421 +1,424
1 #ifndef FSW_PARAMS_H_INCLUDED
1 #ifndef FSW_PARAMS_H_INCLUDED
2 #define FSW_PARAMS_H_INCLUDED
2 #define FSW_PARAMS_H_INCLUDED
3
3
4 #include "fsw_params_processing.h"
4 #include "fsw_params_processing.h"
5 #include "fsw_params_nb_bytes.h"
5 #include "fsw_params_nb_bytes.h"
6 #include "tm_byte_positions.h"
6 #include "tm_byte_positions.h"
7 #include "ccsds_types.h"
7 #include "ccsds_types.h"
8
8
9 #define GRSPW_DEVICE_NAME "/dev/grspw0"
9 #define GRSPW_DEVICE_NAME "/dev/grspw0"
10 #define UART_DEVICE_NAME "/dev/console"
10 #define UART_DEVICE_NAME "/dev/console"
11
11
12 //*******
12 //*******
13 // MACROS
13 // MACROS
14 #ifdef PRINT_MESSAGES_ON_CONSOLE
14 #ifdef PRINT_MESSAGES_ON_CONSOLE
15 #define PRINTF(x) printf(x);
15 #define PRINTF(x) printf(x);
16 #define PRINTF1(x,y) printf(x,y);
16 #define PRINTF1(x,y) printf(x,y);
17 #define PRINTF2(x,y,z) printf(x,y,z);
17 #define PRINTF2(x,y,z) printf(x,y,z);
18 #else
18 #else
19 #define PRINTF(x) ;
19 #define PRINTF(x) ;
20 #define PRINTF1(x,y) ;
20 #define PRINTF1(x,y) ;
21 #define PRINTF2(x,y,z) ;
21 #define PRINTF2(x,y,z) ;
22 #endif
22 #endif
23
23
24 #ifdef BOOT_MESSAGES
24 #ifdef BOOT_MESSAGES
25 #define BOOT_PRINTF(x) printf(x);
25 #define BOOT_PRINTF(x) printf(x);
26 #define BOOT_PRINTF1(x,y) printf(x,y);
26 #define BOOT_PRINTF1(x,y) printf(x,y);
27 #define BOOT_PRINTF2(x,y,z) printf(x,y,z);
27 #define BOOT_PRINTF2(x,y,z) printf(x,y,z);
28 #else
28 #else
29 #define BOOT_PRINTF(x) ;
29 #define BOOT_PRINTF(x) ;
30 #define BOOT_PRINTF1(x,y) ;
30 #define BOOT_PRINTF1(x,y) ;
31 #define BOOT_PRINTF2(x,y,z) ;
31 #define BOOT_PRINTF2(x,y,z) ;
32 #endif
32 #endif
33
33
34 #ifdef DEBUG_MESSAGES
34 #ifdef DEBUG_MESSAGES
35 #define DEBUG_PRINTF(x) printf(x);
35 #define DEBUG_PRINTF(x) printf(x);
36 #define DEBUG_PRINTF1(x,y) printf(x,y);
36 #define DEBUG_PRINTF1(x,y) printf(x,y);
37 #define DEBUG_PRINTF2(x,y,z) printf(x,y,z);
37 #define DEBUG_PRINTF2(x,y,z) printf(x,y,z);
38 #else
38 #else
39 #define DEBUG_PRINTF(x) ;
39 #define DEBUG_PRINTF(x) ;
40 #define DEBUG_PRINTF1(x,y) ;
40 #define DEBUG_PRINTF1(x,y) ;
41 #define DEBUG_PRINTF2(x,y,z) ;
41 #define DEBUG_PRINTF2(x,y,z) ;
42 #endif
42 #endif
43
43
44 #define CONST_65536 65536 // 2^16
44 #define CONST_65536 65536 // 2^16
45 #define CONST_2048 2048 // 2^11
45 #define CONST_2048 2048 // 2^11
46 #define CONST_512 512 // 2^9
46 #define CONST_512 512 // 2^9
47 #define CONST_256 256 // 2^8
47 #define CONST_256 256 // 2^8
48 #define CONST_128 128 // 2^7
48 #define CONST_128 128 // 2^7
49 #define UINT8_MAX 255
49 #define UINT8_MAX 255
50
50
51 #define FLOAT_MSBYTE 0
51 #define FLOAT_MSBYTE 0
52 #define FLOAT_LSBYTE 3
52 #define FLOAT_LSBYTE 3
53 #define BITS_PER_BYTE 8
53 #define BITS_PER_BYTE 8
54 #define INIT_FLOAT 0.
54 #define INIT_FLOAT 0.
55 #define INIT_CHAR 0x00
55 #define INIT_CHAR 0x00
56 #define INT8_ALL_F 0xff
56 #define INT8_ALL_F 0xff
57 #define INT16_ALL_F 0xffff
57 #define INT16_ALL_F 0xffff
58 #define INT32_ALL_F 0xffffffff
58 #define INT32_ALL_F 0xffffffff
59 #define INT32_ALL_0 0x00000000
59 #define INT32_ALL_0 0x00000000
60 #define SHIFT_1_BYTE 8
60 #define SHIFT_1_BYTE 8
61 #define SHIFT_2_BYTES 16
61 #define SHIFT_2_BYTES 16
62 #define SHIFT_3_BYTES 24
62 #define SHIFT_3_BYTES 24
63 #define SHIFT_4_BYTES 32
63 #define SHIFT_4_BYTES 32
64 #define SHIFT_5_BYTES 40
64 #define SHIFT_5_BYTES 40
65 #define SHIFT_2_BITS 2
65 #define SHIFT_2_BITS 2
66 #define SHIFT_3_BITS 3
66 #define SHIFT_3_BITS 3
67 #define SHIFT_4_BITS 4
67 #define SHIFT_4_BITS 4
68 #define SHIFT_5_BITS 5
68 #define SHIFT_5_BITS 5
69 #define SHIFT_6_BITS 6
69 #define SHIFT_6_BITS 6
70 #define SHIFT_7_BITS 7
70 #define SHIFT_7_BITS 7
71 #define BYTE_0 0
71 #define BYTE_0 0
72 #define BYTE_1 1
72 #define BYTE_1 1
73 #define BYTE_2 2
73 #define BYTE_2 2
74 #define BYTE_3 3
74 #define BYTE_3 3
75 #define BYTE_4 4
75 #define BYTE_4 4
76 #define BYTE_5 5
76 #define BYTE_5 5
77 #define BYTE_6 6
77 #define BYTE_6 6
78 #define BYTE_7 7
78 #define BYTE_7 7
79 #define BYTE0_MASK 0xff00
79 #define BYTE0_MASK 0xff00
80 #define BYTE1_MASK 0x00ff
80 #define BYTE1_MASK 0x00ff
81
81
82 enum lfr_transition_type_t{
82 enum lfr_transition_type_t{
83 TRANSITION_NOT_SPECIFIC,
83 TRANSITION_NOT_SPECIFIC,
84 TRANSITION_NORM_TO_S1,
84 TRANSITION_NORM_TO_S1,
85 TRANSITION_NORM_TO_S2,
85 TRANSITION_NORM_TO_S2,
86 TRANSITION_S1_TO_NORM,
86 TRANSITION_S1_TO_NORM,
87 TRANSITION_S2_TO_NORM,
87 TRANSITION_S2_TO_NORM,
88 TRANSITION_S1_TO_S2,
88 TRANSITION_S1_TO_S2,
89 TRANSITION_S2_TO_S1
89 TRANSITION_S2_TO_S1
90 };
90 };
91
91
92 typedef struct ring_node
92 typedef struct ring_node
93 {
93 {
94 struct ring_node *previous;
94 struct ring_node *previous;
95 struct ring_node *next;
95 struct ring_node *next;
96 unsigned int sid;
96 unsigned int sid;
97 unsigned int coarseTime;
97 unsigned int coarseTime;
98 unsigned int fineTime;
98 unsigned int fineTime;
99 int buffer_address;
99 int buffer_address;
100 unsigned int status;
100 unsigned int status;
101 } ring_node;
101 } ring_node;
102
102
103 //************************
103 //************************
104 // flight software version
104 // flight software version
105 // this parameters is handled by the Qt project options
105 // this parameters is handled by the Qt project options
106
106
107 #define NB_PACKETS_PER_GROUP_OF_CWF 8 // 8 packets containing 336 blk
107 #define NB_PACKETS_PER_GROUP_OF_CWF 8 // 8 packets containing 336 blk
108 #define NB_PACKETS_PER_GROUP_OF_CWF_LIGHT 4 // 4 packets containing 672 blk
108 #define NB_PACKETS_PER_GROUP_OF_CWF_LIGHT 4 // 4 packets containing 672 blk
109 #define NB_SAMPLES_PER_SNAPSHOT 2688 // 336 * 8 = 672 * 4 = 2688
109 #define NB_SAMPLES_PER_SNAPSHOT 2688 // 336 * 8 = 672 * 4 = 2688
110 #define TIME_OFFSET 2
110 #define TIME_OFFSET 2
111 #define TIME_OFFSET_IN_BYTES 8
111 #define TIME_OFFSET_IN_BYTES 8
112 //#define WAVEFORM_EXTENDED_HEADER_OFFSET 22
112 //#define WAVEFORM_EXTENDED_HEADER_OFFSET 22
113 #define NB_BYTES_SWF_BLK (2 * 6)
113 #define NB_BYTES_SWF_BLK (2 * 6)
114 #define NB_WORDS_SWF_BLK 3
114 #define NB_WORDS_SWF_BLK 3
115 #define NB_BYTES_CWF3_LIGHT_BLK 6
115 #define NB_BYTES_CWF3_LIGHT_BLK 6
116 //#define WFRM_INDEX_OF_LAST_PACKET 6 // waveforms are transmitted in groups of 2048 blocks, 6 packets of 340 and 1 of 8
116 //#define WFRM_INDEX_OF_LAST_PACKET 6 // waveforms are transmitted in groups of 2048 blocks, 6 packets of 340 and 1 of 8
117 #define NB_RING_NODES_F0 3 // AT LEAST 3
117 #define NB_RING_NODES_F0 3 // AT LEAST 3
118 #define NB_RING_NODES_F1 5 // AT LEAST 3
118 #define NB_RING_NODES_F1 5 // AT LEAST 3
119 #define NB_RING_NODES_F2 5 // AT LEAST 3
119 #define NB_RING_NODES_F2 5 // AT LEAST 3
120 #define NB_RING_NODES_F3 3 // AT LEAST 3
120 #define NB_RING_NODES_F3 3 // AT LEAST 3
121
121
122 //**********
122 //**********
123 // LFR MODES
123 // LFR MODES
124 #define LFR_MODE_STANDBY 0
124 #define LFR_MODE_STANDBY 0
125 #define LFR_MODE_NORMAL 1
125 #define LFR_MODE_NORMAL 1
126 #define LFR_MODE_BURST 2
126 #define LFR_MODE_BURST 2
127 #define LFR_MODE_SBM1 3
127 #define LFR_MODE_SBM1 3
128 #define LFR_MODE_SBM2 4
128 #define LFR_MODE_SBM2 4
129
129
130 #define TDS_MODE_LFM 5
130 #define TDS_MODE_LFM 5
131 #define TDS_MODE_STANDBY 0
131 #define TDS_MODE_STANDBY 0
132 #define TDS_MODE_NORMAL 1
132 #define TDS_MODE_NORMAL 1
133 #define TDS_MODE_BURST 2
133 #define TDS_MODE_BURST 2
134 #define TDS_MODE_SBM1 3
134 #define TDS_MODE_SBM1 3
135 #define TDS_MODE_SBM2 4
135 #define TDS_MODE_SBM2 4
136
136
137 #define THR_MODE_STANDBY 0
137 #define THR_MODE_STANDBY 0
138 #define THR_MODE_NORMAL 1
138 #define THR_MODE_NORMAL 1
139 #define THR_MODE_BURST 2
139 #define THR_MODE_BURST 2
140
140
141 #define RTEMS_EVENT_MODE_STANDBY RTEMS_EVENT_0
141 #define RTEMS_EVENT_MODE_STANDBY RTEMS_EVENT_0
142 #define RTEMS_EVENT_MODE_NORMAL RTEMS_EVENT_1
142 #define RTEMS_EVENT_MODE_NORMAL RTEMS_EVENT_1
143 #define RTEMS_EVENT_MODE_BURST RTEMS_EVENT_2
143 #define RTEMS_EVENT_MODE_BURST RTEMS_EVENT_2
144 #define RTEMS_EVENT_MODE_SBM1 RTEMS_EVENT_3
144 #define RTEMS_EVENT_MODE_SBM1 RTEMS_EVENT_3
145 #define RTEMS_EVENT_MODE_SBM2 RTEMS_EVENT_4
145 #define RTEMS_EVENT_MODE_SBM2 RTEMS_EVENT_4
146 #define RTEMS_EVENT_MODE_NORM_S1_S2 RTEMS_EVENT_5
146 #define RTEMS_EVENT_MODE_NORM_S1_S2 RTEMS_EVENT_5
147 #define RTEMS_EVENT_NORM_BP1_F0 RTEMS_EVENT_6
147 #define RTEMS_EVENT_NORM_BP1_F0 RTEMS_EVENT_6
148 #define RTEMS_EVENT_NORM_BP2_F0 RTEMS_EVENT_7
148 #define RTEMS_EVENT_NORM_BP2_F0 RTEMS_EVENT_7
149 #define RTEMS_EVENT_NORM_ASM_F0 RTEMS_EVENT_8 // ASM only in NORM mode
149 #define RTEMS_EVENT_NORM_ASM_F0 RTEMS_EVENT_8 // ASM only in NORM mode
150 #define RTEMS_EVENT_NORM_BP1_F1 RTEMS_EVENT_9
150 #define RTEMS_EVENT_NORM_BP1_F1 RTEMS_EVENT_9
151 #define RTEMS_EVENT_NORM_BP2_F1 RTEMS_EVENT_10
151 #define RTEMS_EVENT_NORM_BP2_F1 RTEMS_EVENT_10
152 #define RTEMS_EVENT_NORM_ASM_F1 RTEMS_EVENT_11 // ASM only in NORM mode
152 #define RTEMS_EVENT_NORM_ASM_F1 RTEMS_EVENT_11 // ASM only in NORM mode
153 #define RTEMS_EVENT_NORM_BP1_F2 RTEMS_EVENT_12
153 #define RTEMS_EVENT_NORM_BP1_F2 RTEMS_EVENT_12
154 #define RTEMS_EVENT_NORM_BP2_F2 RTEMS_EVENT_13
154 #define RTEMS_EVENT_NORM_BP2_F2 RTEMS_EVENT_13
155 #define RTEMS_EVENT_NORM_ASM_F2 RTEMS_EVENT_14 // ASM only in NORM mode
155 #define RTEMS_EVENT_NORM_ASM_F2 RTEMS_EVENT_14 // ASM only in NORM mode
156 #define RTEMS_EVENT_SBM_BP1_F0 RTEMS_EVENT_15
156 #define RTEMS_EVENT_SBM_BP1_F0 RTEMS_EVENT_15
157 #define RTEMS_EVENT_SBM_BP2_F0 RTEMS_EVENT_16
157 #define RTEMS_EVENT_SBM_BP2_F0 RTEMS_EVENT_16
158 #define RTEMS_EVENT_SBM_BP1_F1 RTEMS_EVENT_17
158 #define RTEMS_EVENT_SBM_BP1_F1 RTEMS_EVENT_17
159 #define RTEMS_EVENT_SBM_BP2_F1 RTEMS_EVENT_18
159 #define RTEMS_EVENT_SBM_BP2_F1 RTEMS_EVENT_18
160 #define RTEMS_EVENT_BURST_BP1_F0 RTEMS_EVENT_19
160 #define RTEMS_EVENT_BURST_BP1_F0 RTEMS_EVENT_19
161 #define RTEMS_EVENT_BURST_BP2_F0 RTEMS_EVENT_20
161 #define RTEMS_EVENT_BURST_BP2_F0 RTEMS_EVENT_20
162 #define RTEMS_EVENT_BURST_BP1_F1 RTEMS_EVENT_21
162 #define RTEMS_EVENT_BURST_BP1_F1 RTEMS_EVENT_21
163 #define RTEMS_EVENT_BURST_BP2_F1 RTEMS_EVENT_22
163 #define RTEMS_EVENT_BURST_BP2_F1 RTEMS_EVENT_22
164 #define RTEMS_EVENT_SWF_RESYNCH RTEMS_EVENT_23
164 #define RTEMS_EVENT_SWF_RESYNCH RTEMS_EVENT_23
165
165
166 //********************************************
166 //********************************************
167 //********************************************
167 //********************************************
168 // LFR PARAMETERS: DEFAULT, MIN AND MAX VALUES
168 // LFR PARAMETERS: DEFAULT, MIN AND MAX VALUES
169
169
170 #define DEFAULT_LAST_VALID_TRANSITION_DATE 0xffffffff
170 #define DEFAULT_LAST_VALID_TRANSITION_DATE 0xffffffff
171
171
172 // COMMON
172 // COMMON
173 #define DEFAULT_SY_LFR_COMMON0 0x00
173 #define DEFAULT_SY_LFR_COMMON0 0x00
174 #define DEFAULT_SY_LFR_COMMON1 0x20 // default value bw sp0 sp1 r0 r1 r2 = 1 0 0 0 0 0
174 #define DEFAULT_SY_LFR_COMMON1 0x20 // default value bw sp0 sp1 r0 r1 r2 = 1 0 0 0 0 0
175
175
176 // NORM
176 // NORM
177 #define DFLT_SY_LFR_N_SWF_L 2048 // nb sample
177 #define DFLT_SY_LFR_N_SWF_L 2048 // nb sample
178 #define DFLT_SY_LFR_N_SWF_P 300 // sec
178 #define DFLT_SY_LFR_N_SWF_P 300 // sec
179 #define MIN_SY_LFR_N_SWF_P 22 // sec
179 #define MIN_SY_LFR_N_SWF_P 22 // sec
180 #define DFLT_SY_LFR_N_ASM_P 3600 // sec
180 #define DFLT_SY_LFR_N_ASM_P 3600 // sec
181 #define DFLT_SY_LFR_N_BP_P0 4 // sec
181 #define DFLT_SY_LFR_N_BP_P0 4 // sec
182 #define DFLT_SY_LFR_N_BP_P1 20 // sec
182 #define DFLT_SY_LFR_N_BP_P1 20 // sec
183 #define DFLT_SY_LFR_N_CWF_LONG_F3 0 // 0 => production of light continuous waveforms at f3
183 #define DFLT_SY_LFR_N_CWF_LONG_F3 0 // 0 => production of light continuous waveforms at f3
184 #define MIN_DELTA_SNAPSHOT 16 // sec
184 #define MIN_DELTA_SNAPSHOT 16 // sec
185
185
186 // BURST
186 // BURST
187 #define DEFAULT_SY_LFR_B_BP_P0 1 // sec
187 #define DEFAULT_SY_LFR_B_BP_P0 1 // sec
188 #define DEFAULT_SY_LFR_B_BP_P1 5 // sec
188 #define DEFAULT_SY_LFR_B_BP_P1 5 // sec
189
189
190 // SBM1
190 // SBM1
191 #define S1_BP_P0_SCALE 0.25
191 #define S1_BP_P0_SCALE 0.25
192 #define DEFAULT_SY_LFR_S1_BP_P0 1 // 0.25 sec
192 #define DEFAULT_SY_LFR_S1_BP_P0 1 // 0.25 sec
193 #define DEFAULT_SY_LFR_S1_BP_P1 1 // sec
193 #define DEFAULT_SY_LFR_S1_BP_P1 1 // sec
194
194
195 // SBM2
195 // SBM2
196 #define DEFAULT_SY_LFR_S2_BP_P0 1 // sec
196 #define DEFAULT_SY_LFR_S2_BP_P0 1 // sec
197 #define DEFAULT_SY_LFR_S2_BP_P1 5 // sec
197 #define DEFAULT_SY_LFR_S2_BP_P1 5 // sec
198
198
199 // ADDITIONAL PARAMETERS
199 // ADDITIONAL PARAMETERS
200 #define TIME_BETWEEN_TWO_SWF_PACKETS 30 // nb x 10 ms => 300 ms
200 #define TIME_BETWEEN_TWO_SWF_PACKETS 30 // nb x 10 ms => 300 ms
201 #define TIME_BETWEEN_TWO_CWF3_PACKETS 1000 // nb x 10 ms => 10 s
201 #define TIME_BETWEEN_TWO_CWF3_PACKETS 1000 // nb x 10 ms => 10 s
202
202
203 // STATUS WORD
203 // STATUS WORD
204 #define DEFAULT_STATUS_WORD_BYTE0 0x0d // [0000] [1] [101] mode 4 bits / SPW enabled 1 bit / state is run 3 bits
204 #define DEFAULT_STATUS_WORD_BYTE0 0x0d // [0000] [1] [101] mode 4 bits / SPW enabled 1 bit / state is run 3 bits
205
205
206 #define DEFAULT_STATUS_WORD_BYTE1 0x00
206 #define DEFAULT_STATUS_WORD_BYTE1 0x00
207 // TC_LFR_LOAD_FILTER_PAR
207 // TC_LFR_LOAD_FILTER_PAR
208 #define MIN_PAS_FILTER_MODULUS 4
208 #define MIN_PAS_FILTER_MODULUS 4
209 #define MAX_PAS_FILTER_MODULUS 8
209 #define MAX_PAS_FILTER_MODULUS 8
210 #define MIN_PAS_FILTER_TBAD 0.0
210 #define MIN_PAS_FILTER_TBAD 0.0
211 #define MAX_PAS_FILTER_TBAD 4.0
211 #define MAX_PAS_FILTER_TBAD 4.0
212 #define MIN_PAS_FILTER_OFFSET 0
212 #define MIN_PAS_FILTER_OFFSET 0
213 #define MAX_PAS_FILTER_OFFSET 7
213 #define MAX_PAS_FILTER_OFFSET 7
214 #define MIN_PAS_FILTER_SHIFT 0.0
214 #define MIN_PAS_FILTER_SHIFT 0.0
215 #define MAX_PAS_FILTER_SHIFT 1.0
215 #define MAX_PAS_FILTER_SHIFT 1.0
216 #define MIN_SY_LFR_SC_RW_DELTA_F 0
217 #define MIN_SY_LFR_RW_K 0
216 //
218 //
217 #define SY_LFR_DPU_CONNECT_TIMEOUT 100 // 100 * 10 ms = 1 s
219 #define SY_LFR_DPU_CONNECT_TIMEOUT 100 // 100 * 10 ms = 1 s
218 #define SY_LFR_DPU_CONNECT_ATTEMPT 3
220 #define SY_LFR_DPU_CONNECT_ATTEMPT 3
219 //****************************
221 //****************************
220
222
221 //*****************************
223 //*****************************
222 // APB REGISTERS BASE ADDRESSES
224 // APB REGISTERS BASE ADDRESSES
223 #define REGS_ADDR_APBUART 0x80000100
225 #define REGS_ADDR_APBUART 0x80000100
224 #define REGS_ADDR_GPTIMER 0x80000300
226 #define REGS_ADDR_GPTIMER 0x80000300
225 #define REGS_ADDR_GRSPW 0x80000500
227 #define REGS_ADDR_GRSPW 0x80000500
226 #define APB_OFFSET_GRSPW_STATUS_REGISTER 0x04
228 #define APB_OFFSET_GRSPW_STATUS_REGISTER 0x04
227 #define APB_OFFSET_GRSPW_TIME_REGISTER 0x14
229 #define APB_OFFSET_GRSPW_TIME_REGISTER 0x14
228 #define REGS_ADDR_TIME_MANAGEMENT 0x80000600
230 #define REGS_ADDR_TIME_MANAGEMENT 0x80000600
229 #define REGS_ADDR_GRGPIO 0x80000b00
231 #define REGS_ADDR_GRGPIO 0x80000b00
230
232
231 #define REGS_ADDR_SPECTRAL_MATRIX 0x80000f00
233 #define REGS_ADDR_SPECTRAL_MATRIX 0x80000f00
232 #define REGS_ADDR_WAVEFORM_PICKER 0x80000f54 // PDB >= 0.1.28
234 #define REGS_ADDR_WAVEFORM_PICKER 0x80000f54 // PDB >= 0.1.28
233 #define APB_OFFSET_VHDL_REV 0xb0
235 #define APB_OFFSET_VHDL_REV 0xb0
234 #define REGS_ADDR_VHDL_VERSION 0x80000ff0
236 #define REGS_ADDR_VHDL_VERSION 0x80000ff0
235
237
236 #define APBUART_CTRL_REG_MASK_DB 0xfffff7ff
238 #define APBUART_CTRL_REG_MASK_DB 0xfffff7ff
237 #define APBUART_CTRL_REG_MASK_TE 0x00000002
239 #define APBUART_CTRL_REG_MASK_TE 0x00000002
238 // scaler value = system_clock_frequency / ( baud_rate * 8 ) - 1
240 // scaler value = system_clock_frequency / ( baud_rate * 8 ) - 1
239 #define APBUART_SCALER_RELOAD_VALUE 0x00000050 // 25 MHz => about 38400
241 #define APBUART_SCALER_RELOAD_VALUE 0x00000050 // 25 MHz => about 38400
240
242
241 //**********
243 //**********
242 // IRQ LINES
244 // IRQ LINES
243 #define IRQ_GPTIMER_WATCHDOG 9
245 #define IRQ_GPTIMER_WATCHDOG 9
244 #define IRQ_SPARC_GPTIMER_WATCHDOG 0x19 // see sparcv8.pdf p.76 for interrupt levels
246 #define IRQ_SPARC_GPTIMER_WATCHDOG 0x19 // see sparcv8.pdf p.76 for interrupt levels
245 #define IRQ_WAVEFORM_PICKER 14
247 #define IRQ_WAVEFORM_PICKER 14
246 #define IRQ_SPARC_WAVEFORM_PICKER 0x1e // see sparcv8.pdf p.76 for interrupt levels
248 #define IRQ_SPARC_WAVEFORM_PICKER 0x1e // see sparcv8.pdf p.76 for interrupt levels
247 #define IRQ_SPECTRAL_MATRIX 6
249 #define IRQ_SPECTRAL_MATRIX 6
248 #define IRQ_SPARC_SPECTRAL_MATRIX 0x16 // see sparcv8.pdf p.76 for interrupt levels
250 #define IRQ_SPARC_SPECTRAL_MATRIX 0x16 // see sparcv8.pdf p.76 for interrupt levels
249
251
250 //*****
252 //*****
251 // TIME
253 // TIME
252 #define CLKDIV_WATCHDOG (10000000 - 1) // 10.0s => 10 000 000
254 #define CLKDIV_WATCHDOG (10000000 - 1) // 10.0s => 10 000 000
253 #define TIMER_WATCHDOG 1
255 #define TIMER_WATCHDOG 1
254 #define WATCHDOG_PERIOD 100 // 1s
256 #define WATCHDOG_PERIOD 100 // 1s
255 #define HK_PERIOD 100 // 100 * 10ms => 1s
257 #define HK_PERIOD 100 // 100 * 10ms => 1s
256 #define AVGV_PERIOD 6 // 6 * 10ms => 60ms (1 / 16 = 62.5ms)
258 #define AVGV_PERIOD 6 // 6 * 10ms => 60ms (1 / 16 = 62.5ms)
257 #define SY_LFR_TIME_SYN_TIMEOUT_in_ticks 200 // 200 * 10 ms = 2 s
259 #define SY_LFR_TIME_SYN_TIMEOUT_in_ticks 200 // 200 * 10 ms = 2 s
258 #define HK_SYNC_WAIT 10 // 10 * 10 ms = 100 ms
260 #define HK_SYNC_WAIT 10 // 10 * 10 ms = 100 ms
259 #define SPW_LINK_WAIT 10 // 10 * 10 ms = 100 ms
261 #define SPW_LINK_WAIT 10 // 10 * 10 ms = 100 ms
260 #define TIMECODE_TIMER_TIMEOUT 120 // 120 * 10 ms = 1.2 s
262 #define TIMECODE_TIMER_TIMEOUT 120 // 120 * 10 ms = 1.2 s
261 #define TIMECODE_TIMER_TIMEOUT_INIT 200 // 200 * 10 ms = 2.0 s
263 #define TIMECODE_TIMER_TIMEOUT_INIT 200 // 200 * 10 ms = 2.0 s
262 #define TIMECODE_MASK 0x3f // 0011 1111
264 #define TIMECODE_MASK 0x3f // 0011 1111
263
265
264 //**********
266 //**********
265 // LPP CODES
267 // LPP CODES
266 #define LFR_SUCCESSFUL 0
268 #define LFR_SUCCESSFUL 0
267 #define LFR_DEFAULT 1
269 #define LFR_DEFAULT 1
268 #define LFR_EXE_ERROR 2
270 #define LFR_EXE_ERROR 2
271 #define LFR_DEFAULT_ALT -1
269
272
270 //******
273 //******
271 // RTEMS
274 // RTEMS
272 #define STACK_SIZE_MULT 2
275 #define STACK_SIZE_MULT 2
273
276
274 #define TASKID_AVGV 0
277 #define TASKID_AVGV 0
275 #define TASKID_RECV 1
278 #define TASKID_RECV 1
276 #define TASKID_ACTN 2
279 #define TASKID_ACTN 2
277 #define TASKID_SPIQ 3
280 #define TASKID_SPIQ 3
278 #define TASKID_LOAD 4
281 #define TASKID_LOAD 4
279 #define TASKID_AVF0 5
282 #define TASKID_AVF0 5
280 #define TASKID_SWBD 6
283 #define TASKID_SWBD 6
281 #define TASKID_WFRM 7
284 #define TASKID_WFRM 7
282 #define TASKID_DUMB 8
285 #define TASKID_DUMB 8
283 #define TASKID_HOUS 9
286 #define TASKID_HOUS 9
284 #define TASKID_PRC0 10
287 #define TASKID_PRC0 10
285 #define TASKID_CWF3 11
288 #define TASKID_CWF3 11
286 #define TASKID_CWF2 12
289 #define TASKID_CWF2 12
287 #define TASKID_CWF1 13
290 #define TASKID_CWF1 13
288 #define TASKID_SEND 14
291 #define TASKID_SEND 14
289 #define TASKID_LINK 15
292 #define TASKID_LINK 15
290 #define TASKID_AVF1 16
293 #define TASKID_AVF1 16
291 #define TASKID_PRC1 17
294 #define TASKID_PRC1 17
292 #define TASKID_AVF2 18
295 #define TASKID_AVF2 18
293 #define TASKID_PRC2 19
296 #define TASKID_PRC2 19
294
297
295 #define TASK_PRIORITY_SPIQ 5
298 #define TASK_PRIORITY_SPIQ 5
296 #define TASK_PRIORITY_LINK 20
299 #define TASK_PRIORITY_LINK 20
297 #define TASK_PRIORITY_AVGV 25
300 #define TASK_PRIORITY_AVGV 25
298 #define TASK_PRIORITY_HOUS 30
301 #define TASK_PRIORITY_HOUS 30
299 #define TASK_PRIORITY_CWF1 35 // CWF1 and CWF2 are never running together
302 #define TASK_PRIORITY_CWF1 35 // CWF1 and CWF2 are never running together
300 #define TASK_PRIORITY_CWF2 35 //
303 #define TASK_PRIORITY_CWF2 35 //
301 #define TASK_PRIORITY_SWBD 37 // SWBD has a lower priority than WFRM, this is to extract the snapshot before sending it
304 #define TASK_PRIORITY_SWBD 37 // SWBD has a lower priority than WFRM, this is to extract the snapshot before sending it
302 #define TASK_PRIORITY_WFRM 40
305 #define TASK_PRIORITY_WFRM 40
303 #define TASK_PRIORITY_CWF3 40 // there is a printf in this function, be careful with its priority wrt CWF1
306 #define TASK_PRIORITY_CWF3 40 // there is a printf in this function, be careful with its priority wrt CWF1
304 #define TASK_PRIORITY_SEND 45
307 #define TASK_PRIORITY_SEND 45
305 #define TASK_PRIORITY_RECV 50
308 #define TASK_PRIORITY_RECV 50
306 #define TASK_PRIORITY_ACTN 50
309 #define TASK_PRIORITY_ACTN 50
307 #define TASK_PRIORITY_AVF0 60
310 #define TASK_PRIORITY_AVF0 60
308 #define TASK_PRIORITY_AVF1 70
311 #define TASK_PRIORITY_AVF1 70
309 #define TASK_PRIORITY_PRC0 100
312 #define TASK_PRIORITY_PRC0 100
310 #define TASK_PRIORITY_PRC1 100
313 #define TASK_PRIORITY_PRC1 100
311 #define TASK_PRIORITY_AVF2 110
314 #define TASK_PRIORITY_AVF2 110
312 #define TASK_PRIORITY_PRC2 110
315 #define TASK_PRIORITY_PRC2 110
313 #define TASK_PRIORITY_LOAD 190
316 #define TASK_PRIORITY_LOAD 190
314 #define TASK_PRIORITY_DUMB 200
317 #define TASK_PRIORITY_DUMB 200
315
318
316 #define MSG_QUEUE_COUNT_RECV 10
319 #define MSG_QUEUE_COUNT_RECV 10
317 #define MSG_QUEUE_COUNT_SEND 50
320 #define MSG_QUEUE_COUNT_SEND 50
318 #define MSG_QUEUE_COUNT_PRC0 10
321 #define MSG_QUEUE_COUNT_PRC0 10
319 #define MSG_QUEUE_COUNT_PRC1 10
322 #define MSG_QUEUE_COUNT_PRC1 10
320 #define MSG_QUEUE_COUNT_PRC2 5
323 #define MSG_QUEUE_COUNT_PRC2 5
321 #define MSG_QUEUE_SIZE_SEND 812 // 808 + 4 => TM_LFR_SCIENCE_BURST_BP2_F1
324 #define MSG_QUEUE_SIZE_SEND 812 // 808 + 4 => TM_LFR_SCIENCE_BURST_BP2_F1
322 #define ACTION_MSG_SPW_IOCTL_SEND_SIZE 24 // hlen *hdr dlen *data sent options
325 #define ACTION_MSG_SPW_IOCTL_SEND_SIZE 24 // hlen *hdr dlen *data sent options
323 #define MSG_QUEUE_SIZE_PRC0 36 // two pointers, one rtems_event + 6 integers
326 #define MSG_QUEUE_SIZE_PRC0 36 // two pointers, one rtems_event + 6 integers
324 #define MSG_QUEUE_SIZE_PRC1 36 // two pointers, one rtems_event + 6 integers
327 #define MSG_QUEUE_SIZE_PRC1 36 // two pointers, one rtems_event + 6 integers
325 #define MSG_QUEUE_SIZE_PRC2 36 // two pointers, one rtems_event + 6 integers
328 #define MSG_QUEUE_SIZE_PRC2 36 // two pointers, one rtems_event + 6 integers
326
329
327 #define QUEUE_RECV 0
330 #define QUEUE_RECV 0
328 #define QUEUE_SEND 1
331 #define QUEUE_SEND 1
329 #define QUEUE_PRC0 2
332 #define QUEUE_PRC0 2
330 #define QUEUE_PRC1 3
333 #define QUEUE_PRC1 3
331 #define QUEUE_PRC2 4
334 #define QUEUE_PRC2 4
332
335
333 #define CPU_USAGE_REPORT_PERIOD 6 // * 10 s = period
336 #define CPU_USAGE_REPORT_PERIOD 6 // * 10 s = period
334
337
335 struct param_local_str{
338 struct param_local_str{
336 unsigned int local_sbm1_nb_cwf_sent;
339 unsigned int local_sbm1_nb_cwf_sent;
337 unsigned int local_sbm1_nb_cwf_max;
340 unsigned int local_sbm1_nb_cwf_max;
338 unsigned int local_sbm2_nb_cwf_sent;
341 unsigned int local_sbm2_nb_cwf_sent;
339 unsigned int local_sbm2_nb_cwf_max;
342 unsigned int local_sbm2_nb_cwf_max;
340 };
343 };
341
344
342 //************
345 //************
343 // FBINS MASKS
346 // FBINS MASKS
344
347
345 #define BYTES_PER_FBINS_MASK 16
348 #define BYTES_PER_FBINS_MASK 16
346
349
347 typedef struct {
350 typedef struct {
348 unsigned char merged_fbins_mask_f0[BYTES_PER_FBINS_MASK];
351 unsigned char merged_fbins_mask_f0[BYTES_PER_FBINS_MASK];
349 unsigned char merged_fbins_mask_f1[BYTES_PER_FBINS_MASK];
352 unsigned char merged_fbins_mask_f1[BYTES_PER_FBINS_MASK];
350 unsigned char merged_fbins_mask_f2[BYTES_PER_FBINS_MASK];
353 unsigned char merged_fbins_mask_f2[BYTES_PER_FBINS_MASK];
351 } fbins_masks_t;
354 } fbins_masks_t;
352
355
353 #define DEFAULT_SY_LFR_PAS_FILTER_ENABLED 0
356 #define DEFAULT_SY_LFR_PAS_FILTER_ENABLED 0
354 #define DEFAULT_SY_LFR_PAS_FILTER_MODULUS 4
357 #define DEFAULT_SY_LFR_PAS_FILTER_MODULUS 4
355 #define DEFAULT_SY_LFR_PAS_FILTER_TBAD 1.0
358 #define DEFAULT_SY_LFR_PAS_FILTER_TBAD 1.0
356 #define DEFAULT_SY_LFR_PAS_FILTER_OFFSET 0
359 #define DEFAULT_SY_LFR_PAS_FILTER_OFFSET 0
357 #define DEFAULT_SY_LFR_PAS_FILTER_SHIFT 0.5
360 #define DEFAULT_SY_LFR_PAS_FILTER_SHIFT 0.5
358 #define DEFAULT_SY_LFR_SC_RW_DELTA_F 0.045
361 #define DEFAULT_SY_LFR_SC_RW_DELTA_F 0.045
359 #define DEFAULT_SY_LFR_RW_K1 1.
362 #define DEFAULT_SY_LFR_RW_K1 1.
360 #define DEFAULT_SY_LFR_RW_K2 8.
363 #define DEFAULT_SY_LFR_RW_K2 8.
361 #define DEFAULT_SY_LFR_RW_K3 24.
364 #define DEFAULT_SY_LFR_RW_K3 24.
362 #define DEFAULT_SY_LFR_RW_K4 48.
365 #define DEFAULT_SY_LFR_RW_K4 48.
363
366
364 typedef struct{
367 typedef struct{
365 unsigned char spare_sy_lfr_pas_filter_enabled;
368 unsigned char spare_sy_lfr_pas_filter_enabled;
366 unsigned char sy_lfr_pas_filter_modulus;
369 unsigned char sy_lfr_pas_filter_modulus;
367 float sy_lfr_pas_filter_tbad;
370 float sy_lfr_pas_filter_tbad;
368 unsigned char sy_lfr_pas_filter_offset;
371 unsigned char sy_lfr_pas_filter_offset;
369 float sy_lfr_pas_filter_shift;
372 float sy_lfr_pas_filter_shift;
370 float sy_lfr_sc_rw_delta_f;
373 float sy_lfr_sc_rw_delta_f;
371 // rw1_k
374 // rw1_k
372 float sy_lfr_rw1_k1;
375 float sy_lfr_rw1_k1;
373 float sy_lfr_rw1_k2;
376 float sy_lfr_rw1_k2;
374 float sy_lfr_rw1_k3;
377 float sy_lfr_rw1_k3;
375 float sy_lfr_rw1_k4;
378 float sy_lfr_rw1_k4;
376 // rw2_k
379 // rw2_k
377 float sy_lfr_rw2_k1;
380 float sy_lfr_rw2_k1;
378 float sy_lfr_rw2_k2;
381 float sy_lfr_rw2_k2;
379 float sy_lfr_rw2_k3;
382 float sy_lfr_rw2_k3;
380 float sy_lfr_rw2_k4;
383 float sy_lfr_rw2_k4;
381 // rw3_k
384 // rw3_k
382 float sy_lfr_rw3_k1;
385 float sy_lfr_rw3_k1;
383 float sy_lfr_rw3_k2;
386 float sy_lfr_rw3_k2;
384 float sy_lfr_rw3_k3;
387 float sy_lfr_rw3_k3;
385 float sy_lfr_rw3_k4;
388 float sy_lfr_rw3_k4;
386 // rw4_k
389 // rw4_k
387 float sy_lfr_rw4_k1;
390 float sy_lfr_rw4_k1;
388 float sy_lfr_rw4_k2;
391 float sy_lfr_rw4_k2;
389 float sy_lfr_rw4_k3;
392 float sy_lfr_rw4_k3;
390 float sy_lfr_rw4_k4;
393 float sy_lfr_rw4_k4;
391 } filterPar_t;
394 } filterPar_t;
392
395
393 typedef struct{
396 typedef struct{
394 // rw1_f
397 // rw1_f
395 float cp_rpw_sc_rw1_f1;
398 float cp_rpw_sc_rw1_f1;
396 float cp_rpw_sc_rw1_f2;
399 float cp_rpw_sc_rw1_f2;
397 float cp_rpw_sc_rw1_f3;
400 float cp_rpw_sc_rw1_f3;
398 float cp_rpw_sc_rw1_f4;
401 float cp_rpw_sc_rw1_f4;
399 // rw2_f
402 // rw2_f
400 float cp_rpw_sc_rw2_f1;
403 float cp_rpw_sc_rw2_f1;
401 float cp_rpw_sc_rw2_f2;
404 float cp_rpw_sc_rw2_f2;
402 float cp_rpw_sc_rw2_f3;
405 float cp_rpw_sc_rw2_f3;
403 float cp_rpw_sc_rw2_f4;
406 float cp_rpw_sc_rw2_f4;
404 // rw3_f
407 // rw3_f
405 float cp_rpw_sc_rw3_f1;
408 float cp_rpw_sc_rw3_f1;
406 float cp_rpw_sc_rw3_f2;
409 float cp_rpw_sc_rw3_f2;
407 float cp_rpw_sc_rw3_f3;
410 float cp_rpw_sc_rw3_f3;
408 float cp_rpw_sc_rw3_f4;
411 float cp_rpw_sc_rw3_f4;
409 // rw4_f
412 // rw4_f
410 float cp_rpw_sc_rw4_f1;
413 float cp_rpw_sc_rw4_f1;
411 float cp_rpw_sc_rw4_f2;
414 float cp_rpw_sc_rw4_f2;
412 float cp_rpw_sc_rw4_f3;
415 float cp_rpw_sc_rw4_f3;
413 float cp_rpw_sc_rw4_f4;
416 float cp_rpw_sc_rw4_f4;
414 } rw_f_t;
417 } rw_f_t;
415
418
416 #define NB_ACQUISITION_DURATION 3
419 #define NB_ACQUISITION_DURATION 3
417 #define ACQUISITION_DURATION_F0 683 // 256 / 24576 * 65536
420 #define ACQUISITION_DURATION_F0 683 // 256 / 24576 * 65536
418 #define ACQUISITION_DURATION_F1 4096 // 256 / 4096 * 65536
421 #define ACQUISITION_DURATION_F1 4096 // 256 / 4096 * 65536
419 #define ACQUISITION_DURATION_F2 65536 // 256 / 256 * 65536
422 #define ACQUISITION_DURATION_F2 65536 // 256 / 256 * 65536
420
423
421 #endif // FSW_PARAMS_H_INCLUDED
424 #endif // FSW_PARAMS_H_INCLUDED
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