##// END OF EJS Templates
HG_REPOSITORIES » LPP » INSTRUMENTATION » SOLO_LFR » lfr_common_headers
RSS
sync
paul -
r7:a8668a356692 default
parent child
Show More
Show file before | Show file after | Hide comments
@@ -1,260 +1,260
1 1 #ifndef FSW_PARAMS_H_INCLUDED
2 2 #define FSW_PARAMS_H_INCLUDED
3 3
4 4 #include "fsw_params_processing.h"
5 5 #include "fsw_params_nb_bytes.h"
6 6 #include "tm_byte_positions.h"
7 7 #include "ccsds_types.h"
8 8
9 9 #define GRSPW_DEVICE_NAME "/dev/grspw0"
10 10 #define UART_DEVICE_NAME "/dev/console"
11 11
12 12 typedef struct ring_node
13 13 {
14 14 struct ring_node *previous;
15 15 struct ring_node *next;
16 16 unsigned int sid;
17 17 unsigned int coarseTime;
18 18 unsigned int fineTime;
19 19 int buffer_address;
20 20 unsigned int status;
21 21 } ring_node;
22 22
23 23 //************************
24 24 // flight software version
25 25 // this parameters is handled by the Qt project options
26 26
27 27 #define NB_PACKETS_PER_GROUP_OF_CWF 8 // 8 packets containing 336 blk
28 28 #define NB_PACKETS_PER_GROUP_OF_CWF_LIGHT 4 // 4 packets containing 672 blk
29 29 #define NB_SAMPLES_PER_SNAPSHOT 2688 // 336 * 8 = 672 * 4 = 2688
30 30 #define TIME_OFFSET 2
31 31 #define TIME_OFFSET_IN_BYTES 8
32 32 //#define WAVEFORM_EXTENDED_HEADER_OFFSET 22
33 33 #define NB_BYTES_SWF_BLK (2 * 6)
34 34 #define NB_WORDS_SWF_BLK 3
35 35 #define NB_BYTES_CWF3_LIGHT_BLK 6
36 36 //#define WFRM_INDEX_OF_LAST_PACKET 6 // waveforms are transmitted in groups of 2048 blocks, 6 packets of 340 and 1 of 8
37 37 #define NB_RING_NODES_F0 3 // AT LEAST 3
38 38 #define NB_RING_NODES_F1 5 // AT LEAST 3
39 39 #define NB_RING_NODES_F2 5 // AT LEAST 3
40 40 #define NB_RING_NODES_F3 3 // AT LEAST 3
41 41
42 42 //**********
43 43 // LFR MODES
44 44 #define LFR_MODE_STANDBY 0
45 45 #define LFR_MODE_NORMAL 1
46 46 #define LFR_MODE_BURST 2
47 47 #define LFR_MODE_SBM1 3
48 48 #define LFR_MODE_SBM2 4
49 49
50 50 #define TDS_MODE_LFM 5
51 51 #define TDS_MODE_STANDBY 0
52 52 #define TDS_MODE_NORMAL 1
53 53 #define TDS_MODE_BURST 2
54 54 #define TDS_MODE_SBM1 3
55 55 #define TDS_MODE_SBM2 4
56 56
57 57 #define THR_MODE_STANDBY 0
58 58 #define THR_MODE_NORMAL 1
59 59 #define THR_MODE_BURST 2
60 60
61 61 #define RTEMS_EVENT_MODE_STANDBY RTEMS_EVENT_0
62 62 #define RTEMS_EVENT_MODE_NORMAL RTEMS_EVENT_1
63 63 #define RTEMS_EVENT_MODE_BURST RTEMS_EVENT_2
64 64 #define RTEMS_EVENT_MODE_SBM1 RTEMS_EVENT_3
65 65 #define RTEMS_EVENT_MODE_SBM2 RTEMS_EVENT_4
66 66 #define RTEMS_EVENT_MODE_SBM2_WFRM RTEMS_EVENT_5
67 67 #define RTEMS_EVENT_NORM_BP1_F0 RTEMS_EVENT_6
68 68 #define RTEMS_EVENT_NORM_BP2_F0 RTEMS_EVENT_7
69 69 #define RTEMS_EVENT_NORM_ASM_F0 RTEMS_EVENT_8 // ASM only in NORM mode
70 70 #define RTEMS_EVENT_NORM_BP1_F1 RTEMS_EVENT_9
71 71 #define RTEMS_EVENT_NORM_BP2_F1 RTEMS_EVENT_10
72 72 #define RTEMS_EVENT_NORM_ASM_F1 RTEMS_EVENT_11 // ASM only in NORM mode
73 73 #define RTEMS_EVENT_NORM_BP1_F2 RTEMS_EVENT_12
74 74 #define RTEMS_EVENT_NORM_BP2_F2 RTEMS_EVENT_13
75 75 #define RTEMS_EVENT_NORM_ASM_F2 RTEMS_EVENT_14 // ASM only in NORM mode
76 76 #define RTEMS_EVENT_SBM_BP1_F0 RTEMS_EVENT_15
77 77 #define RTEMS_EVENT_SBM_BP2_F0 RTEMS_EVENT_16
78 78 #define RTEMS_EVENT_SBM_BP1_F1 RTEMS_EVENT_17
79 79 #define RTEMS_EVENT_SBM_BP2_F1 RTEMS_EVENT_18
80 80 #define RTEMS_EVENT_BURST_BP1_F0 RTEMS_EVENT_19
81 81 #define RTEMS_EVENT_BURST_BP2_F0 RTEMS_EVENT_20
82 82 #define RTEMS_EVENT_BURST_BP1_F1 RTEMS_EVENT_21
83 83 #define RTEMS_EVENT_BURST_BP2_F1 RTEMS_EVENT_22
84 84
85 85 //****************************
86 86 // LFR DEFAULT MODE PARAMETERS
87 87 // COMMON
88 88 #define DEFAULT_SY_LFR_COMMON0 0x00
89 89 #define DEFAULT_SY_LFR_COMMON1 0x10 // default value 0 0 0 1 0 0 0 0
90 90 // NORM
91 91 #define DFLT_SY_LFR_N_SWF_L 2048 // nb sample
92 92 #define DFLT_SY_LFR_N_SWF_P 300 // sec
93 93 #define DFLT_SY_LFR_N_ASM_P 3600 // sec
94 94 #define DFLT_SY_LFR_N_BP_P0 4 // sec
95 95 #define DFLT_SY_LFR_N_BP_P1 20 // sec
96 96 #define DFLT_SY_LFR_N_CWF_LONG_F3 0 // 0 => production of light continuous waveforms at f3
97 97 #define MIN_DELTA_SNAPSHOT 16 // sec
98 98 // BURST
99 99 #define DEFAULT_SY_LFR_B_BP_P0 1 // sec
100 100 #define DEFAULT_SY_LFR_B_BP_P1 5 // sec
101 101 // SBM1
102 102 #define DEFAULT_SY_LFR_S1_BP_P0 1 // sec
103 103 #define DEFAULT_SY_LFR_S1_BP_P1 1 // sec
104 104 // SBM2
105 105 #define DEFAULT_SY_LFR_S2_BP_P0 1 // sec
106 106 #define DEFAULT_SY_LFR_S2_BP_P1 5 // sec
107 107 // ADDITIONAL PARAMETERS
108 108 #define TIME_BETWEEN_TWO_SWF_PACKETS 30 // nb x 10 ms => 300 ms
109 109 #define TIME_BETWEEN_TWO_CWF3_PACKETS 1000 // nb x 10 ms => 10 s
110 110 // STATUS WORD
111 111 #define DEFAULT_STATUS_WORD_BYTE0 0x0d // [0000] [1] [101] mode 4 bits / SPW enabled 1 bit / state is run 3 bits
112 112 #define DEFAULT_STATUS_WORD_BYTE1 0x00
113 113 //
114 114 #define SY_LFR_DPU_CONNECT_TIMEOUT 100 // 100 * 10 ms = 1 s
115 115 #define SY_LFR_DPU_CONNECT_ATTEMPT 3
116 116 //****************************
117 117
118 118 //*****************************
119 119 // APB REGISTERS BASE ADDRESSES
120 120 #define REGS_ADDR_APBUART 0x80000100
121 121 #define REGS_ADDR_GPTIMER 0x80000300
122 122 #define REGS_ADDR_GRSPW 0x80000500
123 123 #define REGS_ADDR_TIME_MANAGEMENT 0x80000600
124 124 #define REGS_ADDR_GRGPIO 0x80000b00
125 125
126 126 #define REGS_ADDR_SPECTRAL_MATRIX 0x80000f00
127 127 //#define REGS_ADDR_WAVEFORM_PICKER 0x80000f50
128 128 #define REGS_ADDR_WAVEFORM_PICKER 0x80000f54 // PDB >= 0.1.28
129 129 #define REGS_ADDR_VHDL_VERSION 0x80000ff0
130 130
131 131 #define APBUART_CTRL_REG_MASK_DB 0xfffff7ff
132 132 #define APBUART_CTRL_REG_MASK_TE 0x00000002
133 133 // scaler value = system_clock_frequency / ( baud_rate * 8 ) - 1
134 134 #define APBUART_SCALER_RELOAD_VALUE 0x00000050 // 25 MHz => about 38400
135 135
136 136 //**********
137 137 // IRQ LINES
138 138 #define IRQ_SM_SIMULATOR 9
139 139 #define IRQ_SPARC_SM_SIMULATOR 0x19 // see sparcv8.pdf p.76 for interrupt levels
140 140 #define IRQ_WAVEFORM_PICKER 14
141 141 #define IRQ_SPARC_WAVEFORM_PICKER 0x1e // see sparcv8.pdf p.76 for interrupt levels
142 142 #define IRQ_SPECTRAL_MATRIX 6
143 143 #define IRQ_SPARC_SPECTRAL_MATRIX 0x16 // see sparcv8.pdf p.76 for interrupt levels
144 144
145 145 //*****
146 146 // TIME
147 147 #define CLKDIV_SM_SIMULATOR (10416 - 1) // 10 ms => nominal is 1/96 = 0.010416667, 10417 - 1 = 10416
148 148 #define TIMER_SM_SIMULATOR 1
149 149 #define HK_PERIOD 100 // 100 * 10ms => 1s
150 150 #define SY_LFR_TIME_SYN_TIMEOUT_in_ms 2000
151 151 #define SY_LFR_TIME_SYN_TIMEOUT_in_ticks 200 // 200 * 10 ms = 2 s
152 152
153 153 //**********
154 154 // LPP CODES
155 155 #define LFR_SUCCESSFUL 0
156 156 #define LFR_DEFAULT 1
157 157 #define LFR_EXE_ERROR 2
158 158
159 159 //******
160 160 // RTEMS
161 161 #define TASKID_RECV 1
162 162 #define TASKID_ACTN 2
163 163 #define TASKID_SPIQ 3
164 164 #define TASKID_STAT 4
165 165 #define TASKID_AVF0 5
166 166 #define TASKID_SWBD 6
167 167 #define TASKID_WFRM 7
168 168 #define TASKID_DUMB 8
169 169 #define TASKID_HOUS 9
170 170 #define TASKID_PRC0 10
171 171 #define TASKID_CWF3 11
172 172 #define TASKID_CWF2 12
173 173 #define TASKID_CWF1 13
174 174 #define TASKID_SEND 14
175 175 #define TASKID_WTDG 15
176 176 #define TASKID_AVF1 16
177 177 #define TASKID_PRC1 17
178 178 #define TASKID_AVF2 18
179 179 #define TASKID_PRC2 19
180 180
181 181 #define TASK_PRIORITY_SPIQ 5
182 #define TASK_PRIORITY_WTDG 10
183 #define TASK_PRIORITY_SEND 15
184 #define TASK_PRIORITY_HOUS 20
185 #define TASK_PRIORITY_AVF0 25
186 #define TASK_PRIORITY_AVF1 30
187 #define TASK_PRIORITY_CWF1 35 // CWF1 and CWF2 are never running together
188 #define TASK_PRIORITY_CWF2 35 //
189 #define TASK_PRIORITY_SWBD 37 // SWBD has a lower priority than WFRM, this is to extract the snapshot before sending it
182 #define TASK_PRIORITY_WTDG 20
183 #define TASK_PRIORITY_HOUS 30
184 #define TASK_PRIORITY_CWF1 35 // CWF1 and CWF2 are never running together
185 #define TASK_PRIORITY_CWF2 35 //
186 #define TASK_PRIORITY_SWBD 37 // SWBD has a lower priority than WFRM, this is to extract the snapshot before sending it
190 187 #define TASK_PRIORITY_WFRM 40
191 #define TASK_PRIORITY_CWF3 40 // there is a printf in this function, be careful with its priority wrt CWF1
188 #define TASK_PRIORITY_AVF0 41
189 #define TASK_PRIORITY_AVF1 42
190 #define TASK_PRIORITY_SEND 45
191 #define TASK_PRIORITY_RECV 45
192 192 #define TASK_PRIORITY_ACTN 50
193 // The following tasks use the SEND mesage queue
193 194 #define TASK_PRIORITY_PRC0 100
194 195 #define TASK_PRIORITY_PRC1 100
195 #define TASK_PRIORITY_AVF2 110
196 #define TASK_PRIORITY_PRC2 110
197 #define TASK_PRIORITY_RECV 120
198 //#define TASK_PRIORITY_SEND 120
196 #define TASK_PRIORITY_PRC2 100
197 #define TASK_PRIORITY_AVF2 105
198 #define TASK_PRIORITY_CWF3 120 // there is a printf in this function, be careful with its priority wrt CWF1
199 199 #define TASK_PRIORITY_STAT 200
200 200 #define TASK_PRIORITY_DUMB 200
201 201
202 202 #define MSG_QUEUE_COUNT_RECV 10
203 203 #define MSG_QUEUE_COUNT_SEND 50
204 204 #define MSG_QUEUE_COUNT_PRC0 10
205 205 #define MSG_QUEUE_COUNT_PRC1 10
206 206 #define MSG_QUEUE_COUNT_PRC2 5
207 207 #define MSG_QUEUE_SIZE_SEND 810 // 806 + 4 => TM_LFR_SCIENCE_BURST_BP2_F1
208 208 #define ACTION_MSG_SPW_IOCTL_SEND_SIZE 24 // hlen *hdr dlen *data sent options
209 209 #define MSG_QUEUE_SIZE_PRC0 28 // two pointers, one rtems_event + 4 integers
210 210 #define MSG_QUEUE_SIZE_PRC1 28 // two pointers, one rtems_event + 4 integers
211 211 #define MSG_QUEUE_SIZE_PRC2 28 // two pointers, one rtems_event + 4 integers
212 212
213 213 #define QUEUE_RECV 0
214 214 #define QUEUE_SEND 1
215 215 #define QUEUE_PRC0 2
216 216 #define QUEUE_PRC1 3
217 217 #define QUEUE_PRC2 4
218 218
219 219 //*******
220 220 // MACROS
221 221 #ifdef PRINT_MESSAGES_ON_CONSOLE
222 222 #define PRINTF(x) printf(x);
223 223 #define PRINTF1(x,y) printf(x,y);
224 224 #define PRINTF2(x,y,z) printf(x,y,z);
225 225 #else
226 226 #define PRINTF(x) ;
227 227 #define PRINTF1(x,y) ;
228 228 #define PRINTF2(x,y,z) ;
229 229 #endif
230 230
231 231 #ifdef BOOT_MESSAGES
232 232 #define BOOT_PRINTF(x) printf(x);
233 233 #define BOOT_PRINTF1(x,y) printf(x,y);
234 234 #define BOOT_PRINTF2(x,y,z) printf(x,y,z);
235 235 #else
236 236 #define BOOT_PRINTF(x) ;
237 237 #define BOOT_PRINTF1(x,y) ;
238 238 #define BOOT_PRINTF2(x,y,z) ;
239 239 #endif
240 240
241 241 #ifdef DEBUG_MESSAGES
242 242 #define DEBUG_PRINTF(x) printf(x);
243 243 #define DEBUG_PRINTF1(x,y) printf(x,y);
244 244 #define DEBUG_PRINTF2(x,y,z) printf(x,y,z);
245 245 #else
246 246 #define DEBUG_PRINTF(x) ;
247 247 #define DEBUG_PRINTF1(x,y) ;
248 248 #define DEBUG_PRINTF2(x,y,z) ;
249 249 #endif
250 250
251 251 #define CPU_USAGE_REPORT_PERIOD 6 // * 10 s = period
252 252
253 253 struct param_local_str{
254 254 unsigned int local_sbm1_nb_cwf_sent;
255 255 unsigned int local_sbm1_nb_cwf_max;
256 256 unsigned int local_sbm2_nb_cwf_sent;
257 257 unsigned int local_sbm2_nb_cwf_max;
258 258 };
259 259
260 260 #endif // FSW_PARAMS_H_INCLUDED
Show file before | Show file after | Hide comments
@@ -1,77 +1,76
1 1 #ifndef FSW_PARAMS_PROCESSING_H
2 2 #define FSW_PARAMS_PROCESSING_H
3 3
4 4 #define NB_BINS_PER_SM 128
5 5 #define NB_VALUES_PER_SM 25
6 6 #define TOTAL_SIZE_SM 3200 // 25 * 128 = 0xC80
7 7 #define TOTAL_SIZE_NORM_BP1_F0 99 // 11 * 9 = 99
8 8 #define TOTAL_SIZE_NORM_BP1_F1 117 // 13 * 9 = 117
9 9 #define TOTAL_SIZE_NORM_BP1_F2 108 // 12 * 9 = 108
10 10 #define TOTAL_SIZE_SBM1_BP1_F0 198 // 22 * 9 = 198
11 11 // F0
12 12 #define NB_RING_NODES_SM_F0 20 // AT LEAST 8 due to the way the averaging is done
13 13 #define NB_RING_NODES_ASM_BURST_SBM_F0 10 // AT LEAST 3
14 14 #define NB_RING_NODES_ASM_NORM_F0 10 // AT LEAST 3
15 15 #define NB_RING_NODES_ASM_F0 3 // AT LEAST 3
16 16 // F1
17 17 #define NB_RING_NODES_SM_F1 12 // AT LEAST 8 due to the way the averaging is done
18 18 #define NB_RING_NODES_ASM_BURST_SBM_F1 5 // AT LEAST 3
19 19 #define NB_RING_NODES_ASM_NORM_F1 5 // AT LEAST 3
20 20 #define NB_RING_NODES_ASM_F1 3 // AT LEAST 3
21 21 // F2
22 22 #define NB_RING_NODES_SM_F2 5 // AT LEAST 3
23 23 #define NB_RING_NODES_ASM_BURST_SBM_F2 3 // AT LEAST 3
24 24 #define NB_RING_NODES_ASM_NORM_F2 3 // AT LEAST 3
25 25 #define NB_RING_NODES_ASM_F2 3 // AT LEAST 3
26 26 //
27 27 #define NB_BINS_PER_ASM_F0 88
28 28 #define NB_BINS_PER_PKT_ASM_F0 44
29 29 #define TOTAL_SIZE_ASM_F0_IN_BYTES 4400 // 25 * 88 * 2
30 30 #define ASM_F0_INDICE_START 17 // 88 bins
31 31 #define ASM_F0_INDICE_STOP 104 // 2 packets of 44 bins
32 32 //
33 33 #define NB_BINS_PER_ASM_F1 104
34 34 #define NB_BINS_PER_PKT_ASM_F1 52
35 35 #define TOTAL_SIZE_ASM_F1_IN_BYTES 5200 // 25 * 104 * 2
36 36 #define ASM_F1_INDICE_START 6 // 104 bins
37 37 #define ASM_F1_INDICE_STOP 109 // 2 packets of 52 bins
38 38 //
39 39 #define NB_BINS_PER_ASM_F2 96
40 40 #define NB_BINS_PER_PKT_ASM_F2 48
41 41 #define TOTAL_SIZE_ASM_F2_IN_BYTES 4800 // 25 * 96 * 2
42 42 #define ASM_F2_INDICE_START 7 // 96 bins
43 43 #define ASM_F2_INDICE_STOP 102 // 2 packets of 48 bins
44 44 //
45 45 #define NB_BINS_COMPRESSED_SM_F0 11
46 46 #define NB_BINS_COMPRESSED_SM_F1 13
47 47 #define NB_BINS_COMPRESSED_SM_F2 12
48 48 #define NB_BINS_COMPRESSED_SM_SBM_F0 22
49 49 #define NB_BINS_COMPRESSED_SM_SBM_F1 26
50 50 #define NB_BINS_COMPRESSED_SM_SBM_F2 24
51 51 //
52 52 #define NB_BYTES_PER_BP1 9
53 53 #define NB_BYTES_PER_BP2 30
54 54 //
55 55 #define NB_BINS_TO_AVERAGE_ASM_F0 8
56 56 #define NB_BINS_TO_AVERAGE_ASM_F1 8
57 57 #define NB_BINS_TO_AVERAGE_ASM_F2 8
58 58 #define NB_BINS_TO_AVERAGE_ASM_SBM_F0 4
59 59 #define NB_BINS_TO_AVERAGE_ASM_SBM_F1 4
60 60 #define NB_BINS_TO_AVERAGE_ASM_SBM_F2 4
61 61 //
62 62 #define TOTAL_SIZE_COMPRESSED_ASM_NORM_F0 275 // 11 * 25 WORDS
63 63 #define TOTAL_SIZE_COMPRESSED_ASM_NORM_F1 325 // 13 * 25 WORDS
64 64 #define TOTAL_SIZE_COMPRESSED_ASM_NORM_F2 300 // 12 * 25 WORDS
65 65 #define TOTAL_SIZE_COMPRESSED_ASM_SBM_F0 550 // 22 * 25 WORDS
66 66 #define TOTAL_SIZE_COMPRESSED_ASM_SBM_F1 650 // 26 * 25 WORDS
67 #define TOTAL_SIZE_COMPRESSED_ASM_SBM_F2 600 // 24 * 25 WORDS
68 67 #define TOTAL_SIZE_BP1_NORM_F0 99 // 9 * 11 UNSIGNED CHAR
69 68 #define TOTAL_SIZE_BP2_NORM_F0 330 // 30 * 11 UNSIGNED CHAR
70 69 #define TOTAL_SIZE_BP1_SBM_F0 198 // 9 * 22 UNSIGNED CHAR
71 70 // GENERAL
72 71 #define NB_SM_BEFORE_AVF0 8 // must be 8 due to the SM_average() function
73 72 #define NB_SM_BEFORE_AVF1 8 // must be 8 due to the SM_average() function
74 73 #define NB_SM_BEFORE_AVF2 1 // must be 1 due to the SM_average_f2() function
75 74
76 75 #endif // FSW_PARAMS_PROCESSING_H
77 76
General Comments 0
You need to be logged in to leave comments. Login now