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added range for rw_f and init value for int
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1 1 #ifndef FSW_PARAMS_H_INCLUDED
2 2 #define FSW_PARAMS_H_INCLUDED
3 3
4 4 #include "fsw_params_processing.h"
5 5 #include "fsw_params_nb_bytes.h"
6 6 #include "tm_byte_positions.h"
7 7 #include "ccsds_types.h"
8 8
9 9 #define GRSPW_DEVICE_NAME "/dev/grspw0"
10 10 #define UART_DEVICE_NAME "/dev/console"
11 11
12 12 //*******
13 13 // MACROS
14 14 #ifdef PRINT_MESSAGES_ON_CONSOLE
15 15 #define PRINTF(x) printf(x);
16 16 #define PRINTF1(x,y) printf(x,y);
17 17 #define PRINTF2(x,y,z) printf(x,y,z);
18 18 #else
19 19 #define PRINTF(x) ;
20 20 #define PRINTF1(x,y) ;
21 21 #define PRINTF2(x,y,z) ;
22 22 #endif
23 23
24 24 #ifdef BOOT_MESSAGES
25 25 #define BOOT_PRINTF(x) printf(x);
26 26 #define BOOT_PRINTF1(x,y) printf(x,y);
27 27 #define BOOT_PRINTF2(x,y,z) printf(x,y,z);
28 28 #else
29 29 #define BOOT_PRINTF(x) ;
30 30 #define BOOT_PRINTF1(x,y) ;
31 31 #define BOOT_PRINTF2(x,y,z) ;
32 32 #endif
33 33
34 34 #ifdef DEBUG_MESSAGES
35 35 #define DEBUG_PRINTF(x) printf(x);
36 36 #define DEBUG_PRINTF1(x,y) printf(x,y);
37 37 #define DEBUG_PRINTF2(x,y,z) printf(x,y,z);
38 38 #else
39 39 #define DEBUG_PRINTF(x) ;
40 40 #define DEBUG_PRINTF1(x,y) ;
41 41 #define DEBUG_PRINTF2(x,y,z) ;
42 42 #endif
43 43
44 44 #define CONST_65536 65536 // 2^16
45 45 #define CONST_2048 2048 // 2^11
46 46 #define CONST_512 512 // 2^9
47 47 #define CONST_256 256 // 2^8
48 48 #define CONST_128 128 // 2^7
49 49 #define UINT8_MAX 255
50 50
51 51 #define FLOAT_MSBYTE 0
52 52 #define FLOAT_LSBYTE 3
53 53 #define BITS_PER_BYTE 8
54 54 #define INIT_FLOAT 0.
55 55 #define INIT_CHAR 0x00
56 #define INIT_INT 0
56 57 #define INT8_ALL_F 0xff
57 58 #define INT16_ALL_F 0xffff
58 59 #define INT32_ALL_F 0xffffffff
59 60 #define INT32_ALL_0 0x00000000
60 61 #define SHIFT_1_BYTE 8
61 62 #define SHIFT_2_BYTES 16
62 63 #define SHIFT_3_BYTES 24
63 64 #define SHIFT_4_BYTES 32
64 65 #define SHIFT_5_BYTES 40
65 66 #define SHIFT_2_BITS 2
66 67 #define SHIFT_3_BITS 3
67 68 #define SHIFT_4_BITS 4
68 69 #define SHIFT_5_BITS 5
69 70 #define SHIFT_6_BITS 6
70 71 #define SHIFT_7_BITS 7
71 72 #define BYTE_0 0
72 73 #define BYTE_1 1
73 74 #define BYTE_2 2
74 75 #define BYTE_3 3
75 76 #define BYTE_4 4
76 77 #define BYTE_5 5
77 78 #define BYTE_6 6
78 79 #define BYTE_7 7
79 80 #define BYTE0_MASK 0xff00
80 81 #define BYTE1_MASK 0x00ff
81 82
82 83 enum lfr_transition_type_t{
83 84 TRANSITION_NOT_SPECIFIC,
84 85 TRANSITION_NORM_TO_S1,
85 86 TRANSITION_NORM_TO_S2,
86 87 TRANSITION_S1_TO_NORM,
87 88 TRANSITION_S2_TO_NORM,
88 89 TRANSITION_S1_TO_S2,
89 90 TRANSITION_S2_TO_S1
90 91 };
91 92
92 93 typedef struct ring_node
93 94 {
94 95 struct ring_node *previous;
95 96 struct ring_node *next;
96 97 unsigned int sid;
97 98 unsigned int coarseTime;
98 99 unsigned int fineTime;
99 100 int buffer_address;
100 101 unsigned int status;
101 102 } ring_node;
102 103
103 104 //************************
104 105 // flight software version
105 106 // this parameters is handled by the Qt project options
106 107
107 108 #define NB_PACKETS_PER_GROUP_OF_CWF 8 // 8 packets containing 336 blk
108 109 #define NB_PACKETS_PER_GROUP_OF_CWF_LIGHT 4 // 4 packets containing 672 blk
109 110 #define NB_SAMPLES_PER_SNAPSHOT 2688 // 336 * 8 = 672 * 4 = 2688
110 111 #define TIME_OFFSET 2
111 112 #define TIME_OFFSET_IN_BYTES 8
112 113 //#define WAVEFORM_EXTENDED_HEADER_OFFSET 22
113 114 #define NB_BYTES_SWF_BLK (2 * 6)
114 115 #define NB_WORDS_SWF_BLK 3
115 116 #define NB_BYTES_CWF3_LIGHT_BLK 6
116 117 //#define WFRM_INDEX_OF_LAST_PACKET 6 // waveforms are transmitted in groups of 2048 blocks, 6 packets of 340 and 1 of 8
117 118 #define NB_RING_NODES_F0 3 // AT LEAST 3
118 119 #define NB_RING_NODES_F1 5 // AT LEAST 3
119 120 #define NB_RING_NODES_F2 5 // AT LEAST 3
120 121 #define NB_RING_NODES_F3 3 // AT LEAST 3
121 122
122 123 //**********
123 124 // LFR MODES
124 125 #define LFR_MODE_STANDBY 0
125 126 #define LFR_MODE_NORMAL 1
126 127 #define LFR_MODE_BURST 2
127 128 #define LFR_MODE_SBM1 3
128 129 #define LFR_MODE_SBM2 4
129 130
130 131 #define TDS_MODE_LFM 5
131 132 #define TDS_MODE_STANDBY 0
132 133 #define TDS_MODE_NORMAL 1
133 134 #define TDS_MODE_BURST 2
134 135 #define TDS_MODE_SBM1 3
135 136 #define TDS_MODE_SBM2 4
136 137
137 138 #define THR_MODE_STANDBY 0
138 139 #define THR_MODE_NORMAL 1
139 140 #define THR_MODE_BURST 2
140 141
141 142 #define RTEMS_EVENT_MODE_STANDBY RTEMS_EVENT_0
142 143 #define RTEMS_EVENT_MODE_NORMAL RTEMS_EVENT_1
143 144 #define RTEMS_EVENT_MODE_BURST RTEMS_EVENT_2
144 145 #define RTEMS_EVENT_MODE_SBM1 RTEMS_EVENT_3
145 146 #define RTEMS_EVENT_MODE_SBM2 RTEMS_EVENT_4
146 147 #define RTEMS_EVENT_MODE_NORM_S1_S2 RTEMS_EVENT_5
147 148 #define RTEMS_EVENT_NORM_BP1_F0 RTEMS_EVENT_6
148 149 #define RTEMS_EVENT_NORM_BP2_F0 RTEMS_EVENT_7
149 150 #define RTEMS_EVENT_NORM_ASM_F0 RTEMS_EVENT_8 // ASM only in NORM mode
150 151 #define RTEMS_EVENT_NORM_BP1_F1 RTEMS_EVENT_9
151 152 #define RTEMS_EVENT_NORM_BP2_F1 RTEMS_EVENT_10
152 153 #define RTEMS_EVENT_NORM_ASM_F1 RTEMS_EVENT_11 // ASM only in NORM mode
153 154 #define RTEMS_EVENT_NORM_BP1_F2 RTEMS_EVENT_12
154 155 #define RTEMS_EVENT_NORM_BP2_F2 RTEMS_EVENT_13
155 156 #define RTEMS_EVENT_NORM_ASM_F2 RTEMS_EVENT_14 // ASM only in NORM mode
156 157 #define RTEMS_EVENT_SBM_BP1_F0 RTEMS_EVENT_15
157 158 #define RTEMS_EVENT_SBM_BP2_F0 RTEMS_EVENT_16
158 159 #define RTEMS_EVENT_SBM_BP1_F1 RTEMS_EVENT_17
159 160 #define RTEMS_EVENT_SBM_BP2_F1 RTEMS_EVENT_18
160 161 #define RTEMS_EVENT_BURST_BP1_F0 RTEMS_EVENT_19
161 162 #define RTEMS_EVENT_BURST_BP2_F0 RTEMS_EVENT_20
162 163 #define RTEMS_EVENT_BURST_BP1_F1 RTEMS_EVENT_21
163 164 #define RTEMS_EVENT_BURST_BP2_F1 RTEMS_EVENT_22
164 165 #define RTEMS_EVENT_SWF_RESYNCH RTEMS_EVENT_23
165 166
166 167 //********************************************
167 168 //********************************************
168 169 // LFR PARAMETERS: DEFAULT, MIN AND MAX VALUES
169 170
170 171 #define DEFAULT_LAST_VALID_TRANSITION_DATE 0xffffffff
171 172
172 173 // COMMON
173 174 #define DEFAULT_SY_LFR_COMMON0 0x00
174 175 #define DEFAULT_SY_LFR_COMMON1 0x20 // default value bw sp0 sp1 r0 r1 r2 = 1 0 0 0 0 0
175 176
176 177 // NORM
177 178 #define DFLT_SY_LFR_N_SWF_L 2048 // nb sample
178 179 #define DFLT_SY_LFR_N_SWF_P 300 // sec
179 180 #define MIN_SY_LFR_N_SWF_P 22 // sec
180 181 #define DFLT_SY_LFR_N_ASM_P 3600 // sec
181 182 #define DFLT_SY_LFR_N_BP_P0 4 // sec
182 183 #define DFLT_SY_LFR_N_BP_P1 20 // sec
183 184 #define DFLT_SY_LFR_N_CWF_LONG_F3 0 // 0 => production of light continuous waveforms at f3
184 185 #define MIN_DELTA_SNAPSHOT 16 // sec
185 186
186 187 // BURST
187 188 #define DEFAULT_SY_LFR_B_BP_P0 1 // sec
188 189 #define DEFAULT_SY_LFR_B_BP_P1 5 // sec
189 190
190 191 // SBM1
191 192 #define S1_BP_P0_SCALE 0.25
192 193 #define DEFAULT_SY_LFR_S1_BP_P0 1 // 0.25 sec
193 194 #define DEFAULT_SY_LFR_S1_BP_P1 1 // sec
194 195
195 196 // SBM2
196 197 #define DEFAULT_SY_LFR_S2_BP_P0 1 // sec
197 198 #define DEFAULT_SY_LFR_S2_BP_P1 5 // sec
198 199
199 200 // ADDITIONAL PARAMETERS
200 201 #define TIME_BETWEEN_TWO_SWF_PACKETS 30 // nb x 10 ms => 300 ms
201 202 #define TIME_BETWEEN_TWO_CWF3_PACKETS 1000 // nb x 10 ms => 10 s
202 203
203 204 // STATUS WORD
204 205 #define DEFAULT_STATUS_WORD_BYTE0 0x0d // [0000] [1] [101] mode 4 bits / SPW enabled 1 bit / state is run 3 bits
205 206
206 207 #define DEFAULT_STATUS_WORD_BYTE1 0x00
207 208 // TC_LFR_LOAD_FILTER_PAR
208 209 #define MIN_PAS_FILTER_MODULUS 4
209 210 #define MAX_PAS_FILTER_MODULUS 8
210 211 #define MIN_PAS_FILTER_TBAD 0.0
211 212 #define MAX_PAS_FILTER_TBAD 4.0
212 213 #define MIN_PAS_FILTER_OFFSET 0
213 214 #define MAX_PAS_FILTER_OFFSET 7
214 215 #define MIN_PAS_FILTER_SHIFT 0.0
215 216 #define MAX_PAS_FILTER_SHIFT 1.0
216 217 #define MIN_SY_LFR_SC_RW_DELTA_F 0
217 218 #define MIN_SY_LFR_RW_K 0
219 #define MIN_SY_LFR_RW_F 0
218 220 //
219 221 #define SY_LFR_DPU_CONNECT_TIMEOUT 100 // 100 * 10 ms = 1 s
220 222 #define SY_LFR_DPU_CONNECT_ATTEMPT 3
221 223 //****************************
222 224
223 225 //*****************************
224 226 // APB REGISTERS BASE ADDRESSES
225 227 #define REGS_ADDR_APBUART 0x80000100
226 228 #define REGS_ADDR_GPTIMER 0x80000300
227 229 #define REGS_ADDR_GRSPW 0x80000500
228 230 #define APB_OFFSET_GRSPW_STATUS_REGISTER 0x04
229 231 #define APB_OFFSET_GRSPW_TIME_REGISTER 0x14
230 232 #define REGS_ADDR_TIME_MANAGEMENT 0x80000600
231 233 #define REGS_ADDR_GRGPIO 0x80000b00
232 234
233 235 #define REGS_ADDR_SPECTRAL_MATRIX 0x80000f00
234 236 #define REGS_ADDR_WAVEFORM_PICKER 0x80000f54 // PDB >= 0.1.28
235 237 #define APB_OFFSET_VHDL_REV 0xb0
236 238 #define REGS_ADDR_VHDL_VERSION 0x80000ff0
237 239
238 240 #define APBUART_CTRL_REG_MASK_DB 0xfffff7ff
239 241 #define APBUART_CTRL_REG_MASK_TE 0x00000002
240 242 // scaler value = system_clock_frequency / ( baud_rate * 8 ) - 1
241 243 #define APBUART_SCALER_RELOAD_VALUE 0x00000050 // 25 MHz => about 38400
242 244
243 245 //**********
244 246 // IRQ LINES
245 247 #define IRQ_GPTIMER_WATCHDOG 9
246 248 #define IRQ_SPARC_GPTIMER_WATCHDOG 0x19 // see sparcv8.pdf p.76 for interrupt levels
247 249 #define IRQ_WAVEFORM_PICKER 14
248 250 #define IRQ_SPARC_WAVEFORM_PICKER 0x1e // see sparcv8.pdf p.76 for interrupt levels
249 251 #define IRQ_SPECTRAL_MATRIX 6
250 252 #define IRQ_SPARC_SPECTRAL_MATRIX 0x16 // see sparcv8.pdf p.76 for interrupt levels
251 253
252 254 //*****
253 255 // TIME
254 256 #define CLKDIV_WATCHDOG (10000000 - 1) // 10.0s => 10 000 000
255 257 #define TIMER_WATCHDOG 1
256 258 #define WATCHDOG_PERIOD 100 // 1s
257 259 #define HK_PERIOD 100 // 100 * 10ms => 1s
258 260 #define AVGV_PERIOD 6 // 6 * 10ms => 60ms (1 / 16 = 62.5ms)
259 261 #define SY_LFR_TIME_SYN_TIMEOUT_in_ticks 200 // 200 * 10 ms = 2 s
260 262 #define HK_SYNC_WAIT 10 // 10 * 10 ms = 100 ms
261 263 #define SPW_LINK_WAIT 10 // 10 * 10 ms = 100 ms
262 264 #define TIMECODE_TIMER_TIMEOUT 120 // 120 * 10 ms = 1.2 s
263 265 #define TIMECODE_TIMER_TIMEOUT_INIT 200 // 200 * 10 ms = 2.0 s
264 266 #define TIMECODE_MASK 0x3f // 0011 1111
265 267
266 268 //**********
267 269 // LPP CODES
268 270 #define LFR_SUCCESSFUL 0
269 271 #define LFR_DEFAULT 1
270 272 #define LFR_EXE_ERROR 2
271 273 #define LFR_DEFAULT_ALT -1
272 274
273 275 //******
274 276 // RTEMS
275 277 #define STACK_SIZE_MULT 2
276 278
277 279 #define TASKID_AVGV 0
278 280 #define TASKID_RECV 1
279 281 #define TASKID_ACTN 2
280 282 #define TASKID_SPIQ 3
281 283 #define TASKID_LOAD 4
282 284 #define TASKID_AVF0 5
283 285 #define TASKID_SWBD 6
284 286 #define TASKID_WFRM 7
285 287 #define TASKID_DUMB 8
286 288 #define TASKID_HOUS 9
287 289 #define TASKID_PRC0 10
288 290 #define TASKID_CWF3 11
289 291 #define TASKID_CWF2 12
290 292 #define TASKID_CWF1 13
291 293 #define TASKID_SEND 14
292 294 #define TASKID_LINK 15
293 295 #define TASKID_AVF1 16
294 296 #define TASKID_PRC1 17
295 297 #define TASKID_AVF2 18
296 298 #define TASKID_PRC2 19
297 299
298 300 #define TASK_PRIORITY_SPIQ 5
299 301 #define TASK_PRIORITY_LINK 20
300 302 #define TASK_PRIORITY_AVGV 25
301 303 #define TASK_PRIORITY_HOUS 30
302 304 #define TASK_PRIORITY_CWF1 35 // CWF1 and CWF2 are never running together
303 305 #define TASK_PRIORITY_CWF2 35 //
304 306 #define TASK_PRIORITY_SWBD 37 // SWBD has a lower priority than WFRM, this is to extract the snapshot before sending it
305 307 #define TASK_PRIORITY_WFRM 40
306 308 #define TASK_PRIORITY_CWF3 40 // there is a printf in this function, be careful with its priority wrt CWF1
307 309 #define TASK_PRIORITY_SEND 45
308 310 #define TASK_PRIORITY_RECV 50
309 311 #define TASK_PRIORITY_ACTN 50
310 312 #define TASK_PRIORITY_AVF0 60
311 313 #define TASK_PRIORITY_AVF1 70
312 314 #define TASK_PRIORITY_PRC0 100
313 315 #define TASK_PRIORITY_PRC1 100
314 316 #define TASK_PRIORITY_AVF2 110
315 317 #define TASK_PRIORITY_PRC2 110
316 318 #define TASK_PRIORITY_LOAD 190
317 319 #define TASK_PRIORITY_DUMB 200
318 320
319 321 #define MSG_QUEUE_COUNT_RECV 10
320 322 #define MSG_QUEUE_COUNT_SEND 50
321 323 #define MSG_QUEUE_COUNT_PRC0 10
322 324 #define MSG_QUEUE_COUNT_PRC1 10
323 325 #define MSG_QUEUE_COUNT_PRC2 5
324 326 #define MSG_QUEUE_SIZE_SEND 812 // 808 + 4 => TM_LFR_SCIENCE_BURST_BP2_F1
325 327 #define ACTION_MSG_SPW_IOCTL_SEND_SIZE 24 // hlen *hdr dlen *data sent options
326 328 #define MSG_QUEUE_SIZE_PRC0 36 // two pointers, one rtems_event + 6 integers
327 329 #define MSG_QUEUE_SIZE_PRC1 36 // two pointers, one rtems_event + 6 integers
328 330 #define MSG_QUEUE_SIZE_PRC2 36 // two pointers, one rtems_event + 6 integers
329 331
330 332 #define QUEUE_RECV 0
331 333 #define QUEUE_SEND 1
332 334 #define QUEUE_PRC0 2
333 335 #define QUEUE_PRC1 3
334 336 #define QUEUE_PRC2 4
335 337
336 338 #define CPU_USAGE_REPORT_PERIOD 6 // * 10 s = period
337 339
338 340 struct param_local_str{
339 341 unsigned int local_sbm1_nb_cwf_sent;
340 342 unsigned int local_sbm1_nb_cwf_max;
341 343 unsigned int local_sbm2_nb_cwf_sent;
342 344 unsigned int local_sbm2_nb_cwf_max;
343 345 };
344 346
345 347 //************
346 348 // FBINS MASKS
347 349
348 350 #define BYTES_PER_FBINS_MASK 16
349 351
350 352 typedef struct {
351 353 unsigned char merged_fbins_mask_f0[BYTES_PER_FBINS_MASK];
352 354 unsigned char merged_fbins_mask_f1[BYTES_PER_FBINS_MASK];
353 355 unsigned char merged_fbins_mask_f2[BYTES_PER_FBINS_MASK];
354 356 } fbins_masks_t;
355 357
356 358 #define DEFAULT_SY_LFR_PAS_FILTER_ENABLED 0
357 359 #define DEFAULT_SY_LFR_PAS_FILTER_MODULUS 4
358 360 #define DEFAULT_SY_LFR_PAS_FILTER_TBAD 1.0
359 361 #define DEFAULT_SY_LFR_PAS_FILTER_OFFSET 0
360 362 #define DEFAULT_SY_LFR_PAS_FILTER_SHIFT 0.5
361 363 #define DEFAULT_SY_LFR_SC_RW_DELTA_F 0.045
362 364 #define DEFAULT_SY_LFR_RW_K1 1.
363 365 #define DEFAULT_SY_LFR_RW_K2 8.
364 366 #define DEFAULT_SY_LFR_RW_K3 24.
365 367 #define DEFAULT_SY_LFR_RW_K4 48.
366 368
367 369 typedef struct{
368 370 unsigned char spare_sy_lfr_pas_filter_enabled;
369 371 unsigned char sy_lfr_pas_filter_modulus;
370 372 float sy_lfr_pas_filter_tbad;
371 373 unsigned char sy_lfr_pas_filter_offset;
372 374 float sy_lfr_pas_filter_shift;
373 375 float sy_lfr_sc_rw_delta_f;
374 376 // rw1_k
375 377 float sy_lfr_rw1_k1;
376 378 float sy_lfr_rw1_k2;
377 379 float sy_lfr_rw1_k3;
378 380 float sy_lfr_rw1_k4;
379 381 // rw2_k
380 382 float sy_lfr_rw2_k1;
381 383 float sy_lfr_rw2_k2;
382 384 float sy_lfr_rw2_k3;
383 385 float sy_lfr_rw2_k4;
384 386 // rw3_k
385 387 float sy_lfr_rw3_k1;
386 388 float sy_lfr_rw3_k2;
387 389 float sy_lfr_rw3_k3;
388 390 float sy_lfr_rw3_k4;
389 391 // rw4_k
390 392 float sy_lfr_rw4_k1;
391 393 float sy_lfr_rw4_k2;
392 394 float sy_lfr_rw4_k3;
393 395 float sy_lfr_rw4_k4;
394 396 } filterPar_t;
395 397
396 398 typedef struct{
397 399 // rw1_f
398 400 float cp_rpw_sc_rw1_f1;
399 401 float cp_rpw_sc_rw1_f2;
400 402 float cp_rpw_sc_rw1_f3;
401 403 float cp_rpw_sc_rw1_f4;
402 404 // rw2_f
403 405 float cp_rpw_sc_rw2_f1;
404 406 float cp_rpw_sc_rw2_f2;
405 407 float cp_rpw_sc_rw2_f3;
406 408 float cp_rpw_sc_rw2_f4;
407 409 // rw3_f
408 410 float cp_rpw_sc_rw3_f1;
409 411 float cp_rpw_sc_rw3_f2;
410 412 float cp_rpw_sc_rw3_f3;
411 413 float cp_rpw_sc_rw3_f4;
412 414 // rw4_f
413 415 float cp_rpw_sc_rw4_f1;
414 416 float cp_rpw_sc_rw4_f2;
415 417 float cp_rpw_sc_rw4_f3;
416 418 float cp_rpw_sc_rw4_f4;
417 419 } rw_f_t;
418 420
419 421 #define NB_ACQUISITION_DURATION 3
420 422 #define ACQUISITION_DURATION_F0 683 // 256 / 24576 * 65536
421 423 #define ACQUISITION_DURATION_F1 4096 // 256 / 4096 * 65536
422 424 #define ACQUISITION_DURATION_F2 65536 // 256 / 256 * 65536
423 425
424 426 #endif // FSW_PARAMS_H_INCLUDED
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