HG_REPOSITORIES/LPP/INSTRUMENTATION/SOLO_LFR/lfr_common_headers Commit - r23:72c4d5eb0bb9

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ccsds_types.h +8 -4

              #define SID_K_DUMP          11
              // HEADER_LENGTH
-             #define TM_HEADER_LEN 16
-             #define HEADER_LENGTH_TM_LFR_SCIENCE_ASM 28
+             //#define TM_HEADER_LEN 16
+             #define HEADER_LENGTH_TM_LFR_SCIENCE_CWF 32
+             #define HEADER_LENGTH_TM_LFR_SCIENCE_SWF 34
+             #define HEADER_LENGTH_TM_LFR_SCIENCE_ASM 34
              // PACKET_LENGTH
              #define PACKET_LENGTH_TC_EXE_SUCCESS                (20   - CCSDS_TC_TM_PACKET_OFFSET)
              #define PACKET_LENGTH_TC_EXE_INCONSISTENT           (26   - CCSDS_TC_TM_PACKET_OFFSET)
              #define PACKET_LENGTH_PARAMETER_DUMP                (84   - CCSDS_TC_TM_PACKET_OFFSET)
              #define PACKET_LENGTH_K_DUMP                        (3920 - CCSDS_TC_TM_PACKET_OFFSET)
              // SCIENCE ASM
-             #define PACKET_LENGTH_TM_LFR_SCIENCE_ASM_F0         (3230 - CCSDS_TC_TM_PACKET_OFFSET)  // 32 * 25 * 4 + 30 => 88 bins  (32 + 32 + 24 ), 3 packets
-             #define PACKET_LENGTH_TM_LFR_SCIENCE_ASM_F1         (3630 - CCSDS_TC_TM_PACKET_OFFSET)  // 52 * 25 * 2 + 30 => 104 bins (36 + 36 + 32 ), 3 packets
+             #define PACKET_LENGTH_TM_LFR_SCIENCE_ASM_F0_1       (3230 - CCSDS_TC_TM_PACKET_OFFSET)  // 32 * 25 * 4 + 30 => 32 bins  (32 + 32 + 24 ), 3 packets
+             #define PACKET_LENGTH_TM_LFR_SCIENCE_ASM_F0_2       (2430 - CCSDS_TC_TM_PACKET_OFFSET)  // 24 * 25 * 4 + 30 => 24 bins  (32 + 32 + 24 ), 3 packets
+             #define PACKET_LENGTH_TM_LFR_SCIENCE_ASM_F1_1       (3630 - CCSDS_TC_TM_PACKET_OFFSET)  // 36 * 25 * 4 + 30 => 36 bins  (36 + 36 + 32 ), 3 packets
+             #define PACKET_LENGTH_TM_LFR_SCIENCE_ASM_F1_2       (3230 - CCSDS_TC_TM_PACKET_OFFSET)  // 32 * 25 * 4 + 30 => 32 bins  (36 + 36 + 32 ), 3 packets
              #define PACKET_LENGTH_TM_LFR_SCIENCE_ASM_F2         (3230 - CCSDS_TC_TM_PACKET_OFFSET)  // 32 * 25 * 4 + 30 => 96 bins  (32 + 32 + 32 ), 3 packets
              // SCIENCE NORM
              #define PACKET_LENGTH_TM_LFR_SCIENCE_NORM_BP1_F0    (150  - CCSDS_TC_TM_PACKET_OFFSET)  // 11 * 11     + 29 (1 spare byte in the header)

fsw_params.h +1 -1

              #define MSG_QUEUE_COUNT_PRC0  10
              #define MSG_QUEUE_COUNT_PRC1  10
              #define MSG_QUEUE_COUNT_PRC2  5
-             #define MSG_QUEUE_SIZE_SEND             810 // 806 + 4 => TM_LFR_SCIENCE_BURST_BP2_F1
+             #define MSG_QUEUE_SIZE_SEND             812 // 808 + 4 => TM_LFR_SCIENCE_BURST_BP2_F1
              #define ACTION_MSG_SPW_IOCTL_SEND_SIZE  24  // hlen *hdr dlen *data sent options
              #define MSG_QUEUE_SIZE_PRC0             28  // two pointers, one rtems_event + 4 integers
              #define MSG_QUEUE_SIZE_PRC1             28  // two pointers, one rtems_event + 4 integers

fsw_params_processing.h +10 -6

              #define NB_RING_NODES_ASM_F2            3   // AT LEAST 3
              //
              #define NB_BINS_PER_ASM_F0          88
-             #define NB_BINS_PER_PKT_ASM_F0      44
-             #define TOTAL_SIZE_ASM_F0_IN_BYTES  4400    // 25 * 88 * 2
+             #define NB_BINS_PER_PKT_ASM_F0_1    32
+             #define NB_BINS_PER_PKT_ASM_F0_2    24
+             #define DLEN_ASM_F0_PKT_1           3200    // 32 * 25 * 4, 25 components per matrix, 4 bytes per float
+             #define DLEN_ASM_F0_PKT_2           2400    // 24 * 25 * 4, 25 components per matrix, 4 bytes per float
              #define ASM_F0_INDICE_START         16      // 17  - 1, (-1) due to the VHDL behaviour
              #define ASM_F0_INDICE_STOP          103     // 104 - 1, 2 packets of 44 bins
              //
              #define NB_BINS_PER_ASM_F1          104
-             #define NB_BINS_PER_PKT_ASM_F1      52
-             #define TOTAL_SIZE_ASM_F1_IN_BYTES  5200    // 25 * 104 * 2
+             #define NB_BINS_PER_PKT_ASM_F1_1    36
+             #define NB_BINS_PER_PKT_ASM_F1_2    32
+             #define DLEN_ASM_F1_PKT_1           3600    // 36 * 25 * 4, 25 components per matrix, 4 bytes per float
+             #define DLEN_ASM_F1_PKT_2           3200    // 32 * 25 * 4, 25 components per matrix, 4 bytes per float
              #define ASM_F1_INDICE_START         5       //   6 - 1, (-1) due to the VHDL behaviour
              #define ASM_F1_INDICE_STOP          108     // 109 - 1, 2 packets of 52 bins
              //
              #define NB_BINS_PER_ASM_F2          96
-             #define NB_BINS_PER_PKT_ASM_F2      48
-             #define TOTAL_SIZE_ASM_F2_IN_BYTES  4800    // 25 * 96 * 2
+             #define NB_BINS_PER_PKT_ASM_F2      32
+             #define DLEN_ASM_F2_PKT             3200    // 32 * 25 * 4, 25 components per matrix, 4 bytes per float
              #define ASM_F2_INDICE_START         6       //   7 - 1, (-1) due to the VHDL behaviour
              #define ASM_F2_INDICE_STOP          101     // 102 - 1, 2 packets of 48 bins
              //

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