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1 | #ifndef FSW_PARAMS_PROCESSING_H |
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1 | #ifndef FSW_PARAMS_PROCESSING_H | |
2 | #define FSW_PARAMS_PROCESSING_H |
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2 | #define FSW_PARAMS_PROCESSING_H | |
3 |
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3 | |||
4 | #define CHANNELF0 0 |
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4 | #define CHANNELF0 0 | |
5 | #define CHANNELF1 1 |
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5 | #define CHANNELF1 1 | |
6 | #define CHANNELF2 2 |
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6 | #define CHANNELF2 2 | |
7 | #define CHANNELF3 3 |
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7 | #define CHANNELF3 3 | |
8 |
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8 | |||
9 | #define FINETIME_PER_SM_F0 683 // 65536 / 96 = 682.6667 |
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10 | #define FINETIME_PER_SM_F1 4096 // 65536 / 16 |
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11 | #define FINETIME_PER_SM_F2 65536 // 65536 / 1 |
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12 | #define NB_SM_PER_S_F0 96 |
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9 | #define NB_SM_PER_S_F0 96 | |
13 | #define NB_SM_PER_S_F1 16 |
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10 | #define NB_SM_PER_S_F1 16 | |
14 | #define NB_SM_PER_S_F2 1 |
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11 | #define NB_SM_PER_S_F2 1 | |
15 | #define NB_SM_PER_S1_BP_P0 24 |
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12 | #define NB_SM_PER_S1_BP_P0 24 | |
16 |
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13 | |||
17 | #define ASM_COMP_B1B2 1 |
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14 | #define ASM_COMP_B1B2 1 | |
18 | #define ASM_COMP_B1B3 3 |
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15 | #define ASM_COMP_B1B3 3 | |
19 | #define ASM_COMP_B1E1 5 |
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16 | #define ASM_COMP_B1E1 5 | |
20 | #define ASM_COMP_B1E2 7 |
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17 | #define ASM_COMP_B1E2 7 | |
21 | #define ASM_COMP_B2B3 10 |
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18 | #define ASM_COMP_B2B3 10 | |
22 | #define ASM_COMP_B2E1 12 |
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19 | #define ASM_COMP_B2E1 12 | |
23 | #define ASM_COMP_B2E2 14 |
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20 | #define ASM_COMP_B2E2 14 | |
24 | #define ASM_COMP_B3E1 17 |
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21 | #define ASM_COMP_B3E1 17 | |
25 | #define ASM_COMP_B3E2 19 |
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22 | #define ASM_COMP_B3E2 19 | |
26 | #define ASM_COMP_E1E2 22 |
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23 | #define ASM_COMP_E1E2 22 | |
27 | #define ASM_COMP_B1B1 0 |
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24 | #define ASM_COMP_B1B1 0 | |
28 | #define ASM_COMP_B2B2 9 |
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25 | #define ASM_COMP_B2B2 9 | |
29 | #define ASM_COMP_B3B3 16 |
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26 | #define ASM_COMP_B3B3 16 | |
30 | #define ASM_COMP_E1E1 21 |
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27 | #define ASM_COMP_E1E1 21 | |
31 | #define ASM_COMP_E2E2 24 |
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28 | #define ASM_COMP_E2E2 24 | |
32 |
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29 | |||
33 | #define SM_BYTES_PER_VAL 2 |
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30 | #define SM_BYTES_PER_VAL 2 | |
34 | #define NB_BINS_PER_SM 128 |
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31 | #define NB_BINS_PER_SM 128 | |
35 | #define NB_VALUES_PER_SM 25 |
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32 | #define NB_VALUES_PER_SM 25 | |
36 | #define TOTAL_SIZE_SM 3200 // 25 * 128 = 0xC80 |
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33 | #define TOTAL_SIZE_SM 3200 // 25 * 128 = 0xC80 | |
37 | #define TOTAL_SIZE_NORM_BP1_F0 99 // 11 * 9 = 99 |
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34 | #define TOTAL_SIZE_NORM_BP1_F0 99 // 11 * 9 = 99 | |
38 | #define TOTAL_SIZE_NORM_BP1_F1 117 // 13 * 9 = 117 |
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35 | #define TOTAL_SIZE_NORM_BP1_F1 117 // 13 * 9 = 117 | |
39 | #define TOTAL_SIZE_NORM_BP1_F2 108 // 12 * 9 = 108 |
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36 | #define TOTAL_SIZE_NORM_BP1_F2 108 // 12 * 9 = 108 | |
40 | #define TOTAL_SIZE_SBM1_BP1_F0 198 // 22 * 9 = 198 |
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37 | #define TOTAL_SIZE_SBM1_BP1_F0 198 // 22 * 9 = 198 | |
41 | // F0 |
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38 | // F0 | |
42 | #define NB_RING_NODES_SM_F0 20 // AT LEAST 8 due to the way the averaging is done |
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39 | #define NB_RING_NODES_SM_F0 20 // AT LEAST 8 due to the way the averaging is done | |
43 | #define NB_RING_NODES_ASM_BURST_SBM_F0 10 // AT LEAST 3 |
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40 | #define NB_RING_NODES_ASM_BURST_SBM_F0 10 // AT LEAST 3 | |
44 | #define NB_RING_NODES_ASM_NORM_F0 10 // AT LEAST 3 |
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41 | #define NB_RING_NODES_ASM_NORM_F0 10 // AT LEAST 3 | |
45 | #define NB_RING_NODES_ASM_F0 3 // AT LEAST 3 |
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42 | #define NB_RING_NODES_ASM_F0 3 // AT LEAST 3 | |
46 | // F1 |
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43 | // F1 | |
47 | #define NB_RING_NODES_SM_F1 12 // AT LEAST 8 due to the way the averaging is done |
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44 | #define NB_RING_NODES_SM_F1 12 // AT LEAST 8 due to the way the averaging is done | |
48 | #define NB_RING_NODES_ASM_BURST_SBM_F1 5 // AT LEAST 3 |
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45 | #define NB_RING_NODES_ASM_BURST_SBM_F1 5 // AT LEAST 3 | |
49 | #define NB_RING_NODES_ASM_NORM_F1 5 // AT LEAST 3 |
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46 | #define NB_RING_NODES_ASM_NORM_F1 5 // AT LEAST 3 | |
50 | #define NB_RING_NODES_ASM_F1 3 // AT LEAST 3 |
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47 | #define NB_RING_NODES_ASM_F1 3 // AT LEAST 3 | |
51 | // F2 |
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48 | // F2 | |
52 | #define NB_RING_NODES_SM_F2 5 // AT LEAST 3 |
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49 | #define NB_RING_NODES_SM_F2 5 // AT LEAST 3 | |
53 | #define NB_RING_NODES_ASM_NORM_F2 3 // AT LEAST 3 |
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50 | #define NB_RING_NODES_ASM_NORM_F2 3 // AT LEAST 3 | |
54 | #define NB_RING_NODES_ASM_F2 3 // AT LEAST 3 |
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51 | #define NB_RING_NODES_ASM_F2 3 // AT LEAST 3 | |
55 | // |
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52 | // | |
56 | #define NB_BINS_PER_ASM_F0 88 |
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53 | #define NB_BINS_PER_ASM_F0 88 | |
57 | #define NB_BINS_PER_PKT_ASM_F0_1 32 |
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54 | #define NB_BINS_PER_PKT_ASM_F0_1 32 | |
58 | #define NB_BINS_PER_PKT_ASM_F0_2 24 |
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55 | #define NB_BINS_PER_PKT_ASM_F0_2 24 | |
59 | #define DLEN_ASM_F0_PKT_1 3200 // 32 * 25 * 4, 25 components per matrix, 4 bytes per float |
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56 | #define DLEN_ASM_F0_PKT_1 3200 // 32 * 25 * 4, 25 components per matrix, 4 bytes per float | |
60 | #define DLEN_ASM_F0_PKT_2 2400 // 24 * 25 * 4, 25 components per matrix, 4 bytes per float |
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57 | #define DLEN_ASM_F0_PKT_2 2400 // 24 * 25 * 4, 25 components per matrix, 4 bytes per float | |
61 | #define ASM_F0_INDICE_START 16 // 17 - 1, (-1) due to the VHDL behaviour |
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58 | #define ASM_F0_INDICE_START 16 // 17 - 1, (-1) due to the VHDL behaviour | |
62 | #define ASM_F0_INDICE_STOP 103 // 104 - 1, 2 packets of 44 bins |
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59 | #define ASM_F0_INDICE_STOP 103 // 104 - 1, 2 packets of 44 bins | |
63 | // |
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60 | // | |
64 | #define NB_BINS_PER_ASM_F1 104 |
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61 | #define NB_BINS_PER_ASM_F1 104 | |
65 | #define NB_BINS_PER_PKT_ASM_F1_1 36 |
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62 | #define NB_BINS_PER_PKT_ASM_F1_1 36 | |
66 | #define NB_BINS_PER_PKT_ASM_F1_2 32 |
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63 | #define NB_BINS_PER_PKT_ASM_F1_2 32 | |
67 | #define DLEN_ASM_F1_PKT_1 3600 // 36 * 25 * 4, 25 components per matrix, 4 bytes per float |
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64 | #define DLEN_ASM_F1_PKT_1 3600 // 36 * 25 * 4, 25 components per matrix, 4 bytes per float | |
68 | #define DLEN_ASM_F1_PKT_2 3200 // 32 * 25 * 4, 25 components per matrix, 4 bytes per float |
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65 | #define DLEN_ASM_F1_PKT_2 3200 // 32 * 25 * 4, 25 components per matrix, 4 bytes per float | |
69 | #define ASM_F1_INDICE_START 5 // 6 - 1, (-1) due to the VHDL behaviour |
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66 | #define ASM_F1_INDICE_START 5 // 6 - 1, (-1) due to the VHDL behaviour | |
70 | #define ASM_F1_INDICE_STOP 108 // 109 - 1, 2 packets of 52 bins |
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67 | #define ASM_F1_INDICE_STOP 108 // 109 - 1, 2 packets of 52 bins | |
71 | // |
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68 | // | |
72 | #define NB_BINS_PER_ASM_F2 96 |
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69 | #define NB_BINS_PER_ASM_F2 96 | |
73 | #define NB_BINS_PER_PKT_ASM_F2 32 |
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70 | #define NB_BINS_PER_PKT_ASM_F2 32 | |
74 | #define DLEN_ASM_F2_PKT 3200 // 32 * 25 * 4, 25 components per matrix, 4 bytes per float |
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71 | #define DLEN_ASM_F2_PKT 3200 // 32 * 25 * 4, 25 components per matrix, 4 bytes per float | |
75 | #define ASM_F2_INDICE_START 6 // 7 - 1, (-1) due to the VHDL behaviour |
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72 | #define ASM_F2_INDICE_START 6 // 7 - 1, (-1) due to the VHDL behaviour | |
76 | #define ASM_F2_INDICE_STOP 101 // 102 - 1, 2 packets of 48 bins |
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73 | #define ASM_F2_INDICE_STOP 101 // 102 - 1, 2 packets of 48 bins | |
77 | // |
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74 | // | |
78 | #define KCOEFF_BLK_SIZE 130 |
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75 | #define KCOEFF_BLK_SIZE 130 | |
79 | #define KCOEFF_FREQ 2 |
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76 | #define KCOEFF_FREQ 2 | |
80 | #define NB_BINS_COMPRESSED_SM_F0 11 |
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77 | #define NB_BINS_COMPRESSED_SM_F0 11 | |
81 | #define NB_BINS_COMPRESSED_SM_F1 13 |
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78 | #define NB_BINS_COMPRESSED_SM_F1 13 | |
82 | #define NB_BINS_COMPRESSED_SM_F2 12 |
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79 | #define NB_BINS_COMPRESSED_SM_F2 12 | |
83 | #define NB_BINS_COMPRESSED_SM 36 // 11 + 12 + 13 |
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80 | #define NB_BINS_COMPRESSED_SM 36 // 11 + 12 + 13 | |
84 | #define NB_BINS_COMPRESSED_SM_SBM_F0 22 |
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81 | #define NB_BINS_COMPRESSED_SM_SBM_F0 22 | |
85 | #define NB_BINS_COMPRESSED_SM_SBM_F1 26 |
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82 | #define NB_BINS_COMPRESSED_SM_SBM_F1 26 | |
86 | #define NB_BINS_COMPRESSED_SM_SBM_F2 24 |
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83 | #define NB_BINS_COMPRESSED_SM_SBM_F2 24 | |
87 | // |
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84 | // | |
88 | #define NB_BYTES_PER_BP1 9 |
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85 | #define NB_BYTES_PER_BP1 9 | |
89 | #define NB_BYTES_PER_BP2 30 |
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86 | #define NB_BYTES_PER_BP2 30 | |
90 | // |
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87 | // | |
91 | #define NB_BINS_TO_AVERAGE_ASM_F0 8 |
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88 | #define NB_BINS_TO_AVERAGE_ASM_F0 8 | |
92 | #define NB_BINS_TO_AVERAGE_ASM_F1 8 |
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89 | #define NB_BINS_TO_AVERAGE_ASM_F1 8 | |
93 | #define NB_BINS_TO_AVERAGE_ASM_F2 8 |
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90 | #define NB_BINS_TO_AVERAGE_ASM_F2 8 | |
94 | #define NB_BINS_TO_AVERAGE_ASM_SBM_F0 4 |
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91 | #define NB_BINS_TO_AVERAGE_ASM_SBM_F0 4 | |
95 | #define NB_BINS_TO_AVERAGE_ASM_SBM_F1 4 |
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92 | #define NB_BINS_TO_AVERAGE_ASM_SBM_F1 4 | |
96 | #define NB_BINS_TO_AVERAGE_ASM_SBM_F2 4 |
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93 | #define NB_BINS_TO_AVERAGE_ASM_SBM_F2 4 | |
97 | // |
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94 | // | |
98 | #define TOTAL_SIZE_COMPRESSED_ASM_NORM_F0 275 // 11 * 25 WORDS |
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95 | #define TOTAL_SIZE_COMPRESSED_ASM_NORM_F0 275 // 11 * 25 WORDS | |
99 | #define TOTAL_SIZE_COMPRESSED_ASM_NORM_F1 325 // 13 * 25 WORDS |
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96 | #define TOTAL_SIZE_COMPRESSED_ASM_NORM_F1 325 // 13 * 25 WORDS | |
100 | #define TOTAL_SIZE_COMPRESSED_ASM_NORM_F2 300 // 12 * 25 WORDS |
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97 | #define TOTAL_SIZE_COMPRESSED_ASM_NORM_F2 300 // 12 * 25 WORDS | |
101 | #define TOTAL_SIZE_COMPRESSED_ASM_SBM_F0 550 // 22 * 25 WORDS |
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98 | #define TOTAL_SIZE_COMPRESSED_ASM_SBM_F0 550 // 22 * 25 WORDS | |
102 | #define TOTAL_SIZE_COMPRESSED_ASM_SBM_F1 650 // 26 * 25 WORDS |
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99 | #define TOTAL_SIZE_COMPRESSED_ASM_SBM_F1 650 // 26 * 25 WORDS | |
103 | #define TOTAL_SIZE_BP1_NORM_F0 99 // 9 * 11 UNSIGNED CHAR |
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100 | #define TOTAL_SIZE_BP1_NORM_F0 99 // 9 * 11 UNSIGNED CHAR | |
104 | #define TOTAL_SIZE_BP2_NORM_F0 330 // 30 * 11 UNSIGNED CHAR |
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101 | #define TOTAL_SIZE_BP2_NORM_F0 330 // 30 * 11 UNSIGNED CHAR | |
105 | #define TOTAL_SIZE_BP1_SBM_F0 198 // 9 * 22 UNSIGNED CHAR |
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102 | #define TOTAL_SIZE_BP1_SBM_F0 198 // 9 * 22 UNSIGNED CHAR | |
106 | // GENERAL |
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103 | // GENERAL | |
107 | #define NB_SM_BEFORE_AVF0_F1 8 // must be 8 due to the SM_average() function |
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104 | #define NB_SM_BEFORE_AVF0_F1 8 // must be 8 due to the SM_average() function | |
108 | #define NB_SM_BEFORE_AVF2 1 // must be 1 due to the SM_average_f2() function |
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105 | #define NB_SM_BEFORE_AVF2 1 // must be 1 due to the SM_average_f2() function | |
109 |
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106 | |||
110 | #endif // FSW_PARAMS_PROCESSING_H |
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107 | #endif // FSW_PARAMS_PROCESSING_H | |
111 |
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108 |
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