@@ -106,7 +106,7 | |||
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106 | 106 | #define TC_LEN_LOAD_K 142 |
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107 | 107 | #define TC_LEN_DUMP_K 12 |
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108 | 108 | #define TC_LEN_LOAD_FBINS 60 |
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109 |
#define TC_LEN_LOAD_FILTER_PAR 2 |
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109 | #define TC_LEN_LOAD_FILTER_PAR 92 | |
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110 | 110 | #define TC_LEN_UPDT_TIME 18 |
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111 | 111 | |
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112 | 112 | // PACKET CODES |
@@ -246,7 +246,7 enum apid_destid{ | |||
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246 | 246 | #define PACKET_LENGTH_TC_EXE_ERROR (24 - CCSDS_TC_TM_PACKET_OFFSET) |
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247 | 247 | #define PACKET_LENGTH_TC_EXE_CORRUPTED (32 - CCSDS_TC_TM_PACKET_OFFSET) |
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248 | 248 | #define PACKET_LENGTH_HK (136 - CCSDS_TC_TM_PACKET_OFFSET) |
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249 |
#define PACKET_LENGTH_PARAMETER_DUMP ( |
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249 | #define PACKET_LENGTH_PARAMETER_DUMP (212 - CCSDS_TC_TM_PACKET_OFFSET) | |
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250 | 250 | #define PACKET_LENGTH_K_DUMP (3920 - CCSDS_TC_TM_PACKET_OFFSET) |
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251 | 251 | // SCIENCE ASM |
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252 | 252 | #define PACKET_LENGTH_TM_LFR_SCIENCE_ASM_F0_1 (3230 - CCSDS_TC_TM_PACKET_OFFSET) // 32 * 25 * 4 + 30 => 32 bins (32 + 32 + 24 ), 3 packets |
@@ -674,9 +674,9 typedef struct { | |||
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674 | 674 | unsigned char hk_lfr_buffer_dpu_tm_fifo; |
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675 | 675 | // hk_lfr_ahb_ |
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676 | 676 | unsigned char hk_lfr_ahb_correctable; |
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677 | unsigned char hk_lfr_ahb_uncorrectable; | |
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678 | 677 | // reaction wheel frequency |
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679 | unsigned char hk_lfr_sc_rw_f_flags; | |
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678 | unsigned char hk_lfr_sc_rw1_rw2_f_flags; | |
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679 | unsigned char hk_lfr_sc_rw3_rw4_f_flags; | |
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680 | 680 | } Packet_TM_LFR_HK_t; |
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681 | 681 | |
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682 | 682 | typedef struct { |
@@ -750,6 +750,27 typedef struct { | |||
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750 | 750 | unsigned char sy_lfr_pas_filter_shift[4]; |
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751 | 751 | unsigned char sy_lfr_sc_rw_delta_f[4]; |
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752 | 752 | |
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753 | // RW1_K | |
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754 | unsigned char sy_lfr_rw1_k1[4]; | |
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755 | unsigned char sy_lfr_rw1_k2[4]; | |
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756 | unsigned char sy_lfr_rw1_k3[4]; | |
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757 | unsigned char sy_lfr_rw1_k4[4]; | |
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758 | // RW2_K | |
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759 | unsigned char sy_lfr_rw2_k1[4]; | |
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760 | unsigned char sy_lfr_rw2_k2[4]; | |
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761 | unsigned char sy_lfr_rw2_k3[4]; | |
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762 | unsigned char sy_lfr_rw2_k4[4]; | |
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763 | // RW3_K | |
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764 | unsigned char sy_lfr_rw3_k1[4]; | |
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765 | unsigned char sy_lfr_rw3_k2[4]; | |
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766 | unsigned char sy_lfr_rw3_k3[4]; | |
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767 | unsigned char sy_lfr_rw3_k4[4]; | |
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768 | // RW4_K | |
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769 | unsigned char sy_lfr_rw4_k1[4]; | |
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770 | unsigned char sy_lfr_rw4_k2[4]; | |
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771 | unsigned char sy_lfr_rw4_k3[4]; | |
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772 | unsigned char sy_lfr_rw4_k4[4]; | |
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773 | ||
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753 | 774 | // LFR_RW_MASK |
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754 | 775 | unsigned char sy_lfr_rw_mask_f0_word1[4]; |
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755 | 776 | unsigned char sy_lfr_rw_mask_f0_word2[4]; |
@@ -287,6 +287,10 typedef struct { | |||
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287 | 287 | #define DEFAULT_SY_LFR_PAS_FILTER_OFFSET 0 |
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288 | 288 | #define DEFAULT_SY_LFR_PAS_FILTER_SHIFT 0.5 |
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289 | 289 | #define DEFAULT_SY_LFR_SC_RW_DELTA_F 0.025 |
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290 | #define DEFAULT_SY_LFR_RW_K1 1. | |
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291 | #define DEFAULT_SY_LFR_RW_K2 8. | |
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292 | #define DEFAULT_SY_LFR_RW_K3 24. | |
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293 | #define DEFAULT_SY_LFR_RW_K4 48. | |
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290 | 294 | |
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291 | 295 | typedef struct{ |
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292 | 296 | unsigned char spare_sy_lfr_pas_filter_enabled; |
@@ -295,8 +299,51 typedef struct{ | |||
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295 | 299 | unsigned char sy_lfr_pas_filter_offset; |
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296 | 300 | float sy_lfr_pas_filter_shift; |
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297 | 301 | float sy_lfr_sc_rw_delta_f; |
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302 | // rw1_k | |
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303 | float sy_lfr_rw1_k1; | |
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304 | float sy_lfr_rw1_k2; | |
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305 | float sy_lfr_rw1_k3; | |
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306 | float sy_lfr_rw1_k4; | |
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307 | // rw2_k | |
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308 | float sy_lfr_rw2_k1; | |
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309 | float sy_lfr_rw2_k2; | |
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310 | float sy_lfr_rw2_k3; | |
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311 | float sy_lfr_rw2_k4; | |
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312 | // rw3_k | |
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313 | float sy_lfr_rw3_k1; | |
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314 | float sy_lfr_rw3_k2; | |
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315 | float sy_lfr_rw3_k3; | |
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316 | float sy_lfr_rw3_k4; | |
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317 | // rw4_k | |
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318 | float sy_lfr_rw4_k1; | |
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319 | float sy_lfr_rw4_k2; | |
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320 | float sy_lfr_rw4_k3; | |
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321 | float sy_lfr_rw4_k4; | |
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298 | 322 | } filterPar_t; |
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299 | 323 | |
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324 | typedef struct{ | |
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325 | // rw1_f | |
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326 | float cp_rpw_sc_rw1_f1; | |
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327 | float cp_rpw_sc_rw1_f2; | |
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328 | float cp_rpw_sc_rw1_f3; | |
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329 | float cp_rpw_sc_rw1_f4; | |
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330 | // rw2_f | |
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331 | float cp_rpw_sc_rw2_f1; | |
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332 | float cp_rpw_sc_rw2_f2; | |
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333 | float cp_rpw_sc_rw2_f3; | |
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334 | float cp_rpw_sc_rw2_f4; | |
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335 | // rw3_f | |
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336 | float cp_rpw_sc_rw3_f1; | |
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337 | float cp_rpw_sc_rw3_f2; | |
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338 | float cp_rpw_sc_rw3_f3; | |
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339 | float cp_rpw_sc_rw3_f4; | |
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340 | // rw4_f | |
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341 | float cp_rpw_sc_rw4_f1; | |
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342 | float cp_rpw_sc_rw4_f2; | |
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343 | float cp_rpw_sc_rw4_f3; | |
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344 | float cp_rpw_sc_rw4_f4; | |
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345 | } rw_f_t; | |
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346 | ||
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300 | 347 | #define ACQUISITION_DURATION_F0 683 // 256 / 24576 * 65536 |
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301 | 348 | #define ACQUISITION_DURATION_F1 4096 // 256 / 4096 * 65536 |
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302 | 349 | #define ACQUISITION_DURATION_F2 65536 // 256 / 256 * 65536 |
@@ -32,15 +32,26 | |||
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32 | 32 | #define BYTE_POS_UPDATE_INFO_PARAMETERS_SET2 11 |
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33 | 33 | #define BYTE_POS_UPDATE_INFO_PARAMETERS_SET5 34 |
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34 | 34 | #define BYTE_POS_UPDATE_INFO_PARAMETERS_SET6 35 |
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35 | // RW1 | |
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35 | 36 | #define BYTE_POS_UPDATE_INFO_CP_RPW_SC_RW1_F1 44 |
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36 | 37 | #define BYTE_POS_UPDATE_INFO_CP_RPW_SC_RW1_F2 48 |
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37 |
#define BYTE_POS_UPDATE_INFO_CP_RPW_SC_RW |
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38 |
#define BYTE_POS_UPDATE_INFO_CP_RPW_SC_RW |
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39 | #define BYTE_POS_UPDATE_INFO_CP_RPW_SC_RW3_F1 60 | |
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40 |
#define BYTE_POS_UPDATE_INFO_CP_RPW_SC_RW |
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41 |
#define BYTE_POS_UPDATE_INFO_CP_RPW_SC_RW |
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42 |
#define BYTE_POS_UPDATE_INFO_CP_RPW_SC_RW |
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43 |
#define BYTE_POS_UPDATE_INFO_CP_RPW_SC_RW |
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38 | #define BYTE_POS_UPDATE_INFO_CP_RPW_SC_RW1_F3 52 | |
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39 | #define BYTE_POS_UPDATE_INFO_CP_RPW_SC_RW1_F4 56 | |
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40 | // RW2 | |
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41 | #define BYTE_POS_UPDATE_INFO_CP_RPW_SC_RW2_F1 60 | |
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42 | #define BYTE_POS_UPDATE_INFO_CP_RPW_SC_RW2_F2 64 | |
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43 | #define BYTE_POS_UPDATE_INFO_CP_RPW_SC_RW2_F3 68 | |
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44 | #define BYTE_POS_UPDATE_INFO_CP_RPW_SC_RW2_F4 72 | |
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45 | // RW3 | |
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46 | #define BYTE_POS_UPDATE_INFO_CP_RPW_SC_RW3_F1 76 | |
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47 | #define BYTE_POS_UPDATE_INFO_CP_RPW_SC_RW3_F2 80 | |
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48 | #define BYTE_POS_UPDATE_INFO_CP_RPW_SC_RW3_F3 84 | |
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49 | #define BYTE_POS_UPDATE_INFO_CP_RPW_SC_RW3_F4 88 | |
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50 | // RW4 | |
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51 | #define BYTE_POS_UPDATE_INFO_CP_RPW_SC_RW4_F1 92 | |
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52 | #define BYTE_POS_UPDATE_INFO_CP_RPW_SC_RW4_F2 96 | |
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53 | #define BYTE_POS_UPDATE_INFO_CP_RPW_SC_RW4_F3 100 | |
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54 | #define BYTE_POS_UPDATE_INFO_CP_RPW_SC_RW4_F4 104 | |
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44 | 55 | |
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45 | 56 | // TC_LFR_ENTER_MODE |
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46 | 57 | #define BYTE_POS_CP_MODE_LFR_SET 11 |
@@ -52,6 +63,8 | |||
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52 | 63 | #define NB_BYTES_PER_FBINS_MASK 4 |
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53 | 64 | |
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54 | 65 | // TC_LFR_LOAD_FILTER_PAR |
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66 | #define NB_RW_K_COEFFS 16 | |
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67 | #define NB_BYTES_PER_RW_K_COEFF 4 | |
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55 | 68 | #define DATAFIELD_POS_PA_RPW_SPARE8_2 0 // 8 bits |
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56 | 69 | #define DATAFIELD_POS_SY_LFR_PAS_FILTER_ENABLED 1 // 8 bits |
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57 | 70 | #define DATAFIELD_POS_SY_LFR_PAS_FILTER_MODULUS 2 // 8 bits |
@@ -59,6 +72,22 | |||
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59 | 72 | #define DATAFIELD_POS_SY_LFR_PAS_FILTER_OFFSET 7 // 8 bits |
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60 | 73 | #define DATAFIELD_POS_SY_LFR_PAS_FILTER_SHIFT 8 // 32 bits |
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61 | 74 | #define DATAFIELD_POS_SY_LFR_SC_RW_DELTA_F 12 // 32 bits |
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75 | #define DATAFIELD_POS_SY_LFR_RW1_K1 16 // 32 bits | |
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76 | #define DATAFIELD_POS_SY_LFR_RW1_K2 20 // 32 bits | |
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77 | #define DATAFIELD_POS_SY_LFR_RW1_K3 24 // 32 bits | |
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78 | #define DATAFIELD_POS_SY_LFR_RW1_K4 28 // 32 bits | |
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79 | #define DATAFIELD_POS_SY_LFR_RW2_K1 32 // 32 bits | |
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80 | #define DATAFIELD_POS_SY_LFR_RW2_K2 36 // 32 bits | |
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81 | #define DATAFIELD_POS_SY_LFR_RW2_K3 40 // 32 bits | |
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82 | #define DATAFIELD_POS_SY_LFR_RW2_K4 44 // 32 bits | |
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83 | #define DATAFIELD_POS_SY_LFR_RW3_K1 48 // 32 bits | |
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84 | #define DATAFIELD_POS_SY_LFR_RW3_K2 52 // 32 bits | |
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85 | #define DATAFIELD_POS_SY_LFR_RW3_K3 56 // 32 bits | |
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86 | #define DATAFIELD_POS_SY_LFR_RW3_K4 60 // 32 bits | |
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87 | #define DATAFIELD_POS_SY_LFR_RW4_K1 64 // 32 bits | |
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88 | #define DATAFIELD_POS_SY_LFR_RW4_K2 68 // 32 bits | |
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89 | #define DATAFIELD_POS_SY_LFR_RW4_K3 72 // 32 bits | |
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90 | #define DATAFIELD_POS_SY_LFR_RW4_K4 76 // 32 bits | |
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62 | 91 | |
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63 | 92 | // TC_LFR_LOAD_KCOEFFICIENTS |
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64 | 93 | #define NB_BYTES_PER_FLOAT 4 |
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