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HK packet changed due to misalignment of one int data...
HK packet changed due to misalignment of one int data v e1 and e2 are now valid in the HK packet

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r70:13fada57fe42 merge VHDLib206
r132:f919b72104cf VHDLib206
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*.pdf
*~
*.o
tests/*.err
doc
*.srec
FSW-qt/bin/fsw