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#ifndef FSW_RTEMS_CONFIG_H_INCLUDED
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#define FSW_RTEMS_CONFIG_H_INCLUDED
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#define GRSPW_DEVICE_NAME "/dev/grspw0"
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#define UART_DEVICE_NAME "/dev/console"
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//************************
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// flight software version
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// this parameters is handled by the Qt project options
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//**********
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// LFR MODES
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#define LFR_MODE_STANDBY 0
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#define LFR_MODE_NORMAL 1
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#define LFR_MODE_BURST 2
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#define LFR_MODE_SBM1 3
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#define LFR_MODE_SBM2 4
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#define RTEMS_EVENT_MODE_STANDBY RTEMS_EVENT_0
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#define RTEMS_EVENT_MODE_NORMAL RTEMS_EVENT_1
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#define RTEMS_EVENT_MODE_BURST RTEMS_EVENT_2
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#define RTEMS_EVENT_MODE_SBM1 RTEMS_EVENT_3
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#define RTEMS_EVENT_MODE_SBM2 RTEMS_EVENT_4
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//*****************************
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// APB REGISTERS BASE ADDRESSES
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#define REGS_ADDR_APBUART 0x80000100
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#define REGS_ADDR_GPTIMER 0x80000300
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#define REGS_ADDR_GRSPW 0x80000500
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#define REGS_ADDR_TIME_MANAGEMENT 0x80000600
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#define REGS_ADDR_SPECTRAL_MATRICES 0x80000700
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#define REGS_ADDR_WAVEFORM_PICKER 0x80000f20
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#define APBUART_CTRL_REG_MASK_DB 0xfffff7ff
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#define APBUART_SCALER_RELOAD_VALUE 0x00000050 // 25 MHz => about 38400
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//**********
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// IRQ LINES
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#define IRQ_SM 9
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#define IRQ_SPARC_SM 0x19 // see sparcv8.pdf p.76 for interrupt levels
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#define IRQ_WF 10
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#define IRQ_SPARC_WF 0x1a // see sparcv8.pdf p.76 for interrupt levels
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#define IRQ_TIME1 12
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#define IRQ_SPARC_TIME1 0x1c // see sparcv8.pdf p.76 for interrupt levels
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#define IRQ_TIME2 13
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#define IRQ_SPARC_TIME2 0x1d // see sparcv8.pdf p.76 for interrupt levels
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#define IRQ_WAVEFORM_PICKER 14
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#define IRQ_SPARC_WAVEFORM_PICKER 0x1e // see sparcv8.pdf p.76 for interrupt levels
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//*****
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// TIME
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#define CLKDIV_SM_SIMULATOR 9999
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#define CLKDIV_WF_SIMULATOR 9999999
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#define TIMER_SM_SIMULATOR 1
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#define TIMER_WF_SIMULATOR 2
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#define HK_PERIOD 100 // 100 * 10ms => 1sec
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//**********
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// LPP CODES
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#define LFR_SUCCESSFUL 0
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#define LFR_DEFAULT 1
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//******
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// RTEMS
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#define TASKID_RECV 1
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#define TASKID_ACTN 2
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#define TASKID_SPIQ 3
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#define TASKID_SMIQ 4
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#define TASKID_STAT 5
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#define TASKID_AVF0 6
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#define TASKID_BPF0 7
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#define TASKID_WFRM 8
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#define TASKID_DUMB 9
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#define TASKID_HOUS 10
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#define ACTION_MSG_QUEUE_COUNT 10
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//*******
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// MACROS
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#ifdef PRINT_MESSAGES_ON_CONSOLE
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#define PRINTF(x) printf(x);
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#define PRINTF1(x,y) printf(x,y);
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#define PRINTF2(x,y,z) printf(x,y,z);
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#else
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#define PRINTF(x) ;
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#define PRINTF1(x,y) ;
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#define PRINTF2(x,y,z) ;
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#endif
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#define NB_SAMPLES_PER_SNAPSHOT 2048
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#define TIME_OFFSET 2
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#define WAVEFORM_EXTENDED_HEADER_OFFSET 22
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#define NB_BYTES_SWF_BLK 2 * 6
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#define NB_WORDS_SWF_BLK 3
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//******************
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// SEQUENCE COUNTERS
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#define SEQ_CNT_NB_PID 2
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#define SEQ_CNT_NB_CAT 4
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#define SEQ_CNT_NB_DEST_ID 11
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// pid
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#define SEQ_CNT_PID_76 0
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#define SEQ_CNT_PID_79 1
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//cat
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#define SEQ_CNT_CAT_1 0
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#define SEQ_CNT_CAT_4 1
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#define SEQ_CNT_CAT_9 2
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#define SEQ_CNT_CAT_12 3
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// destination id
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#define SEQ_CNT_DST_ID_GROUND 0
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#define SEQ_CNT_DST_ID_MISSION_TIMELINE 1
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#define SEQ_CNT_DST_ID_TC_SEQUENCES 2
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#define SEQ_CNT_DST_ID_RECOVERY_ACTION_CMD 3
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#define SEQ_CNT_DST_ID_BACKUP_MISSION_TIMELINE 4
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#define SEQ_CNT_DST_ID_DIRECT_CMD 5
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#define SEQ_CNT_DST_ID_SPARE_GRD_SRC1 6
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#define SEQ_CNT_DST_ID_SPARE_GRD_SRC2 7
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#define SEQ_CNT_DST_ID_OBCP 8
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#define SEQ_CNT_DST_ID_SYSTEM_CONTROL 9
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#define SEQ_CNT_DST_ID_AOCS 10
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struct param_common_str{
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unsigned char sy_lfr_common0;
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unsigned char sy_lfr_common1;
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};
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struct param_norm_str{
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unsigned int sy_lfr_n_swf_l; // length of the snapshots
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unsigned int sy_lfr_n_swf_p; // time between two snapshots
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unsigned int sy_lfr_n_asm_p; // time between two asm
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unsigned char sy_lfr_n_bp_p0; // timebetween two products BP1 set
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unsigned char sy_lfr_n_bp_p1; // time between two products BP2 set
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};
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struct param_burst_str{
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unsigned char sy_lfr_b_bp_p0; // timebetween two products BP1 set
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unsigned char sy_lfr_b_bp_p1; // time between two products BP2 set
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};
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struct param_sbm1_str{
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unsigned char sy_lfr_s1_bp_p0; // timebetween two products BP1 set
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unsigned char sy_lfr_s1_bp_p1; // time between two products BP2 set
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};
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struct param_sbm2_str{
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unsigned char sy_lfr_s2_bp_p0; // timebetween two products BP1 set
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unsigned char sy_lfr_s2_bp_p1; // time between two products BP2 set
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};
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#endif // FSW_RTEMS_CONFIG_H_INCLUDED
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