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#ifndef GRLIB_REGS_H_INCLUDED
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#define GRLIB_REGS_H_INCLUDED
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#define NB_GPTIMER 3
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#include <stdint.h>
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struct apbuart_regs_str{
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volatile unsigned int data;
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volatile unsigned int status;
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volatile unsigned int ctrl;
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volatile unsigned int scaler;
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volatile unsigned int fifoDebug;
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};
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struct grgpio_regs_str{
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volatile int io_port_data_register;
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int io_port_output_register;
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int io_port_direction_register;
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int interrupt_mak_register;
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int interrupt_polarity_register;
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int interrupt_edge_register;
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int bypass_register;
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int reserved;
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// 0x20-0x3c interrupt map register(s)
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};
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typedef struct {
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volatile unsigned int counter;
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volatile unsigned int reload;
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volatile unsigned int ctrl;
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volatile unsigned int unused;
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} timer_regs_t;
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//*************
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//*************
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// GPTIMER_REGS
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#define GPTIMER_CLEAR_IRQ 0x00000010 // clear pending IRQ if any
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#define GPTIMER_LD 0x00000004 // LD load value from the reload register
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#define GPTIMER_EN 0x00000001 // EN enable the timer
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#define GPTIMER_EN_MASK 0xfffffffe // EN enable the timer
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#define GPTIMER_RS 0x00000002 // RS restart
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#define GPTIMER_IE 0x00000008 // IE interrupt enable
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#define GPTIMER_IE_MASK 0xffffffef // IE interrupt enable
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typedef struct {
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volatile unsigned int scaler_value;
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volatile unsigned int scaler_reload;
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volatile unsigned int conf;
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volatile unsigned int unused0;
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timer_regs_t timer[NB_GPTIMER];
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} gptimer_regs_t;
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//*********************
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//*********************
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// TIME_MANAGEMENT_REGS
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#define VAL_SOFTWARE_RESET 0x02 // [0010] software reset
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#define VAL_LFR_SYNCHRONIZED 0x80000000
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#define BIT_SYNCHRONIZATION 31
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#define COARSE_TIME_MASK 0x7fffffff
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#define SYNC_BIT_MASK 0x7f
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#define SYNC_BIT 0x80
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#define BIT_CAL_RELOAD 0x00000010
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#define MASK_CAL_RELOAD 0xffffffef // [1110 1111]
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#define BIT_CAL_ENABLE 0x00000040
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#define MASK_CAL_ENABLE 0xffffffbf // [1011 1111]
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#define BIT_SET_INTERLEAVED 0x00000020 // [0010 0000]
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#define MASK_SET_INTERLEAVED 0xffffffdf // [1101 1111]
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#define BIT_SOFT_RESET 0x00000004 // [0100]
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#define MASK_SOFT_RESET 0xfffffffb // [1011]
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typedef struct {
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volatile int ctrl; // bit 0 forces the load of the coarse_time_load value and resets the fine_time
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// bit 1 is the soft reset for the time management module
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// bit 2 is the soft reset for the waveform picker and the spectral matrix modules, set to 1 after HW reset
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volatile int coarse_time_load;
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volatile int coarse_time;
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volatile int fine_time;
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// TEMPERATURES
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volatile int temp_pcb; // SEL1 = 0 SEL0 = 0
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volatile int temp_fpga; // SEL1 = 0 SEL0 = 1
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volatile int temp_scm; // SEL1 = 1 SEL0 = 0
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// CALIBRATION
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volatile unsigned int calDACCtrl;
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volatile unsigned int calPrescaler;
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volatile unsigned int calDivisor;
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volatile unsigned int calDataPtr;
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volatile unsigned int calData;
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} time_management_regs_t;
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//*********************
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//*********************
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// WAVEFORM_PICKER_REGS
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#define BITS_WFP_STATUS_F3 0xc0 // [1100 0000] check the f3 full bits
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#define BIT_WFP_BUF_F3_0 0x40 // [0100 0000] f3 buffer 0 is full
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#define BIT_WFP_BUF_F3_1 0x80 // [1000 0000] f3 buffer 1 is full
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#define RST_WFP_F3_0 0x00008840 // [1000 1000 0100 0000]
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#define RST_WFP_F3_1 0x00008880 // [1000 1000 1000 0000]
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#define BITS_WFP_STATUS_F2 0x30 // [0011 0000] get the status bits for f2
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#define SHIFT_WFP_STATUS_F2 4
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#define BIT_WFP_BUF_F2_0 0x10 // [0001 0000] f2 buffer 0 is full
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#define BIT_WFP_BUF_F2_1 0x20 // [0010 0000] f2 buffer 1 is full
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#define RST_WFP_F2_0 0x00004410 // [0100 0100 0001 0000]
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#define RST_WFP_F2_1 0x00004420 // [0100 0100 0010 0000]
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#define BITS_WFP_STATUS_F1 0x0c // [0000 1100] check the f1 full bits
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#define BIT_WFP_BUF_F1_0 0x04 // [0000 0100] f1 buffer 0 is full
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#define BIT_WFP_BUF_F1_1 0x08 // [0000 1000] f1 buffer 1 is full
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#define RST_WFP_F1_0 0x00002204 // [0010 0010 0000 0100] f1 bits = 0
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#define RST_WFP_F1_1 0x00002208 // [0010 0010 0000 1000] f1 bits = 0
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#define BITS_WFP_STATUS_F0 0x03 // [0000 0011] check the f0 full bits
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#define RST_WFP_F0_0 0x00001101 // [0001 0001 0000 0001]
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#define RST_WFP_F0_1 0x00001102 // [0001 0001 0000 0010]
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#define BIT_WFP_BUFFER_0 0x01
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#define BIT_WFP_BUFFER_1 0x02
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#define RST_BITS_RUN_BURST_EN 0x80 // [1000 0000] burst f2, f1, f0 enable f3, f2, f1, f0
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#define BITS_WFP_ENABLE_ALL 0x0f // [0000 1111] enable f3, f2, f1, f0
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#define BITS_WFP_ENABLE_BURST 0x0c // [0000 1100] enable f3, f2
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#define RUN_BURST_ENABLE_SBM2 0x60 // [0110 0000] enable f2 and f1 burst
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#define RUN_BURST_ENABLE_BURST 0x40 // [0100 0000] f2 burst enabled
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#define DFLT_WFP_NB_DATA_BY_BUFFER 0xa7f // 0x30 *** 2688 - 1 => nb samples -1
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#define DFLT_WFP_SNAPSHOT_PARAM 0xa80 // 0x34 *** 2688 => nb samples
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#define DFLT_WFP_BUFFER_LENGTH 0x1f8 // buffer length in burst = 3 * 2688 / 16 = 504 = 0x1f8
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#define DFLT_WFP_DELTA_F0_2 0x30 // 48 = 11 0000, max 7 bits
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// PDB >= 0.1.28, 0x80000f54
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typedef struct{
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int data_shaping; // 0x00 00 *** R2 R1 R0 SP1 SP0 BW
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int run_burst_enable; // 0x04 01 *** [run *** burst f2, f1, f0 *** enable f3, f2, f1, f0 ]
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int addr_data_f0_0; // 0x08
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int addr_data_f0_1; // 0x0c
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int addr_data_f1_0; // 0x10
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int addr_data_f1_1; // 0x14
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int addr_data_f2_0; // 0x18
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int addr_data_f2_1; // 0x1c
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int addr_data_f3_0; // 0x20
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int addr_data_f3_1; // 0x24
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volatile int status; // 0x28
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volatile int delta_snapshot; // 0x2c
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int delta_f0; // 0x30
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int delta_f0_2; // 0x34
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int delta_f1; // 0x38
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int delta_f2; // 0x3c
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int nb_data_by_buffer; // 0x40 number of samples in a buffer = 2688
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int snapshot_param; // 0x44
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int start_date; // 0x48
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//
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volatile unsigned int f0_0_coarse_time; // 0x4c
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volatile unsigned int f0_0_fine_time; // 0x50
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volatile unsigned int f0_1_coarse_time; // 0x54
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volatile unsigned int f0_1_fine_time; // 0x58
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//
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volatile unsigned int f1_0_coarse_time; // 0x5c
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volatile unsigned int f1_0_fine_time; // 0x60
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volatile unsigned int f1_1_coarse_time; // 0x64
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volatile unsigned int f1_1_fine_time; // 0x68
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//
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volatile unsigned int f2_0_coarse_time; // 0x6c
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volatile unsigned int f2_0_fine_time; // 0x70
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volatile unsigned int f2_1_coarse_time; // 0x74
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volatile unsigned int f2_1_fine_time; // 0x78
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//
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volatile unsigned int f3_0_coarse_time; // 0x7c => 0x7c + 0xf54 = 0xd0
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volatile unsigned int f3_0_fine_time; // 0x80
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volatile unsigned int f3_1_coarse_time; // 0x84
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volatile unsigned int f3_1_fine_time; // 0x88
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//
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unsigned int buffer_length; // 0x8c = buffer length in burst 2688 / 16 = 168
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//
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volatile int16_t v_dummy; // 0x90
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volatile int16_t v; // 0x90
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volatile int16_t e1_dummy; // 0x94
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volatile int16_t e1; // 0x94
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volatile int16_t e2_dummy; // 0x98
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volatile int16_t e2; // 0x98
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} waveform_picker_regs_0_1_18_t;
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//*********************
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//*********************
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// SPECTRAL_MATRIX_REGS
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#define BITS_STATUS_F0 0x03 // [0011]
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#define BITS_STATUS_F1 0x0c // [1100]
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#define BITS_STATUS_F2 0x30 // [0011 0000]
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#define BITS_HK_AA_SM 0x780 // [0111 1000 0000]
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#define BITS_SM_ERR 0x7c0 // [0111 1100 0000]
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#define BITS_STATUS_REG 0x7ff // [0111 1111 1111]
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#define BIT_READY_0 0x1 // [01]
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#define BIT_READY_1 0x2 // [10]
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#define BIT_READY_0_1 0x3 // [11]
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#define BIT_STATUS_F1_0 0x04 // [0100]
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#define BIT_STATUS_F1_1 0x08 // [1000]
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#define BIT_STATUS_F2_0 0x10 // [0001 0000]
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#define BIT_STATUS_F2_1 0x20 // [0010 0000]
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#define DEFAULT_MATRIX_LENGTH 0xc8 // 25 * 128 / 16 = 200 = 0xc8
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#define BIT_IRQ_ON_NEW_MATRIX 0x01
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#define MASK_IRQ_ON_NEW_MATRIX 0xfffffffe
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#define BIT_IRQ_ON_ERROR 0x02
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#define MASK_IRQ_ON_ERROR 0xfffffffd
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typedef struct {
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volatile int config; // 0x00
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volatile int status; // 0x04
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volatile int f0_0_address; // 0x08
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volatile int f0_1_address; // 0x0C
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//
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volatile int f1_0_address; // 0x10
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volatile int f1_1_address; // 0x14
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volatile int f2_0_address; // 0x18
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volatile int f2_1_address; // 0x1C
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//
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volatile unsigned int f0_0_coarse_time; // 0x20
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volatile unsigned int f0_0_fine_time; // 0x24
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volatile unsigned int f0_1_coarse_time; // 0x28
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volatile unsigned int f0_1_fine_time; // 0x2C
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//
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volatile unsigned int f1_0_coarse_time; // 0x30
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volatile unsigned int f1_0_fine_time; // 0x34
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volatile unsigned int f1_1_coarse_time; // 0x38
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volatile unsigned int f1_1_fine_time; // 0x3C
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//
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volatile unsigned int f2_0_coarse_time; // 0x40
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volatile unsigned int f2_0_fine_time; // 0x44
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volatile unsigned int f2_1_coarse_time; // 0x48
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volatile unsigned int f2_1_fine_time; // 0x4C
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//
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unsigned int matrix_length; // 0x50, length of a spectral matrix in burst 3200 / 16 = 200 = 0xc8
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} spectral_matrix_regs_t;
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#endif // GRLIB_REGS_H_INCLUDED
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