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#include <..\header\LPP_spwAPI.h>
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#include <stdlib.h>
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#include <stdio.h>
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volatile int *lreg = (int*) 0x80000200; // the IRQMP controller registers are at 0x80000200
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inline int loadmemAPI(int addr)
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{
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int tmp;
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asm volatile (" lda [%1]1, %0 " // LDA => Load Word from Alternate space
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: "=r" (tmp)
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: "r" (addr)
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);
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return tmp;
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}
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inline char loadb(int addr)
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{
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char tmp;
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asm volatile (" lduba [%1]1, %0 "
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: "=r" (tmp)
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: "r" (addr)
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);
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return tmp;
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}
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char *almalloc(int sz)
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{
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char *tmp;
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tmp = (char*) malloc(2*sz);
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tmp = (char*) (((int)tmp+sz) & ~(sz-1));
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return(tmp);
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}
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//////
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// SPW
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//////
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void spw_reset(grspwregs_t *regs)
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{
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regs->ctrl = GRSPW_CTRL_RS; // make complete reset of the spacewire node, self clearing
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}
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void spw_init(int nodeaddr, int clkdiv, int destkey, int rxmaxlen, grspwregs_t *regs)
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{
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regs->ctrl = GRSPW_CTRL_LS | GRSPW_CTRL_RE; // link start (LS)
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// RMAP enable (RE)
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regs->ctrl = GRSPW_CTRL_LS | GRSPW_CTRL_RE;
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regs->ctrl = GRSPW_CTRL_LS | GRSPW_CTRL_RE;
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regs->ctrl = GRSPW_CTRL_LS | GRSPW_CTRL_RE;
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regs->ctrl = GRSPW_CTRL_LS | GRSPW_CTRL_RE;
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regs->ctrl = GRSPW_CTRL_LS | GRSPW_CTRL_RE;
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regs->status = 0xffffffff;
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regs->nodeaddr = nodeaddr;
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regs->clkdiv = clkdiv;
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regs->destkey = destkey;
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regs->time = 0;
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regs->dmactrl = GRSPW_DMACTRL_RA | GRSPW_DMACTRL_TA | GRSPW_DMACTRL_PR | GRSPW_DMACTRL_PS | GRSPW_DMACTRL_AI;
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regs->rxmaxlen = rxmaxlen;
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regs->txdesc = 0;
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regs->rxdesc = 0;
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}
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void set_txd(char *dataAddress, unsigned int dataLength, char *headerAddress, unsigned int headerLength, volatile int *txd)
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{
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txd[4] = 0;
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txd[3] = (int) dataAddress; // data address
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txd[2] = dataLength; // data length
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txd[1] = (int) headerAddress; // header address
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txd[0] = (1 << 13) | (1 << 12) | headerLength; // bit 13 WR = 1 next descriptor read will be 1st one in the table (at the base address)
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// bit 12 EN = 1 enable transmitter descriptor
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// bit 0 to 7 stand for the header length
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}
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int spw_checkrx(int* size, volatile int *rxd, grspwregs_t *regs)
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{
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volatile int tmp = 0;
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tmp = regs->dmactrl;
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if ( ( (tmp >> 6) & 1 ) )
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{ // bit 6 PR packet received
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*size = loadmemAPI((int) &rxd[0]) & 0x00001fff;
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regs->dmactrl = regs->dmactrl | 1 << 6; // clear bit 6 PR (packet received) by writing a one
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return 1;
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}
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else return 0;
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}
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int spw_checktx(grspwregs_t *regs)
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{
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if ( ( (regs->dmactrl >> 5) & 1 )==1 )
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{ // bit 5 PS (packet sent), cleared when written with a one
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regs->dmactrl = regs->dmactrl | 1 << 5; // clear bit 5 PS (packet sent) by writing a one
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return 1;
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}
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else return 0;
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}
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void enable_transmitter_descriptor(unsigned int headerLength, volatile int *txd)
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{
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txd[0] = GRSPW_TXBD_WR | GRSPW_TXBD_EN;
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//WR = 1 next descriptor read will be 1st one in the table (at the base address)
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//EN = 1 enable transmitter descriptor
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}
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void enable_transmitter(grspwregs_t *regs)
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{
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regs->dmactrl = regs->dmactrl | GRSPW_DMACTRL_TE;
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}
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void enable_receiver_descriptor(volatile char *rx, volatile int *rxd)
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{
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rxd[1] = (int) rx;
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rxd[0] = GRSPW_RXBD_IE | GRSPW_RXBD_WR | GRSPW_RXBD_EN;
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// IE = 1 Interrupt enable
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// WR = 1 next descriptor will be the 1st one in the desc table (at the base address)
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// EN = 1 activate the descriptor
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}
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void enable_receiver(grspwregs_t *regs)
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{
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regs->dmactrl = regs->dmactrl | 1 << 11 | 1 << 2;
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}
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int enable_timecode_reception(grspwregs_t *regs)
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{
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regs->ctrl = regs->ctrl | GRSPW_CTRL_TR;
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return 1;
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}
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int check_time(grspwregs_t *grspw_regs)
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{
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int tmp = loadmemAPI((int)&(grspw_regs->status)) & 1;
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if (tmp) {
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grspw_regs->status = loadmemAPI((int)&(grspw_regs->status)) | 1;
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}
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return tmp;
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}
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//////////////
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// GENERAL USE
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//////////////
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void send_fine_time(unsigned int fine_time){
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spacewire_PARAMETERS.tx[0] = (char) fine_time; // send the fine time value to LPPMON
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spacewire_PARAMETERS.tx[1] = (char) (fine_time>>8);
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spacewire_PARAMETERS.tx[2] = (char) (fine_time>>16);
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spacewire_PARAMETERS.tx[3] = (char) (fine_time>>24);
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enable_transmitter_descriptor(HEADERLEN, spacewire_PARAMETERS.txd); // enable the descriptor for transmission
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enable_transmitter(spacewire_PARAMETERS.regs); // enable the transmission
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}
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//////
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// IRQ
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//////
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int irqhandler_receive_CCSDS(int irq, void * args, struct leonbare_pt_regs * leon_regs)
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{
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if (spw_checkrx(spacewire_PARAMETERS.size, spacewire_PARAMETERS.rxd, spacewire_PARAMETERS.regs)==1)
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{
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packet_type.time_packet = 1;
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return 1;
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}
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return 0;
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}
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int enable_irq(int irq)
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{
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lreg[ICLEAR/4] = (1 << irq); // clear any pending irq
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lreg[IMASK/4] = lreg[IMASK/4] | (1 << irq); // unmask irq
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return 1;
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}
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int disable_irq(int irq) { lreg[IMASK/4] &= ~(1 << irq); return 1;}
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int force_irq(int irq) { lreg[IFORCE/4] = lreg[IFORCE/4] | (1 << irq); return 1;}
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