HG_REPOSITORIES/LPP/INSTRUMENTATION/SOLO_LFR/DEV_PLE Files · FSW-qt/bin/loadPlugin.py

TM_LFR_SCIENCE_NORMA_ASM_ packets modified, 32 bits values instead of 16 bits...

TM_LFR_SCIENCE_NORMA_ASM_ packets modified, 32 bits values instead of 16 bits resetCacheControlRegister function added txHdrSize changed (34 instead of 32)

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             loadPlugin.py
        
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             / FSW-qt / bin / loadPlugin.py
          
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      # -*- coding: utf-8 *-*

      # setting up LPPMON plugins

      from __main__ import proxy

      if not(proxy.instanceExists("RMAPPlugin0")):

      	proxy.loadSysDriver("RMAPPlugin", "RMAPPlugin0")

      	proxy.loadSysDriverToParent("dsu3plugin", "RMAPPlugin0")

      	dsu3plugin0.openFile("/opt/DEV_PLE/FSW-qt/bin/fsw")

      	dsu3plugin0.loadFile()

      	dsu3plugin0.run()

      from __main__ import RMAPPlugin0

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				# -- coding: utf-8 -*

				# setting up LPPMON plugins
				from __main__ import proxy
				if not(proxy.instanceExists("RMAPPlugin0")):
				proxy.loadSysDriver("RMAPPlugin", "RMAPPlugin0")
				proxy.loadSysDriverToParent("dsu3plugin", "RMAPPlugin0")

				dsu3plugin0.openFile("/opt/DEV_PLE/FSW-qt/bin/fsw")
				dsu3plugin0.loadFile()
				dsu3plugin0.run()

				from __main__ import RMAPPlugin0