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#ifndef GRSPW_H_INCLUDED
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#define GRSPW_H_INCLUDED
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#define GRSPW_APB_ADDR 0x80000500
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#define NODEADDR 0xfe
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#define NODEADDR_M7A3P1000 0xfd
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#define CLKDIV 0x0303
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#define DESTKEY 0
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#define RXMAXLEN 64
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#define HEADERLEN 4
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#define IFORCE 0x08
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#define ICLEAR 0x0c
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#define IMASK 0x40
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#define GRSPW_IRQ 10
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#define SPW_LINK_STATE_RESET 0
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#define SPW_LINK_STATE_WAIT 1
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#define SPW_LINK_STATE_READY 2
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#define SPW_LINK_STATE_STARTED 3
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#define SPW_LINK_STATE_CONNECTING 4
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#define SPW_LINK_STATE_RUN 5
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/////////////////////////////////////
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/* GRSPW - Control Register - 0x00 */
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#define GRSPW_CTRL_RA_BIT 31 // RMAP avaialble
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#define GRSPW_CTRL_RX_BIT 30 // RX unaligned access
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#define GRSPW_CTRL_RC_BIT 29 // RMAP CRC available
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#define GRSPW_CTRL_NCH_BIT 27 // 28:27 number of DMA channels minus 1
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#define GRSPW_CTRL_PO_BIT 26 // number of ports minus 1
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#define GRSPW_CTRL_PS_BIT 21 // Port select
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#define GRSPW_CTRL_NP_BIT 20 // No port force
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#define GRSPW_CTRL_RD_BIT 17 // RMAP buffer disable
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#define GRSPW_CTRL_RE_BIT 16 // RMAP Enable
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#define GRSPW_CTRL_TR_BIT 11 // Time Rx enable
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#define GRSPW_CTRL_TT_BIT 10 // Time Tx enable
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#define GRSPW_CTRL_LI_BIT 9 // Link error IRQ
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#define GRSPW_CTRL_TQ_BIT 8 // Tick-out IRQ
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#define GRSPW_CTRL_RS_BIT 6 // Reset
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#define GRSPW_CTRL_PM_BIT 5 // Promiscuous mode
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#define GRSPW_CTRL_TI_BIT 4 // Tick In
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#define GRSPW_CTRL_IE_BIT 3 // Interrupt enable
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#define GRSPW_CTRL_AS_BIT 2 // Autostart
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#define GRSPW_CTRL_LS_BIT 1 // Link Start
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#define GRSPW_CTRL_LD_BIT 0 // Lind Disable
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#define GRSPW_CTRL_RA (1<<GRSPW_CTRL_RA_BIT)
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#define GRSPW_CTRL_RX (1<<GRSPW_CTRL_RX_BIT)
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#define GRSPW_CTRL_RC (1<<GRSPW_CTRL_RC_BIT)
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#define GRSPW_CTRL_NCH (0x3<<GRSPW_CTRL_NCH_BIT)
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#define GRSPW_CTRL_PO (1<<GRSPW_CTRL_PO_BIT)
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#define GRSPW_CTRL_PS (1<<GRSPW_CTRL_PS_BIT)
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#define GRSPW_CTRL_NP (1<<GRSPW_CTRL_NP_BIT)
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#define GRSPW_CTRL_RD (1<<GRSPW_CTRL_RD_BIT)
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#define GRSPW_CTRL_RE (1<<GRSPW_CTRL_RE_BIT)
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#define GRSPW_CTRL_TR (1<<GRSPW_CTRL_TR_BIT)
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#define GRSPW_CTRL_TT (1<<GRSPW_CTRL_TT_BIT)
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#define GRSPW_CTRL_LI (1<<GRSPW_CTRL_LI_BIT)
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#define GRSPW_CTRL_TQ (1<<GRSPW_CTRL_TQ_BIT)
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#define GRSPW_CTRL_RS (1<<GRSPW_CTRL_RS_BIT)
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#define GRSPW_CTRL_PM (1<<GRSPW_CTRL_PM_BIT)
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#define GRSPW_CTRL_TI (1<<GRSPW_CTRL_TI_BIT)
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#define GRSPW_CTRL_IE (1<<GRSPW_CTRL_IE_BIT)
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#define GRSPW_CTRL_AS (1<<GRSPW_CTRL_AS_BIT)
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#define GRSPW_CTRL_LS (1<<GRSPW_CTRL_LS_BIT)
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#define GRSPW_CTRL_LD (1<<GRSPW_CTRL_LD_BIT)
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////////////////////////////////////
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/* GRSPW - Status Register - 0x04 */
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#define GRSPW_STAT_LS_BIT 21 // Link State
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#define GRSPW_STAT_AP_BIT 9 // Active Port
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#define GRSPW_STAT_EE_BIT 8 // Early EOP-EEP
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#define GRSPW_STAT_IA_BIT 7 // Invalid Address
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#define GRSPW_STAT_PE_BIT 4 // Parity Error
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#define GRSPW_STAT_DE_BIT 3 // Disconnect Error
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#define GRSPW_STAT_ER_BIT 2 // Escape Error
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#define GRSPW_STAT_CE_BIT 1 // Credit Error
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#define GRSPW_STAT_TO_BIT 0 // Tick Out
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#define GRSPW_STAT_LS (0x7<<GRSPW_STAT_LS_BIT)
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#define GRSPW_STAT_AP (1<<GRSPW_STAT_AP_BIT)
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#define GRSPW_STAT_EE (1<<GRSPW_STAT_EE_BIT)
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#define GRSPW_STAT_IA (1<<GRSPW_STAT_IA_BIT)
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#define GRSPW_STAT_WE (1<<GRSPW_STAT_WE_BIT)
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#define GRSPW_STAT_PE (1<<GRSPW_STAT_PE_BIT)
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#define GRSPW_STAT_DE (1<<GRSPW_STAT_DE_BIT)
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#define GRSPW_STAT_ER (1<<GRSPW_STAT_ER_BIT)
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#define GRSPW_STAT_CE (1<<GRSPW_STAT_CE_BIT)
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#define GRSPW_STAT_TO (1<<GRSPW_STAT_TO_BIT)
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/////////////////////////////////////////////
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/* GRSPW - Default Address Register - 0x08 */
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#define GRSPW_DEF_ADDR_BIT 0 // Default address
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#define GRSPW_DEF_MASK_BIT 8 // Default mask
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#define GRSPW_DEF_ADDR (0xff<<GRSPW_DEF_ADDR_BIT)
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#define GRSPW_DEF_MASK (0xff<<GRSPW_DEF_MASK_BIT)
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///////////////////////////////////////////
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/* GRSPW - Clock Divisor Register - 0x0C */
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#define GRSPW_CLKDIV_START_BIT 8 // Clock divisor startup
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#define GRSPW_CLKDIV_RUN_BIT 0 // Clock divisor run
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#define GRSPW_CLKDIV_START (0xff<<GRSPW_CLKDIV_START_BIT)
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#define GRSPW_CLKDIV_RUN (0xff<<GRSPW_CLKDIV_RUN_BIT)
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#define GRSPW_CLKDIV_MASK (GRSPW_CLKDIV_START|GRSPW_CLKDIV_RUN)
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/////////////////////////////////////////////
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/* GRSPW - Destination key Register - 0x10 */
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#define GRSPW_DK_DESTKEY_BIT 0 // Destination key
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#define GRSPW_DK_DESTKEY (0xff<<GRSPW_DK_DESTKEY_BIT)
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//////////////////////////////////
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/* GRSPW - Time Register - 0x14 */
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#define GRSPW_TIME_CTRL_BIT 0 // Time counter
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#define GRSPW_TIME_CNT_BIT 6 // Time control flags
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#define GRSPW_TIME_CTRL (0x3f<<GRSPW_TIME_CTRL_BIT)
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#define GRSPW_TIME_TCNT (0x3<<GRSPW_TIME_CNT_BIT)
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///////////////////////////////////////////
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/* GRSPW - DMA Control Register - 0x20*N */
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#define GRSPW_DMACTRL_LE_BIT 16 // Link error disable
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#define GRSPW_DMACTRL_SP_BIT 15 // Strip PID
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#define GRSPW_DMACTRL_SA_BIT 14 // Strip address
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#define GRSPW_DMACTRL_EN_BIT 13 // Enable address
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#define GRSPW_DMACTRL_NS_BIT 12 // No spill
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#define GRSPW_DMACTRL_RD_BIT 11 // Rx descriptors available
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#define GRSPW_DMACTRL_RX_BIT 10 // RX active
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#define GRSPW_DMACTRL_AT_BIT 9 // Abort TX
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#define GRSPW_DMACTRL_RA_BIT 8 // RX AHB error
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#define GRSPW_DMACTRL_TA_BIT 7 // TX AHB error
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#define GRSPW_DMACTRL_PR_BIT 6 // Packet received
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#define GRSPW_DMACTRL_PS_BIT 5 // Packet sent
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#define GRSPW_DMACTRL_AI_BIT 4 // AHB error interrupt
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#define GRSPW_DMACTRL_RI_BIT 3 // Receive interrupt
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#define GRSPW_DMACTRL_TI_BIT 2 // Transmit interrupt
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#define GRSPW_DMACTRL_RE_BIT 1 // Receiver enable
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#define GRSPW_DMACTRL_TE_BIT 0 // Transmitter enable
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#define GRSPW_DMACTRL_LE (1<<GRSPW_DMACTRL_LE_BIT)
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#define GRSPW_DMACTRL_SP (1<<GRSPW_DMACTRL_SP_BIT)
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#define GRSPW_DMACTRL_SA (1<<GRSPW_DMACTRL_SA_BIT)
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#define GRSPW_DMACTRL_EN (1<<GRSPW_DMACTRL_EN_BIT)
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#define GRSPW_DMACTRL_NS (1<<GRSPW_DMACTRL_NS_BIT)
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#define GRSPW_DMACTRL_RD (1<<GRSPW_DMACTRL_RD_BIT)
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#define GRSPW_DMACTRL_RX (1<<GRSPW_DMACTRL_RX_BIT)
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#define GRSPW_DMACTRL_AT (1<<GRSPW_DMACTRL_AT_BIT)
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#define GRSPW_DMACTRL_RA (1<<GRSPW_DMACTRL_RA_BIT)
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#define GRSPW_DMACTRL_TA (1<<GRSPW_DMACTRL_TA_BIT)
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#define GRSPW_DMACTRL_PR (1<<GRSPW_DMACTRL_PR_BIT)
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#define GRSPW_DMACTRL_PS (1<<GRSPW_DMACTRL_PS_BIT)
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#define GRSPW_DMACTRL_AI (1<<GRSPW_DMACTRL_AI_BIT)
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#define GRSPW_DMACTRL_RI (1<<GRSPW_DMACTRL_RI_BIT)
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#define GRSPW_DMACTRL_TI (1<<GRSPW_DMACTRL_TI_BIT)
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#define GRSPW_DMACTRL_RE (1<<GRSPW_DMACTRL_RE_BIT)
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#define GRSPW_DMACTRL_TE (1<<GRSPW_DMACTRL_TE_BIT)
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//////////////////////////////////////////////////////////////////////
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/* GRSPW - DMA Channel Max Packet Length Register - (0x20*N + 0x04) */
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#define GRSPW_DMARXLEN_MAX_BIT 0 // RX maximum length
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#define GRSPW_DMARXLEN_MAX (0xffffff<<GRSPW_DMARXLEN_MAX_BIT)
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/* GRSPW - DMA Channel Address Register - (0x20*N + 0x10) */
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#define GRSPW_DMAADR_ADDR_BIT 0 // address
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#define GRSPW_DMAADR_MASK_BIT 8 // Mask
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#define GRSPW_DMAADR_ADDR (0xff<<GRSPW_DMAADR_ADDR_BIT)
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#define GRSPW_DMAADR_MASK (0xff<<GRSPW_DMAADR_MASK_BIT)
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/* RX Buffer Descriptor */
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struct grspw_rxbd {
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volatile unsigned int ctrl;
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volatile unsigned int addr;
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};
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/* TX Buffer Descriptor */
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struct grspw_txbd {
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volatile unsigned int ctrl;
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volatile unsigned int haddr;
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volatile unsigned int dlen;
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volatile unsigned int daddr;
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};
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///////////////////////////////////////////
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/* GRSPW - DMA Receive descriptor word 0 */
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#define GRSPW_RXBD_LEN_BIT 0
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#define GRSPW_RXBD_LEN (0x1ffffff<<GRSPW_RXBD_LEN_BIT)
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#define GRSPW_RXBD_EN (1<<25) // Enable
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#define GRSPW_RXBD_WR (1<<26) // Wrap
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#define GRSPW_RXBD_IE (1<<27) // Interrupt enable
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#define GRSPW_RXBD_EP (1<<28) // EEP termination
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#define GRSPW_RXBD_HC (1<<29) // Header CRC
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#define GRSPW_RXBD_DC (1<<30) // Data CRC
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#define GRSPW_RXBD_TR (1<<31) // Truncated
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////////////////////////////////////////////
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/* GRSPW - DMA Transmit descriptor word 0 */
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#define GRSPW_TXBD_HLEN (0xff<<0) // header length
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#define GRSPW_TXBD_NCL (0xf<<8) // non-CRC bytes
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#define GRSPW_TXBD_EN (1<<12) // Enable
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#define GRSPW_TXBD_WR (1<<13) // Wrap
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#define GRSPW_TXBD_IE (1<<14) // Interrupt enable
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#define GRSPW_TXBD_LE (1<<15) // Link error
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#define GRSPW_TXBD_HC (1<<16) // Append header CRC
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#define GRSPW_TXBD_DC (1<<17) // Append data CRC
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struct grspwregs_str
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{
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volatile int ctrl;
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volatile int status;
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volatile int nodeaddr;
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volatile int clkdiv;
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volatile int destkey;
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volatile int time;
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volatile int unused[2];
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volatile int dmactrl;
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volatile int rxmaxlen;
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volatile int txdesc;
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volatile int rxdesc;
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};
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typedef struct grspwregs_str grspwregs_t;
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struct spacewire_PARAMETERS_str
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{
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int *size;
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volatile char *rx;
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volatile int *rxd;
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char *tx;
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volatile int *txd;
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grspwregs_t *regs;
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} spacewire_PARAMETERS;
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////////////
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// FUNCTIONS
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unsigned int grspw_link_state(grspwregs_t *);
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#endif // GRSPW_H_INCLUDED
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