##// END OF EJS Templates
timegen version 0.0.0.1
timegen version 0.0.0.1

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r165:c9daaae78ba2 spool
r170:3efd0a6e1344 VHDL_0_1_28
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Makefile
21 lines | 517 B | text/x-makefile | MakefileLexer
SREC_PREFIX = RpwLfrApp
SREC_COUNTER_TEXT = 0003
SREC_COUNTER_DATA = 0004
SREC_FSW_REF = rev-1-0-0-7
SREC_SUFFIX = .srec
SREC_TEXT = $(SREC_PREFIX)_$(SREC_COUNTER_TEXT)_text_$(SREC_FSW_REF)$(SREC_SUFFIX)
SREC_DATA = $(SREC_PREFIX)_$(SREC_COUNTER_DATA)_data_$(SREC_FSW_REF)$(SREC_SUFFIX)
OBJCOPY = sparc-rtems-objcopy
OBJCOPY_OPT = -g -v
all: text data
text: fsw
$(OBJCOPY) $(OBJCOPY_OPT) fsw $(SREC_TEXT) -O srec -j .text
data: fsw
$(OBJCOPY) $(OBJCOPY_OPT) fsw $(SREC_DATA) -O srec -j .data
clean:
rm *.srec