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Bug 976 HK_LFR_SC_V_F3 is erroneous
paul -
r349:da15683fb282 R3++ draft
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1 1 #ifndef GRLIB_REGS_H_INCLUDED
2 2 #define GRLIB_REGS_H_INCLUDED
3 3
4 4 #define NB_GPTIMER 3
5 5
6 #include <stdint.h>
7
6 8 struct apbuart_regs_str{
7 9 volatile unsigned int data;
8 10 volatile unsigned int status;
9 11 volatile unsigned int ctrl;
10 12 volatile unsigned int scaler;
11 13 volatile unsigned int fifoDebug;
12 14 };
13 15
14 16 struct grgpio_regs_str{
15 17 volatile int io_port_data_register;
16 18 int io_port_output_register;
17 19 int io_port_direction_register;
18 20 int interrupt_mak_register;
19 21 int interrupt_polarity_register;
20 22 int interrupt_edge_register;
21 23 int bypass_register;
22 24 int reserved;
23 25 // 0x20-0x3c interrupt map register(s)
24 26 };
25 27
26 28 typedef struct {
27 29 volatile unsigned int counter;
28 30 volatile unsigned int reload;
29 31 volatile unsigned int ctrl;
30 32 volatile unsigned int unused;
31 33 } timer_regs_t;
32 34
33 35 //*************
34 36 //*************
35 37 // GPTIMER_REGS
36 38
37 39 #define GPTIMER_CLEAR_IRQ 0x00000010 // clear pending IRQ if any
38 40 #define GPTIMER_LD 0x00000004 // LD load value from the reload register
39 41 #define GPTIMER_EN 0x00000001 // EN enable the timer
40 42 #define GPTIMER_EN_MASK 0xfffffffe // EN enable the timer
41 43 #define GPTIMER_RS 0x00000002 // RS restart
42 44 #define GPTIMER_IE 0x00000008 // IE interrupt enable
43 45 #define GPTIMER_IE_MASK 0xffffffef // IE interrupt enable
44 46
45 47 typedef struct {
46 48 volatile unsigned int scaler_value;
47 49 volatile unsigned int scaler_reload;
48 50 volatile unsigned int conf;
49 51 volatile unsigned int unused0;
50 52 timer_regs_t timer[NB_GPTIMER];
51 53 } gptimer_regs_t;
52 54
53 55 //*********************
54 56 //*********************
55 57 // TIME_MANAGEMENT_REGS
56 58
57 59 #define VAL_SOFTWARE_RESET 0x02 // [0010] software reset
58 60 #define VAL_LFR_SYNCHRONIZED 0x80000000
59 61 #define BIT_SYNCHRONIZATION 31
60 62 #define COARSE_TIME_MASK 0x7fffffff
61 63 #define SYNC_BIT_MASK 0x7f
62 64 #define SYNC_BIT 0x80
63 65 #define BIT_CAL_RELOAD 0x00000010
64 66 #define MASK_CAL_RELOAD 0xffffffef // [1110 1111]
65 67 #define BIT_CAL_ENABLE 0x00000040
66 68 #define MASK_CAL_ENABLE 0xffffffbf // [1011 1111]
67 69 #define BIT_SET_INTERLEAVED 0x00000020 // [0010 0000]
68 70 #define MASK_SET_INTERLEAVED 0xffffffdf // [1101 1111]
69 71 #define BIT_SOFT_RESET 0x00000004 // [0100]
70 72 #define MASK_SOFT_RESET 0xfffffffb // [1011]
71 73
72 74 typedef struct {
73 75 volatile int ctrl; // bit 0 forces the load of the coarse_time_load value and resets the fine_time
74 76 // bit 1 is the soft reset for the time management module
75 77 // bit 2 is the soft reset for the waveform picker and the spectral matrix modules, set to 1 after HW reset
76 78 volatile int coarse_time_load;
77 79 volatile int coarse_time;
78 80 volatile int fine_time;
79 81 // TEMPERATURES
80 82 volatile int temp_pcb; // SEL1 = 0 SEL0 = 0
81 83 volatile int temp_fpga; // SEL1 = 0 SEL0 = 1
82 84 volatile int temp_scm; // SEL1 = 1 SEL0 = 0
83 85 // CALIBRATION
84 86 volatile unsigned int calDACCtrl;
85 87 volatile unsigned int calPrescaler;
86 88 volatile unsigned int calDivisor;
87 89 volatile unsigned int calDataPtr;
88 90 volatile unsigned int calData;
89 91 } time_management_regs_t;
90 92
91 93 //*********************
92 94 //*********************
93 95 // WAVEFORM_PICKER_REGS
94 96
95 97 #define BITS_WFP_STATUS_F3 0xc0 // [1100 0000] check the f3 full bits
96 98 #define BIT_WFP_BUF_F3_0 0x40 // [0100 0000] f3 buffer 0 is full
97 99 #define BIT_WFP_BUF_F3_1 0x80 // [1000 0000] f3 buffer 1 is full
98 100 #define RST_WFP_F3_0 0x00008840 // [1000 1000 0100 0000]
99 101 #define RST_WFP_F3_1 0x00008880 // [1000 1000 1000 0000]
100 102
101 103 #define BITS_WFP_STATUS_F2 0x30 // [0011 0000] get the status bits for f2
102 104 #define SHIFT_WFP_STATUS_F2 4
103 105 #define BIT_WFP_BUF_F2_0 0x10 // [0001 0000] f2 buffer 0 is full
104 106 #define BIT_WFP_BUF_F2_1 0x20 // [0010 0000] f2 buffer 1 is full
105 107 #define RST_WFP_F2_0 0x00004410 // [0100 0100 0001 0000]
106 108 #define RST_WFP_F2_1 0x00004420 // [0100 0100 0010 0000]
107 109
108 110 #define BITS_WFP_STATUS_F1 0x0c // [0000 1100] check the f1 full bits
109 111 #define BIT_WFP_BUF_F1_0 0x04 // [0000 0100] f1 buffer 0 is full
110 112 #define BIT_WFP_BUF_F1_1 0x08 // [0000 1000] f1 buffer 1 is full
111 113 #define RST_WFP_F1_0 0x00002204 // [0010 0010 0000 0100] f1 bits = 0
112 114 #define RST_WFP_F1_1 0x00002208 // [0010 0010 0000 1000] f1 bits = 0
113 115
114 116 #define BITS_WFP_STATUS_F0 0x03 // [0000 0011] check the f0 full bits
115 117 #define RST_WFP_F0_0 0x00001101 // [0001 0001 0000 0001]
116 118 #define RST_WFP_F0_1 0x00001102 // [0001 0001 0000 0010]
117 119
118 120 #define BIT_WFP_BUFFER_0 0x01
119 121 #define BIT_WFP_BUFFER_1 0x02
120 122
121 123 #define RST_BITS_RUN_BURST_EN 0x80 // [1000 0000] burst f2, f1, f0 enable f3, f2, f1, f0
122 124 #define BITS_WFP_ENABLE_ALL 0x0f // [0000 1111] enable f3, f2, f1, f0
123 125 #define BITS_WFP_ENABLE_BURST 0x0c // [0000 1100] enable f3, f2
124 126 #define RUN_BURST_ENABLE_SBM2 0x60 // [0110 0000] enable f2 and f1 burst
125 127 #define RUN_BURST_ENABLE_BURST 0x40 // [0100 0000] f2 burst enabled
126 128
127 129 #define DFLT_WFP_NB_DATA_BY_BUFFER 0xa7f // 0x30 *** 2688 - 1 => nb samples -1
128 130 #define DFLT_WFP_SNAPSHOT_PARAM 0xa80 // 0x34 *** 2688 => nb samples
129 131 #define DFLT_WFP_BUFFER_LENGTH 0x1f8 // buffer length in burst = 3 * 2688 / 16 = 504 = 0x1f8
130 132 #define DFLT_WFP_DELTA_F0_2 0x30 // 48 = 11 0000, max 7 bits
131 133
132 134 // PDB >= 0.1.28, 0x80000f54
133 135 typedef struct{
134 136 int data_shaping; // 0x00 00 *** R2 R1 R0 SP1 SP0 BW
135 137 int run_burst_enable; // 0x04 01 *** [run *** burst f2, f1, f0 *** enable f3, f2, f1, f0 ]
136 138 int addr_data_f0_0; // 0x08
137 139 int addr_data_f0_1; // 0x0c
138 140 int addr_data_f1_0; // 0x10
139 141 int addr_data_f1_1; // 0x14
140 142 int addr_data_f2_0; // 0x18
141 143 int addr_data_f2_1; // 0x1c
142 144 int addr_data_f3_0; // 0x20
143 145 int addr_data_f3_1; // 0x24
144 146 volatile int status; // 0x28
145 147 volatile int delta_snapshot; // 0x2c
146 148 int delta_f0; // 0x30
147 149 int delta_f0_2; // 0x34
148 150 int delta_f1; // 0x38
149 151 int delta_f2; // 0x3c
150 152 int nb_data_by_buffer; // 0x40 number of samples in a buffer = 2688
151 153 int snapshot_param; // 0x44
152 154 int start_date; // 0x48
153 155 //
154 156 volatile unsigned int f0_0_coarse_time; // 0x4c
155 157 volatile unsigned int f0_0_fine_time; // 0x50
156 158 volatile unsigned int f0_1_coarse_time; // 0x54
157 159 volatile unsigned int f0_1_fine_time; // 0x58
158 160 //
159 161 volatile unsigned int f1_0_coarse_time; // 0x5c
160 162 volatile unsigned int f1_0_fine_time; // 0x60
161 163 volatile unsigned int f1_1_coarse_time; // 0x64
162 164 volatile unsigned int f1_1_fine_time; // 0x68
163 165 //
164 166 volatile unsigned int f2_0_coarse_time; // 0x6c
165 167 volatile unsigned int f2_0_fine_time; // 0x70
166 168 volatile unsigned int f2_1_coarse_time; // 0x74
167 169 volatile unsigned int f2_1_fine_time; // 0x78
168 170 //
169 171 volatile unsigned int f3_0_coarse_time; // 0x7c => 0x7c + 0xf54 = 0xd0
170 172 volatile unsigned int f3_0_fine_time; // 0x80
171 173 volatile unsigned int f3_1_coarse_time; // 0x84
172 174 volatile unsigned int f3_1_fine_time; // 0x88
173 175 //
174 176 unsigned int buffer_length; // 0x8c = buffer length in burst 2688 / 16 = 168
175 177 //
176 volatile unsigned int v; // 0x90
177 volatile unsigned int e1; // 0x94
178 volatile unsigned int e2; // 0x98
178 volatile int16_t v_dummy; // 0x90
179 volatile int16_t v; // 0x90
180 volatile int16_t e1_dummy; // 0x94
181 volatile int16_t e1; // 0x94
182 volatile int16_t e2_dummy; // 0x98
183 volatile int16_t e2; // 0x98
179 184 } waveform_picker_regs_0_1_18_t;
180 185
181 186 //*********************
182 187 //*********************
183 188 // SPECTRAL_MATRIX_REGS
184 189
185 190 #define BITS_STATUS_F0 0x03 // [0011]
186 191 #define BITS_STATUS_F1 0x0c // [1100]
187 192 #define BITS_STATUS_F2 0x30 // [0011 0000]
188 193 #define BITS_HK_AA_SM 0x780 // [0111 1000 0000]
189 194 #define BITS_SM_ERR 0x7c0 // [0111 1100 0000]
190 195 #define BITS_STATUS_REG 0x7ff // [0111 1111 1111]
191 196 #define BIT_READY_0 0x1 // [01]
192 197 #define BIT_READY_1 0x2 // [10]
193 198 #define BIT_READY_0_1 0x3 // [11]
194 199 #define BIT_STATUS_F1_0 0x04 // [0100]
195 200 #define BIT_STATUS_F1_1 0x08 // [1000]
196 201 #define BIT_STATUS_F2_0 0x10 // [0001 0000]
197 202 #define BIT_STATUS_F2_1 0x20 // [0010 0000]
198 203 #define DEFAULT_MATRIX_LENGTH 0xc8 // 25 * 128 / 16 = 200 = 0xc8
199 204 #define BIT_IRQ_ON_NEW_MATRIX 0x01
200 205 #define MASK_IRQ_ON_NEW_MATRIX 0xfffffffe
201 206 #define BIT_IRQ_ON_ERROR 0x02
202 207 #define MASK_IRQ_ON_ERROR 0xfffffffd
203 208
204 209 typedef struct {
205 210 volatile int config; // 0x00
206 211 volatile int status; // 0x04
207 212 volatile int f0_0_address; // 0x08
208 213 volatile int f0_1_address; // 0x0C
209 214 //
210 215 volatile int f1_0_address; // 0x10
211 216 volatile int f1_1_address; // 0x14
212 217 volatile int f2_0_address; // 0x18
213 218 volatile int f2_1_address; // 0x1C
214 219 //
215 220 volatile unsigned int f0_0_coarse_time; // 0x20
216 221 volatile unsigned int f0_0_fine_time; // 0x24
217 222 volatile unsigned int f0_1_coarse_time; // 0x28
218 223 volatile unsigned int f0_1_fine_time; // 0x2C
219 224 //
220 225 volatile unsigned int f1_0_coarse_time; // 0x30
221 226 volatile unsigned int f1_0_fine_time; // 0x34
222 227 volatile unsigned int f1_1_coarse_time; // 0x38
223 228 volatile unsigned int f1_1_fine_time; // 0x3C
224 229 //
225 230 volatile unsigned int f2_0_coarse_time; // 0x40
226 231 volatile unsigned int f2_0_fine_time; // 0x44
227 232 volatile unsigned int f2_1_coarse_time; // 0x48
228 233 volatile unsigned int f2_1_fine_time; // 0x4C
229 234 //
230 235 unsigned int matrix_length; // 0x50, length of a spectral matrix in burst 3200 / 16 = 200 = 0xc8
231 236 } spectral_matrix_regs_t;
232 237
233 238 #endif // GRLIB_REGS_H_INCLUDED
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@@ -1,1001 +1,1001
1 1 /** General usage functions and RTEMS tasks.
2 2 *
3 3 * @file
4 4 * @author P. LEROY
5 5 *
6 6 */
7 7
8 8 #include "fsw_misc.h"
9 9
10 10 int16_t hk_lfr_sc_v_f3_as_int16 = 0;
11 11 int16_t hk_lfr_sc_e1_f3_as_int16 = 0;
12 12 int16_t hk_lfr_sc_e2_f3_as_int16 = 0;
13 13
14 14 void timer_configure(unsigned char timer, unsigned int clock_divider,
15 15 unsigned char interrupt_level, rtems_isr (*timer_isr)() )
16 16 {
17 17 /** This function configures a GPTIMER timer instantiated in the VHDL design.
18 18 *
19 19 * @param gptimer_regs points to the APB registers of the GPTIMER IP core.
20 20 * @param timer is the number of the timer in the IP core (several timers can be instantiated).
21 21 * @param clock_divider is the divider of the 1 MHz clock that will be configured.
22 22 * @param interrupt_level is the interrupt level that the timer drives.
23 23 * @param timer_isr is the interrupt subroutine that will be attached to the IRQ driven by the timer.
24 24 *
25 25 * Interrupt levels are described in the SPARC documentation sparcv8.pdf p.76
26 26 *
27 27 */
28 28
29 29 rtems_status_code status;
30 30 rtems_isr_entry old_isr_handler;
31 31
32 32 old_isr_handler = NULL;
33 33
34 34 gptimer_regs->timer[timer].ctrl = INIT_CHAR; // reset the control register
35 35
36 36 status = rtems_interrupt_catch( timer_isr, interrupt_level, &old_isr_handler) ; // see sparcv8.pdf p.76 for interrupt levels
37 37 if (status!=RTEMS_SUCCESSFUL)
38 38 {
39 39 PRINTF("in configure_timer *** ERR rtems_interrupt_catch\n")
40 40 }
41 41
42 42 timer_set_clock_divider( timer, clock_divider);
43 43 }
44 44
45 45 void timer_start(unsigned char timer)
46 46 {
47 47 /** This function starts a GPTIMER timer.
48 48 *
49 49 * @param gptimer_regs points to the APB registers of the GPTIMER IP core.
50 50 * @param timer is the number of the timer in the IP core (several timers can be instantiated).
51 51 *
52 52 */
53 53
54 54 gptimer_regs->timer[timer].ctrl = gptimer_regs->timer[timer].ctrl | GPTIMER_CLEAR_IRQ;
55 55 gptimer_regs->timer[timer].ctrl = gptimer_regs->timer[timer].ctrl | GPTIMER_LD;
56 56 gptimer_regs->timer[timer].ctrl = gptimer_regs->timer[timer].ctrl | GPTIMER_EN;
57 57 gptimer_regs->timer[timer].ctrl = gptimer_regs->timer[timer].ctrl | GPTIMER_RS;
58 58 gptimer_regs->timer[timer].ctrl = gptimer_regs->timer[timer].ctrl | GPTIMER_IE;
59 59 }
60 60
61 61 void timer_stop(unsigned char timer)
62 62 {
63 63 /** This function stops a GPTIMER timer.
64 64 *
65 65 * @param gptimer_regs points to the APB registers of the GPTIMER IP core.
66 66 * @param timer is the number of the timer in the IP core (several timers can be instantiated).
67 67 *
68 68 */
69 69
70 70 gptimer_regs->timer[timer].ctrl = gptimer_regs->timer[timer].ctrl & GPTIMER_EN_MASK;
71 71 gptimer_regs->timer[timer].ctrl = gptimer_regs->timer[timer].ctrl & GPTIMER_IE_MASK;
72 72 gptimer_regs->timer[timer].ctrl = gptimer_regs->timer[timer].ctrl | GPTIMER_CLEAR_IRQ;
73 73 }
74 74
75 75 void timer_set_clock_divider(unsigned char timer, unsigned int clock_divider)
76 76 {
77 77 /** This function sets the clock divider of a GPTIMER timer.
78 78 *
79 79 * @param gptimer_regs points to the APB registers of the GPTIMER IP core.
80 80 * @param timer is the number of the timer in the IP core (several timers can be instantiated).
81 81 * @param clock_divider is the divider of the 1 MHz clock that will be configured.
82 82 *
83 83 */
84 84
85 85 gptimer_regs->timer[timer].reload = clock_divider; // base clock frequency is 1 MHz
86 86 }
87 87
88 88 // WATCHDOG
89 89
90 90 rtems_isr watchdog_isr( rtems_vector_number vector )
91 91 {
92 92 rtems_status_code status_code;
93 93
94 94 status_code = rtems_event_send( Task_id[TASKID_DUMB], RTEMS_EVENT_12 );
95 95
96 96 PRINTF("watchdog_isr *** this is the end, exit(0)\n");
97 97
98 98 exit(0);
99 99 }
100 100
101 101 void watchdog_configure(void)
102 102 {
103 103 /** This function configure the watchdog.
104 104 *
105 105 * @param gptimer_regs points to the APB registers of the GPTIMER IP core.
106 106 * @param timer is the number of the timer in the IP core (several timers can be instantiated).
107 107 *
108 108 * The watchdog is a timer provided by the GPTIMER IP core of the GRLIB.
109 109 *
110 110 */
111 111
112 112 LEON_Mask_interrupt( IRQ_GPTIMER_WATCHDOG ); // mask gptimer/watchdog interrupt during configuration
113 113
114 114 timer_configure( TIMER_WATCHDOG, CLKDIV_WATCHDOG, IRQ_SPARC_GPTIMER_WATCHDOG, watchdog_isr );
115 115
116 116 LEON_Clear_interrupt( IRQ_GPTIMER_WATCHDOG ); // clear gptimer/watchdog interrupt
117 117 }
118 118
119 119 void watchdog_stop(void)
120 120 {
121 121 LEON_Mask_interrupt( IRQ_GPTIMER_WATCHDOG ); // mask gptimer/watchdog interrupt line
122 122 timer_stop( TIMER_WATCHDOG );
123 123 LEON_Clear_interrupt( IRQ_GPTIMER_WATCHDOG ); // clear gptimer/watchdog interrupt
124 124 }
125 125
126 126 void watchdog_reload(void)
127 127 {
128 128 /** This function reloads the watchdog timer counter with the timer reload value.
129 129 *
130 130 * @param void
131 131 *
132 132 * @return void
133 133 *
134 134 */
135 135
136 136 gptimer_regs->timer[TIMER_WATCHDOG].ctrl = gptimer_regs->timer[TIMER_WATCHDOG].ctrl | GPTIMER_LD;
137 137 }
138 138
139 139 void watchdog_start(void)
140 140 {
141 141 /** This function starts the watchdog timer.
142 142 *
143 143 * @param gptimer_regs points to the APB registers of the GPTIMER IP core.
144 144 * @param timer is the number of the timer in the IP core (several timers can be instantiated).
145 145 *
146 146 */
147 147
148 148 LEON_Clear_interrupt( IRQ_GPTIMER_WATCHDOG );
149 149
150 150 gptimer_regs->timer[TIMER_WATCHDOG].ctrl = gptimer_regs->timer[TIMER_WATCHDOG].ctrl | GPTIMER_CLEAR_IRQ;
151 151 gptimer_regs->timer[TIMER_WATCHDOG].ctrl = gptimer_regs->timer[TIMER_WATCHDOG].ctrl | GPTIMER_LD;
152 152 gptimer_regs->timer[TIMER_WATCHDOG].ctrl = gptimer_regs->timer[TIMER_WATCHDOG].ctrl | GPTIMER_EN;
153 153 gptimer_regs->timer[TIMER_WATCHDOG].ctrl = gptimer_regs->timer[TIMER_WATCHDOG].ctrl | GPTIMER_IE;
154 154
155 155 LEON_Unmask_interrupt( IRQ_GPTIMER_WATCHDOG );
156 156
157 157 }
158 158
159 159 int enable_apbuart_transmitter( void ) // set the bit 1, TE Transmitter Enable to 1 in the APBUART control register
160 160 {
161 161 struct apbuart_regs_str *apbuart_regs = (struct apbuart_regs_str *) REGS_ADDR_APBUART;
162 162
163 163 apbuart_regs->ctrl = APBUART_CTRL_REG_MASK_TE;
164 164
165 165 return 0;
166 166 }
167 167
168 168 void set_apbuart_scaler_reload_register(unsigned int regs, unsigned int value)
169 169 {
170 170 /** This function sets the scaler reload register of the apbuart module
171 171 *
172 172 * @param regs is the address of the apbuart registers in memory
173 173 * @param value is the value that will be stored in the scaler register
174 174 *
175 175 * The value shall be set by the software to get data on the serial interface.
176 176 *
177 177 */
178 178
179 179 struct apbuart_regs_str *apbuart_regs = (struct apbuart_regs_str *) regs;
180 180
181 181 apbuart_regs->scaler = value;
182 182
183 183 BOOT_PRINTF1("OK *** apbuart port scaler reload register set to 0x%x\n", value)
184 184 }
185 185
186 186 //************
187 187 // RTEMS TASKS
188 188
189 189 rtems_task load_task(rtems_task_argument argument)
190 190 {
191 191 BOOT_PRINTF("in LOAD *** \n")
192 192
193 193 rtems_status_code status;
194 194 unsigned int i;
195 195 unsigned int j;
196 196 rtems_name name_watchdog_rate_monotonic; // name of the watchdog rate monotonic
197 197 rtems_id watchdog_period_id; // id of the watchdog rate monotonic period
198 198
199 199 watchdog_period_id = RTEMS_ID_NONE;
200 200
201 201 name_watchdog_rate_monotonic = rtems_build_name( 'L', 'O', 'A', 'D' );
202 202
203 203 status = rtems_rate_monotonic_create( name_watchdog_rate_monotonic, &watchdog_period_id );
204 204 if( status != RTEMS_SUCCESSFUL ) {
205 205 PRINTF1( "in LOAD *** rtems_rate_monotonic_create failed with status of %d\n", status )
206 206 }
207 207
208 208 i = 0;
209 209 j = 0;
210 210
211 211 watchdog_configure();
212 212
213 213 watchdog_start();
214 214
215 215 set_sy_lfr_watchdog_enabled( true );
216 216
217 217 while(1){
218 218 status = rtems_rate_monotonic_period( watchdog_period_id, WATCHDOG_PERIOD );
219 219 watchdog_reload();
220 220 i = i + 1;
221 221 if ( i == WATCHDOG_LOOP_PRINTF )
222 222 {
223 223 i = 0;
224 224 j = j + 1;
225 225 PRINTF1("%d\n", j)
226 226 }
227 227 #ifdef DEBUG_WATCHDOG
228 228 if (j == WATCHDOG_LOOP_DEBUG )
229 229 {
230 230 status = rtems_task_delete(RTEMS_SELF);
231 231 }
232 232 #endif
233 233 }
234 234 }
235 235
236 236 rtems_task hous_task(rtems_task_argument argument)
237 237 {
238 238 rtems_status_code status;
239 239 rtems_status_code spare_status;
240 240 rtems_id queue_id;
241 241 rtems_rate_monotonic_period_status period_status;
242 242 bool isSynchronized;
243 243
244 244 queue_id = RTEMS_ID_NONE;
245 245 memset(&period_status, 0, sizeof(rtems_rate_monotonic_period_status));
246 246 isSynchronized = false;
247 247
248 248 status = get_message_queue_id_send( &queue_id );
249 249 if (status != RTEMS_SUCCESSFUL)
250 250 {
251 251 PRINTF1("in HOUS *** ERR get_message_queue_id_send %d\n", status)
252 252 }
253 253
254 254 BOOT_PRINTF("in HOUS ***\n");
255 255
256 256 if (rtems_rate_monotonic_ident( name_hk_rate_monotonic, &HK_id) != RTEMS_SUCCESSFUL) {
257 257 status = rtems_rate_monotonic_create( name_hk_rate_monotonic, &HK_id );
258 258 if( status != RTEMS_SUCCESSFUL ) {
259 259 PRINTF1( "rtems_rate_monotonic_create failed with status of %d\n", status );
260 260 }
261 261 }
262 262
263 263 status = rtems_rate_monotonic_cancel(HK_id);
264 264 if( status != RTEMS_SUCCESSFUL ) {
265 265 PRINTF1( "ERR *** in HOUS *** rtems_rate_monotonic_cancel(HK_id) ***code: %d\n", status );
266 266 }
267 267 else {
268 268 DEBUG_PRINTF("OK *** in HOUS *** rtems_rate_monotonic_cancel(HK_id)\n");
269 269 }
270 270
271 271 // startup phase
272 272 status = rtems_rate_monotonic_period( HK_id, SY_LFR_TIME_SYN_TIMEOUT_in_ticks );
273 273 status = rtems_rate_monotonic_get_status( HK_id, &period_status );
274 274 DEBUG_PRINTF1("startup HK, HK_id status = %d\n", period_status.state)
275 275 while( (period_status.state != RATE_MONOTONIC_EXPIRED)
276 276 && (isSynchronized == false) ) // after SY_LFR_TIME_SYN_TIMEOUT ms, starts HK anyway
277 277 {
278 278 if ((time_management_regs->coarse_time & VAL_LFR_SYNCHRONIZED) == INT32_ALL_0) // check time synchronization
279 279 {
280 280 isSynchronized = true;
281 281 }
282 282 else
283 283 {
284 284 status = rtems_rate_monotonic_get_status( HK_id, &period_status );
285 285
286 286 status = rtems_task_wake_after( HK_SYNC_WAIT ); // wait HK_SYNCH_WAIT 100 ms = 10 * 10 ms
287 287 }
288 288 }
289 289 status = rtems_rate_monotonic_cancel(HK_id);
290 290 DEBUG_PRINTF1("startup HK, HK_id status = %d\n", period_status.state)
291 291
292 292 set_hk_lfr_reset_cause( POWER_ON );
293 293
294 294 while(1){ // launch the rate monotonic task
295 295 status = rtems_rate_monotonic_period( HK_id, HK_PERIOD );
296 296 if ( status != RTEMS_SUCCESSFUL ) {
297 297 PRINTF1( "in HOUS *** ERR period: %d\n", status);
298 298 spare_status = rtems_event_send( Task_id[TASKID_DUMB], RTEMS_EVENT_6 );
299 299 }
300 300 else {
301 301 housekeeping_packet.packetSequenceControl[BYTE_0] = (unsigned char) (sequenceCounterHK >> SHIFT_1_BYTE);
302 302 housekeeping_packet.packetSequenceControl[BYTE_1] = (unsigned char) (sequenceCounterHK );
303 303 increment_seq_counter( &sequenceCounterHK );
304 304
305 305 housekeeping_packet.time[BYTE_0] = (unsigned char) (time_management_regs->coarse_time >> SHIFT_3_BYTES);
306 306 housekeeping_packet.time[BYTE_1] = (unsigned char) (time_management_regs->coarse_time >> SHIFT_2_BYTES);
307 307 housekeeping_packet.time[BYTE_2] = (unsigned char) (time_management_regs->coarse_time >> SHIFT_1_BYTE);
308 308 housekeeping_packet.time[BYTE_3] = (unsigned char) (time_management_regs->coarse_time);
309 309 housekeeping_packet.time[BYTE_4] = (unsigned char) (time_management_regs->fine_time >> SHIFT_1_BYTE);
310 310 housekeeping_packet.time[BYTE_5] = (unsigned char) (time_management_regs->fine_time);
311 311
312 312 spacewire_update_hk_lfr_link_state( &housekeeping_packet.lfr_status_word[0] );
313 313
314 314 spacewire_read_statistics();
315 315
316 316 update_hk_with_grspw_stats();
317 317
318 318 set_hk_lfr_time_not_synchro();
319 319
320 320 housekeeping_packet.hk_lfr_q_sd_fifo_size_max = hk_lfr_q_sd_fifo_size_max;
321 321 housekeeping_packet.hk_lfr_q_rv_fifo_size_max = hk_lfr_q_rv_fifo_size_max;
322 322 housekeeping_packet.hk_lfr_q_p0_fifo_size_max = hk_lfr_q_p0_fifo_size_max;
323 323 housekeeping_packet.hk_lfr_q_p1_fifo_size_max = hk_lfr_q_p1_fifo_size_max;
324 324 housekeeping_packet.hk_lfr_q_p2_fifo_size_max = hk_lfr_q_p2_fifo_size_max;
325 325
326 326 housekeeping_packet.sy_lfr_common_parameters_spare = parameter_dump_packet.sy_lfr_common_parameters_spare;
327 327 housekeeping_packet.sy_lfr_common_parameters = parameter_dump_packet.sy_lfr_common_parameters;
328 328 get_temperatures( housekeeping_packet.hk_lfr_temp_scm );
329 329 get_v_e1_e2_f3( housekeeping_packet.hk_lfr_sc_v_f3 );
330 330 get_cpu_load( (unsigned char *) &housekeeping_packet.hk_lfr_cpu_load );
331 331
332 332 hk_lfr_le_me_he_update();
333 333
334 334 // SEND PACKET
335 335 status = rtems_message_queue_send( queue_id, &housekeeping_packet,
336 336 PACKET_LENGTH_HK + CCSDS_TC_TM_PACKET_OFFSET + CCSDS_PROTOCOLE_EXTRA_BYTES);
337 337 if (status != RTEMS_SUCCESSFUL) {
338 338 PRINTF1("in HOUS *** ERR send: %d\n", status)
339 339 }
340 340 }
341 341 }
342 342
343 343 PRINTF("in HOUS *** deleting task\n")
344 344
345 345 status = rtems_task_delete( RTEMS_SELF ); // should not return
346 346
347 347 return;
348 348 }
349 349
350 350 rtems_task avgv_task(rtems_task_argument argument)
351 351 {
352 352 #define MOVING_AVERAGE 16
353 353 rtems_status_code status;
354 static unsigned int v[MOVING_AVERAGE] = {0};
355 static unsigned int e1[MOVING_AVERAGE] = {0};
356 static unsigned int e2[MOVING_AVERAGE] = {0};
357 float average_v;
358 float average_e1;
359 float average_e2;
360 float newValue_v;
361 float newValue_e1;
362 float newValue_e2;
354 static int32_t v[MOVING_AVERAGE] = {0};
355 static int32_t e1[MOVING_AVERAGE] = {0};
356 static int32_t e2[MOVING_AVERAGE] = {0};
357 int32_t average_v;
358 int32_t average_e1;
359 int32_t average_e2;
360 int32_t newValue_v;
361 int32_t newValue_e1;
362 int32_t newValue_e2;
363 363 unsigned char k;
364 364 unsigned char indexOfOldValue;
365 365
366 366 BOOT_PRINTF("in AVGV ***\n");
367 367
368 if (rtems_rate_monotonic_ident( name_avgv_rate_monotonic, &HK_id) != RTEMS_SUCCESSFUL) {
368 if (rtems_rate_monotonic_ident( name_avgv_rate_monotonic, &AVGV_id) != RTEMS_SUCCESSFUL) {
369 369 status = rtems_rate_monotonic_create( name_avgv_rate_monotonic, &AVGV_id );
370 370 if( status != RTEMS_SUCCESSFUL ) {
371 371 PRINTF1( "rtems_rate_monotonic_create failed with status of %d\n", status );
372 372 }
373 373 }
374 374
375 375 status = rtems_rate_monotonic_cancel(AVGV_id);
376 376 if( status != RTEMS_SUCCESSFUL ) {
377 377 PRINTF1( "ERR *** in AVGV *** rtems_rate_monotonic_cancel(AVGV_id) ***code: %d\n", status );
378 378 }
379 379 else {
380 380 DEBUG_PRINTF("OK *** in AVGV *** rtems_rate_monotonic_cancel(AVGV_id)\n");
381 381 }
382 382
383 383 // initialize values
384 384 indexOfOldValue = MOVING_AVERAGE - 1;
385 average_v = INIT_FLOAT;
386 average_e1 = INIT_FLOAT;
387 average_e2 = INIT_FLOAT;
388 newValue_v = INIT_FLOAT;
389 newValue_e1 = INIT_FLOAT;
390 newValue_e2 = INIT_FLOAT;
385 average_v = 0;
386 average_e1 = 0;
387 average_e2 = 0;
388 newValue_v = 0;
389 newValue_e1 = 0;
390 newValue_e2 = 0;
391 391
392 392 k = INIT_CHAR;
393 393
394 394 while(1)
395 395 { // launch the rate monotonic task
396 396 status = rtems_rate_monotonic_period( AVGV_id, AVGV_PERIOD );
397 397 if ( status != RTEMS_SUCCESSFUL )
398 398 {
399 399 PRINTF1( "in AVGV *** ERR period: %d\n", status);
400 400 }
401 401 else
402 402 {
403 403 // get new values
404 newValue_v = waveform_picker_regs->v;
405 newValue_e1 = waveform_picker_regs->e1;
406 newValue_e2 = waveform_picker_regs->e2;
404 newValue_v = (int32_t) waveform_picker_regs->v;
405 newValue_e1 = (int32_t) waveform_picker_regs->e1;
406 newValue_e2 = (int32_t) waveform_picker_regs->e2;
407 407
408 408 // compute the moving average
409 409 average_v = average_v + newValue_v - v[k];
410 410 average_e1 = average_e1 + newValue_e1 - e1[k];
411 411 average_e2 = average_e2 + newValue_e2 - e2[k];
412 412
413 413 // store new values in buffers
414 414 v[k] = newValue_v;
415 415 e1[k] = newValue_e1;
416 416 e2[k] = newValue_e2;
417 417 }
418 418 if (k == (MOVING_AVERAGE-1))
419 419 {
420 420 k = 0;
421 421 }
422 422 else
423 423 {
424 424 k++;
425 425 }
426 426 //update int16 values
427 hk_lfr_sc_v_f3_as_int16 = (int16_t) (average_v / ((float) MOVING_AVERAGE) );
428 hk_lfr_sc_e1_f3_as_int16 = (int16_t) (average_e1 / ((float) MOVING_AVERAGE) );
429 hk_lfr_sc_e2_f3_as_int16 = (int16_t) (average_e2 / ((float) MOVING_AVERAGE) );
427 hk_lfr_sc_v_f3_as_int16 = (int16_t) (average_v / MOVING_AVERAGE );
428 hk_lfr_sc_e1_f3_as_int16 = (int16_t) (average_e1 / MOVING_AVERAGE );
429 hk_lfr_sc_e2_f3_as_int16 = (int16_t) (average_e2 / MOVING_AVERAGE );
430 430 }
431 431
432 432 PRINTF("in AVGV *** deleting task\n");
433 433
434 434 status = rtems_task_delete( RTEMS_SELF ); // should not return
435 435
436 436 return;
437 437 }
438 438
439 439 rtems_task dumb_task( rtems_task_argument unused )
440 440 {
441 441 /** This RTEMS taks is used to print messages without affecting the general behaviour of the software.
442 442 *
443 443 * @param unused is the starting argument of the RTEMS task
444 444 *
445 445 * The DUMB taks waits for RTEMS events and print messages depending on the incoming events.
446 446 *
447 447 */
448 448
449 449 unsigned int i;
450 450 unsigned int intEventOut;
451 451 unsigned int coarse_time = 0;
452 452 unsigned int fine_time = 0;
453 453 rtems_event_set event_out;
454 454
455 455 event_out = EVENT_SETS_NONE_PENDING;
456 456
457 457 BOOT_PRINTF("in DUMB *** \n")
458 458
459 459 while(1){
460 460 rtems_event_receive(RTEMS_EVENT_0 | RTEMS_EVENT_1 | RTEMS_EVENT_2 | RTEMS_EVENT_3
461 461 | RTEMS_EVENT_4 | RTEMS_EVENT_5 | RTEMS_EVENT_6 | RTEMS_EVENT_7
462 462 | RTEMS_EVENT_8 | RTEMS_EVENT_9 | RTEMS_EVENT_12 | RTEMS_EVENT_13
463 463 | RTEMS_EVENT_14,
464 464 RTEMS_WAIT | RTEMS_EVENT_ANY, RTEMS_NO_TIMEOUT, &event_out); // wait for an RTEMS_EVENT
465 465 intEventOut = (unsigned int) event_out;
466 466 for ( i=0; i<NB_RTEMS_EVENTS; i++)
467 467 {
468 468 if ( ((intEventOut >> i) & 1) != 0)
469 469 {
470 470 coarse_time = time_management_regs->coarse_time;
471 471 fine_time = time_management_regs->fine_time;
472 472 if (i==EVENT_12)
473 473 {
474 474 PRINTF1("%s\n", DUMB_MESSAGE_12)
475 475 }
476 476 if (i==EVENT_13)
477 477 {
478 478 PRINTF1("%s\n", DUMB_MESSAGE_13)
479 479 }
480 480 if (i==EVENT_14)
481 481 {
482 482 PRINTF1("%s\n", DUMB_MESSAGE_1)
483 483 }
484 484 }
485 485 }
486 486 }
487 487 }
488 488
489 489 //*****************************
490 490 // init housekeeping parameters
491 491
492 492 void init_housekeeping_parameters( void )
493 493 {
494 494 /** This function initialize the housekeeping_packet global variable with default values.
495 495 *
496 496 */
497 497
498 498 unsigned int i = 0;
499 499 unsigned char *parameters;
500 500 unsigned char sizeOfHK;
501 501
502 502 sizeOfHK = sizeof( Packet_TM_LFR_HK_t );
503 503
504 504 parameters = (unsigned char*) &housekeeping_packet;
505 505
506 506 for(i = 0; i< sizeOfHK; i++)
507 507 {
508 508 parameters[i] = INIT_CHAR;
509 509 }
510 510
511 511 housekeeping_packet.targetLogicalAddress = CCSDS_DESTINATION_ID;
512 512 housekeeping_packet.protocolIdentifier = CCSDS_PROTOCOLE_ID;
513 513 housekeeping_packet.reserved = DEFAULT_RESERVED;
514 514 housekeeping_packet.userApplication = CCSDS_USER_APP;
515 515 housekeeping_packet.packetID[0] = (unsigned char) (APID_TM_HK >> SHIFT_1_BYTE);
516 516 housekeeping_packet.packetID[1] = (unsigned char) (APID_TM_HK);
517 517 housekeeping_packet.packetSequenceControl[0] = TM_PACKET_SEQ_CTRL_STANDALONE;
518 518 housekeeping_packet.packetSequenceControl[1] = TM_PACKET_SEQ_CNT_DEFAULT;
519 519 housekeeping_packet.packetLength[0] = (unsigned char) (PACKET_LENGTH_HK >> SHIFT_1_BYTE);
520 520 housekeeping_packet.packetLength[1] = (unsigned char) (PACKET_LENGTH_HK );
521 521 housekeeping_packet.spare1_pusVersion_spare2 = DEFAULT_SPARE1_PUSVERSION_SPARE2;
522 522 housekeeping_packet.serviceType = TM_TYPE_HK;
523 523 housekeeping_packet.serviceSubType = TM_SUBTYPE_HK;
524 524 housekeeping_packet.destinationID = TM_DESTINATION_ID_GROUND;
525 525 housekeeping_packet.sid = SID_HK;
526 526
527 527 // init status word
528 528 housekeeping_packet.lfr_status_word[0] = DEFAULT_STATUS_WORD_BYTE0;
529 529 housekeeping_packet.lfr_status_word[1] = DEFAULT_STATUS_WORD_BYTE1;
530 530 // init software version
531 531 housekeeping_packet.lfr_sw_version[0] = SW_VERSION_N1;
532 532 housekeeping_packet.lfr_sw_version[1] = SW_VERSION_N2;
533 533 housekeeping_packet.lfr_sw_version[BYTE_2] = SW_VERSION_N3;
534 534 housekeeping_packet.lfr_sw_version[BYTE_3] = SW_VERSION_N4;
535 535 // init fpga version
536 536 parameters = (unsigned char *) (REGS_ADDR_VHDL_VERSION);
537 537 housekeeping_packet.lfr_fpga_version[BYTE_0] = parameters[BYTE_1]; // n1
538 538 housekeeping_packet.lfr_fpga_version[BYTE_1] = parameters[BYTE_2]; // n2
539 539 housekeeping_packet.lfr_fpga_version[BYTE_2] = parameters[BYTE_3]; // n3
540 540
541 541 housekeeping_packet.hk_lfr_q_sd_fifo_size = MSG_QUEUE_COUNT_SEND;
542 542 housekeeping_packet.hk_lfr_q_rv_fifo_size = MSG_QUEUE_COUNT_RECV;
543 543 housekeeping_packet.hk_lfr_q_p0_fifo_size = MSG_QUEUE_COUNT_PRC0;
544 544 housekeeping_packet.hk_lfr_q_p1_fifo_size = MSG_QUEUE_COUNT_PRC1;
545 545 housekeeping_packet.hk_lfr_q_p2_fifo_size = MSG_QUEUE_COUNT_PRC2;
546 546 }
547 547
548 548 void increment_seq_counter( unsigned short *packetSequenceControl )
549 549 {
550 550 /** This function increment the sequence counter passes in argument.
551 551 *
552 552 * The increment does not affect the grouping flag. In case of an overflow, the counter is reset to 0.
553 553 *
554 554 */
555 555
556 556 unsigned short segmentation_grouping_flag;
557 557 unsigned short sequence_cnt;
558 558
559 559 segmentation_grouping_flag = TM_PACKET_SEQ_CTRL_STANDALONE << SHIFT_1_BYTE; // keep bits 7 downto 6
560 560 sequence_cnt = (*packetSequenceControl) & SEQ_CNT_MASK; // [0011 1111 1111 1111]
561 561
562 562 if ( sequence_cnt < SEQ_CNT_MAX)
563 563 {
564 564 sequence_cnt = sequence_cnt + 1;
565 565 }
566 566 else
567 567 {
568 568 sequence_cnt = 0;
569 569 }
570 570
571 571 *packetSequenceControl = segmentation_grouping_flag | sequence_cnt ;
572 572 }
573 573
574 574 void getTime( unsigned char *time)
575 575 {
576 576 /** This function write the current local time in the time buffer passed in argument.
577 577 *
578 578 */
579 579
580 580 time[0] = (unsigned char) (time_management_regs->coarse_time>>SHIFT_3_BYTES);
581 581 time[1] = (unsigned char) (time_management_regs->coarse_time>>SHIFT_2_BYTES);
582 582 time[2] = (unsigned char) (time_management_regs->coarse_time>>SHIFT_1_BYTE);
583 583 time[3] = (unsigned char) (time_management_regs->coarse_time);
584 584 time[4] = (unsigned char) (time_management_regs->fine_time>>SHIFT_1_BYTE);
585 585 time[5] = (unsigned char) (time_management_regs->fine_time);
586 586 }
587 587
588 588 unsigned long long int getTimeAsUnsignedLongLongInt( )
589 589 {
590 590 /** This function write the current local time in the time buffer passed in argument.
591 591 *
592 592 */
593 593 unsigned long long int time;
594 594
595 595 time = ( (unsigned long long int) (time_management_regs->coarse_time & COARSE_TIME_MASK) << SHIFT_2_BYTES )
596 596 + time_management_regs->fine_time;
597 597
598 598 return time;
599 599 }
600 600
601 601 void send_dumb_hk( void )
602 602 {
603 603 Packet_TM_LFR_HK_t dummy_hk_packet;
604 604 unsigned char *parameters;
605 605 unsigned int i;
606 606 rtems_id queue_id;
607 607
608 608 queue_id = RTEMS_ID_NONE;
609 609
610 610 dummy_hk_packet.targetLogicalAddress = CCSDS_DESTINATION_ID;
611 611 dummy_hk_packet.protocolIdentifier = CCSDS_PROTOCOLE_ID;
612 612 dummy_hk_packet.reserved = DEFAULT_RESERVED;
613 613 dummy_hk_packet.userApplication = CCSDS_USER_APP;
614 614 dummy_hk_packet.packetID[0] = (unsigned char) (APID_TM_HK >> SHIFT_1_BYTE);
615 615 dummy_hk_packet.packetID[1] = (unsigned char) (APID_TM_HK);
616 616 dummy_hk_packet.packetSequenceControl[0] = TM_PACKET_SEQ_CTRL_STANDALONE;
617 617 dummy_hk_packet.packetSequenceControl[1] = TM_PACKET_SEQ_CNT_DEFAULT;
618 618 dummy_hk_packet.packetLength[0] = (unsigned char) (PACKET_LENGTH_HK >> SHIFT_1_BYTE);
619 619 dummy_hk_packet.packetLength[1] = (unsigned char) (PACKET_LENGTH_HK );
620 620 dummy_hk_packet.spare1_pusVersion_spare2 = DEFAULT_SPARE1_PUSVERSION_SPARE2;
621 621 dummy_hk_packet.serviceType = TM_TYPE_HK;
622 622 dummy_hk_packet.serviceSubType = TM_SUBTYPE_HK;
623 623 dummy_hk_packet.destinationID = TM_DESTINATION_ID_GROUND;
624 624 dummy_hk_packet.time[0] = (unsigned char) (time_management_regs->coarse_time >> SHIFT_3_BYTES);
625 625 dummy_hk_packet.time[1] = (unsigned char) (time_management_regs->coarse_time >> SHIFT_2_BYTES);
626 626 dummy_hk_packet.time[BYTE_2] = (unsigned char) (time_management_regs->coarse_time >> SHIFT_1_BYTE);
627 627 dummy_hk_packet.time[BYTE_3] = (unsigned char) (time_management_regs->coarse_time);
628 628 dummy_hk_packet.time[BYTE_4] = (unsigned char) (time_management_regs->fine_time >> SHIFT_1_BYTE);
629 629 dummy_hk_packet.time[BYTE_5] = (unsigned char) (time_management_regs->fine_time);
630 630 dummy_hk_packet.sid = SID_HK;
631 631
632 632 // init status word
633 633 dummy_hk_packet.lfr_status_word[0] = INT8_ALL_F;
634 634 dummy_hk_packet.lfr_status_word[1] = INT8_ALL_F;
635 635 // init software version
636 636 dummy_hk_packet.lfr_sw_version[0] = SW_VERSION_N1;
637 637 dummy_hk_packet.lfr_sw_version[1] = SW_VERSION_N2;
638 638 dummy_hk_packet.lfr_sw_version[BYTE_2] = SW_VERSION_N3;
639 639 dummy_hk_packet.lfr_sw_version[BYTE_3] = SW_VERSION_N4;
640 640 // init fpga version
641 641 parameters = (unsigned char *) (REGS_ADDR_WAVEFORM_PICKER + APB_OFFSET_VHDL_REV);
642 642 dummy_hk_packet.lfr_fpga_version[BYTE_0] = parameters[BYTE_1]; // n1
643 643 dummy_hk_packet.lfr_fpga_version[BYTE_1] = parameters[BYTE_2]; // n2
644 644 dummy_hk_packet.lfr_fpga_version[BYTE_2] = parameters[BYTE_3]; // n3
645 645
646 646 parameters = (unsigned char *) &dummy_hk_packet.hk_lfr_cpu_load;
647 647
648 648 for (i=0; i<(BYTE_POS_HK_REACTION_WHEELS_FREQUENCY - BYTE_POS_HK_LFR_CPU_LOAD); i++)
649 649 {
650 650 parameters[i] = INT8_ALL_F;
651 651 }
652 652
653 653 get_message_queue_id_send( &queue_id );
654 654
655 655 rtems_message_queue_send( queue_id, &dummy_hk_packet,
656 656 PACKET_LENGTH_HK + CCSDS_TC_TM_PACKET_OFFSET + CCSDS_PROTOCOLE_EXTRA_BYTES);
657 657 }
658 658
659 659 void get_temperatures( unsigned char *temperatures )
660 660 {
661 661 unsigned char* temp_scm_ptr;
662 662 unsigned char* temp_pcb_ptr;
663 663 unsigned char* temp_fpga_ptr;
664 664
665 665 // SEL1 SEL0
666 666 // 0 0 => PCB
667 667 // 0 1 => FPGA
668 668 // 1 0 => SCM
669 669
670 670 temp_scm_ptr = (unsigned char *) &time_management_regs->temp_scm;
671 671 temp_pcb_ptr = (unsigned char *) &time_management_regs->temp_pcb;
672 672 temp_fpga_ptr = (unsigned char *) &time_management_regs->temp_fpga;
673 673
674 674 temperatures[ BYTE_0 ] = temp_scm_ptr[ BYTE_2 ];
675 675 temperatures[ BYTE_1 ] = temp_scm_ptr[ BYTE_3 ];
676 676 temperatures[ BYTE_2 ] = temp_pcb_ptr[ BYTE_2 ];
677 677 temperatures[ BYTE_3 ] = temp_pcb_ptr[ BYTE_3 ];
678 678 temperatures[ BYTE_4 ] = temp_fpga_ptr[ BYTE_2 ];
679 679 temperatures[ BYTE_5 ] = temp_fpga_ptr[ BYTE_3 ];
680 680 }
681 681
682 682 void get_v_e1_e2_f3( unsigned char *spacecraft_potential )
683 683 {
684 684 unsigned char* v_ptr;
685 685 unsigned char* e1_ptr;
686 686 unsigned char* e2_ptr;
687 687
688 688 v_ptr = (unsigned char *) &hk_lfr_sc_v_f3_as_int16;
689 689 e1_ptr = (unsigned char *) &hk_lfr_sc_e1_f3_as_int16;
690 690 e2_ptr = (unsigned char *) &hk_lfr_sc_e2_f3_as_int16;
691 691
692 692 spacecraft_potential[BYTE_0] = v_ptr[0];
693 693 spacecraft_potential[BYTE_1] = v_ptr[1];
694 694 spacecraft_potential[BYTE_2] = e1_ptr[0];
695 695 spacecraft_potential[BYTE_3] = e1_ptr[1];
696 696 spacecraft_potential[BYTE_4] = e2_ptr[0];
697 697 spacecraft_potential[BYTE_5] = e2_ptr[1];
698 698 }
699 699
700 700 void get_cpu_load( unsigned char *resource_statistics )
701 701 {
702 702 unsigned char cpu_load;
703 703
704 704 cpu_load = lfr_rtems_cpu_usage_report();
705 705
706 706 // HK_LFR_CPU_LOAD
707 707 resource_statistics[0] = cpu_load;
708 708
709 709 // HK_LFR_CPU_LOAD_MAX
710 710 if (cpu_load > resource_statistics[1])
711 711 {
712 712 resource_statistics[1] = cpu_load;
713 713 }
714 714
715 715 // CPU_LOAD_AVE
716 716 resource_statistics[BYTE_2] = 0;
717 717
718 718 #ifndef PRINT_TASK_STATISTICS
719 719 rtems_cpu_usage_reset();
720 720 #endif
721 721
722 722 }
723 723
724 724 void set_hk_lfr_sc_potential_flag( bool state )
725 725 {
726 726 if (state == true)
727 727 {
728 728 housekeeping_packet.lfr_status_word[1] =
729 729 housekeeping_packet.lfr_status_word[1] | STATUS_WORD_SC_POTENTIAL_FLAG_BIT; // [0100 0000]
730 730 }
731 731 else
732 732 {
733 733 housekeeping_packet.lfr_status_word[1] =
734 734 housekeeping_packet.lfr_status_word[1] & STATUS_WORD_SC_POTENTIAL_FLAG_MASK; // [1011 1111]
735 735 }
736 736 }
737 737
738 738 void set_sy_lfr_pas_filter_enabled( bool state )
739 739 {
740 740 if (state == true)
741 741 {
742 742 housekeeping_packet.lfr_status_word[1] =
743 743 housekeeping_packet.lfr_status_word[1] | STATUS_WORD_PAS_FILTER_ENABLED_BIT; // [0010 0000]
744 744 }
745 745 else
746 746 {
747 747 housekeeping_packet.lfr_status_word[1] =
748 748 housekeeping_packet.lfr_status_word[1] & STATUS_WORD_PAS_FILTER_ENABLED_MASK; // [1101 1111]
749 749 }
750 750 }
751 751
752 752 void set_sy_lfr_watchdog_enabled( bool state )
753 753 {
754 754 if (state == true)
755 755 {
756 756 housekeeping_packet.lfr_status_word[1] =
757 757 housekeeping_packet.lfr_status_word[1] | STATUS_WORD_WATCHDOG_BIT; // [0001 0000]
758 758 }
759 759 else
760 760 {
761 761 housekeeping_packet.lfr_status_word[1] =
762 762 housekeeping_packet.lfr_status_word[1] & STATUS_WORD_WATCHDOG_MASK; // [1110 1111]
763 763 }
764 764 }
765 765
766 766 void set_hk_lfr_calib_enable( bool state )
767 767 {
768 768 if (state == true)
769 769 {
770 770 housekeeping_packet.lfr_status_word[1] =
771 771 housekeeping_packet.lfr_status_word[1] | STATUS_WORD_CALIB_BIT; // [0000 1000]
772 772 }
773 773 else
774 774 {
775 775 housekeeping_packet.lfr_status_word[1] =
776 776 housekeeping_packet.lfr_status_word[1] & STATUS_WORD_CALIB_MASK; // [1111 0111]
777 777 }
778 778 }
779 779
780 780 void set_hk_lfr_reset_cause( enum lfr_reset_cause_t lfr_reset_cause )
781 781 {
782 782 housekeeping_packet.lfr_status_word[1] =
783 783 housekeeping_packet.lfr_status_word[1] & STATUS_WORD_RESET_CAUSE_MASK; // [1111 1000]
784 784
785 785 housekeeping_packet.lfr_status_word[1] = housekeeping_packet.lfr_status_word[1]
786 786 | (lfr_reset_cause & STATUS_WORD_RESET_CAUSE_BITS ); // [0000 0111]
787 787
788 788 }
789 789
790 790 void increment_hk_counter( unsigned char newValue, unsigned char oldValue, unsigned int *counter )
791 791 {
792 792 int delta;
793 793
794 794 delta = 0;
795 795
796 796 if (newValue >= oldValue)
797 797 {
798 798 delta = newValue - oldValue;
799 799 }
800 800 else
801 801 {
802 802 delta = (CONST_256 - oldValue) + newValue;
803 803 }
804 804
805 805 *counter = *counter + delta;
806 806 }
807 807
808 808 void hk_lfr_le_update( void )
809 809 {
810 810 static hk_lfr_le_t old_hk_lfr_le = {0};
811 811 hk_lfr_le_t new_hk_lfr_le;
812 812 unsigned int counter;
813 813
814 814 counter = (((unsigned int) housekeeping_packet.hk_lfr_le_cnt[0]) * CONST_256) + housekeeping_packet.hk_lfr_le_cnt[1];
815 815
816 816 // DPU
817 817 new_hk_lfr_le.dpu_spw_parity = housekeeping_packet.hk_lfr_dpu_spw_parity;
818 818 new_hk_lfr_le.dpu_spw_disconnect= housekeeping_packet.hk_lfr_dpu_spw_disconnect;
819 819 new_hk_lfr_le.dpu_spw_escape = housekeeping_packet.hk_lfr_dpu_spw_escape;
820 820 new_hk_lfr_le.dpu_spw_credit = housekeeping_packet.hk_lfr_dpu_spw_credit;
821 821 new_hk_lfr_le.dpu_spw_write_sync= housekeeping_packet.hk_lfr_dpu_spw_write_sync;
822 822 // TIMECODE
823 823 new_hk_lfr_le.timecode_erroneous= housekeeping_packet.hk_lfr_timecode_erroneous;
824 824 new_hk_lfr_le.timecode_missing = housekeeping_packet.hk_lfr_timecode_missing;
825 825 new_hk_lfr_le.timecode_invalid = housekeeping_packet.hk_lfr_timecode_invalid;
826 826 // TIME
827 827 new_hk_lfr_le.time_timecode_it = housekeeping_packet.hk_lfr_time_timecode_it;
828 828 new_hk_lfr_le.time_not_synchro = housekeeping_packet.hk_lfr_time_not_synchro;
829 829 new_hk_lfr_le.time_timecode_ctr = housekeeping_packet.hk_lfr_time_timecode_ctr;
830 830 //AHB
831 831 new_hk_lfr_le.ahb_correctable = housekeeping_packet.hk_lfr_ahb_correctable;
832 832 // housekeeping_packet.hk_lfr_dpu_spw_rx_ahb => not handled by the grspw driver
833 833 // housekeeping_packet.hk_lfr_dpu_spw_tx_ahb => not handled by the grspw driver
834 834
835 835 // update the le counter
836 836 // DPU
837 837 increment_hk_counter( new_hk_lfr_le.dpu_spw_parity, old_hk_lfr_le.dpu_spw_parity, &counter );
838 838 increment_hk_counter( new_hk_lfr_le.dpu_spw_disconnect,old_hk_lfr_le.dpu_spw_disconnect, &counter );
839 839 increment_hk_counter( new_hk_lfr_le.dpu_spw_escape, old_hk_lfr_le.dpu_spw_escape, &counter );
840 840 increment_hk_counter( new_hk_lfr_le.dpu_spw_credit, old_hk_lfr_le.dpu_spw_credit, &counter );
841 841 increment_hk_counter( new_hk_lfr_le.dpu_spw_write_sync,old_hk_lfr_le.dpu_spw_write_sync, &counter );
842 842 // TIMECODE
843 843 increment_hk_counter( new_hk_lfr_le.timecode_erroneous,old_hk_lfr_le.timecode_erroneous, &counter );
844 844 increment_hk_counter( new_hk_lfr_le.timecode_missing, old_hk_lfr_le.timecode_missing, &counter );
845 845 increment_hk_counter( new_hk_lfr_le.timecode_invalid, old_hk_lfr_le.timecode_invalid, &counter );
846 846 // TIME
847 847 increment_hk_counter( new_hk_lfr_le.time_timecode_it, old_hk_lfr_le.time_timecode_it, &counter );
848 848 increment_hk_counter( new_hk_lfr_le.time_not_synchro, old_hk_lfr_le.time_not_synchro, &counter );
849 849 increment_hk_counter( new_hk_lfr_le.time_timecode_ctr, old_hk_lfr_le.time_timecode_ctr, &counter );
850 850 // AHB
851 851 increment_hk_counter( new_hk_lfr_le.ahb_correctable, old_hk_lfr_le.ahb_correctable, &counter );
852 852
853 853 // DPU
854 854 old_hk_lfr_le.dpu_spw_parity = new_hk_lfr_le.dpu_spw_parity;
855 855 old_hk_lfr_le.dpu_spw_disconnect= new_hk_lfr_le.dpu_spw_disconnect;
856 856 old_hk_lfr_le.dpu_spw_escape = new_hk_lfr_le.dpu_spw_escape;
857 857 old_hk_lfr_le.dpu_spw_credit = new_hk_lfr_le.dpu_spw_credit;
858 858 old_hk_lfr_le.dpu_spw_write_sync= new_hk_lfr_le.dpu_spw_write_sync;
859 859 // TIMECODE
860 860 old_hk_lfr_le.timecode_erroneous= new_hk_lfr_le.timecode_erroneous;
861 861 old_hk_lfr_le.timecode_missing = new_hk_lfr_le.timecode_missing;
862 862 old_hk_lfr_le.timecode_invalid = new_hk_lfr_le.timecode_invalid;
863 863 // TIME
864 864 old_hk_lfr_le.time_timecode_it = new_hk_lfr_le.time_timecode_it;
865 865 old_hk_lfr_le.time_not_synchro = new_hk_lfr_le.time_not_synchro;
866 866 old_hk_lfr_le.time_timecode_ctr = new_hk_lfr_le.time_timecode_ctr;
867 867 //AHB
868 868 old_hk_lfr_le.ahb_correctable = new_hk_lfr_le.ahb_correctable;
869 869 // housekeeping_packet.hk_lfr_dpu_spw_rx_ahb => not handled by the grspw driver
870 870 // housekeeping_packet.hk_lfr_dpu_spw_tx_ahb => not handled by the grspw driver
871 871
872 872 // update housekeeping packet counters, convert unsigned int numbers in 2 bytes numbers
873 873 // LE
874 874 housekeeping_packet.hk_lfr_le_cnt[0] = (unsigned char) ((counter & BYTE0_MASK) >> SHIFT_1_BYTE);
875 875 housekeeping_packet.hk_lfr_le_cnt[1] = (unsigned char) (counter & BYTE1_MASK);
876 876 }
877 877
878 878 void hk_lfr_me_update( void )
879 879 {
880 880 static hk_lfr_me_t old_hk_lfr_me = {0};
881 881 hk_lfr_me_t new_hk_lfr_me;
882 882 unsigned int counter;
883 883
884 884 counter = (((unsigned int) housekeeping_packet.hk_lfr_me_cnt[0]) * CONST_256) + housekeeping_packet.hk_lfr_me_cnt[1];
885 885
886 886 // get the current values
887 887 new_hk_lfr_me.dpu_spw_early_eop = housekeeping_packet.hk_lfr_dpu_spw_early_eop;
888 888 new_hk_lfr_me.dpu_spw_invalid_addr = housekeeping_packet.hk_lfr_dpu_spw_invalid_addr;
889 889 new_hk_lfr_me.dpu_spw_eep = housekeeping_packet.hk_lfr_dpu_spw_eep;
890 890 new_hk_lfr_me.dpu_spw_rx_too_big = housekeeping_packet.hk_lfr_dpu_spw_rx_too_big;
891 891
892 892 // update the me counter
893 893 increment_hk_counter( new_hk_lfr_me.dpu_spw_early_eop, old_hk_lfr_me.dpu_spw_early_eop, &counter );
894 894 increment_hk_counter( new_hk_lfr_me.dpu_spw_invalid_addr, old_hk_lfr_me.dpu_spw_invalid_addr, &counter );
895 895 increment_hk_counter( new_hk_lfr_me.dpu_spw_eep, old_hk_lfr_me.dpu_spw_eep, &counter );
896 896 increment_hk_counter( new_hk_lfr_me.dpu_spw_rx_too_big, old_hk_lfr_me.dpu_spw_rx_too_big, &counter );
897 897
898 898 // store the counters for the next time
899 899 old_hk_lfr_me.dpu_spw_early_eop = new_hk_lfr_me.dpu_spw_early_eop;
900 900 old_hk_lfr_me.dpu_spw_invalid_addr = new_hk_lfr_me.dpu_spw_invalid_addr;
901 901 old_hk_lfr_me.dpu_spw_eep = new_hk_lfr_me.dpu_spw_eep;
902 902 old_hk_lfr_me.dpu_spw_rx_too_big = new_hk_lfr_me.dpu_spw_rx_too_big;
903 903
904 904 // update housekeeping packet counters, convert unsigned int numbers in 2 bytes numbers
905 905 // ME
906 906 housekeeping_packet.hk_lfr_me_cnt[0] = (unsigned char) ((counter & BYTE0_MASK) >> SHIFT_1_BYTE);
907 907 housekeeping_packet.hk_lfr_me_cnt[1] = (unsigned char) (counter & BYTE1_MASK);
908 908 }
909 909
910 910 void hk_lfr_le_me_he_update()
911 911 {
912 912
913 913 unsigned int hk_lfr_he_cnt;
914 914
915 915 hk_lfr_he_cnt = (((unsigned int) housekeeping_packet.hk_lfr_he_cnt[0]) * 256) + housekeeping_packet.hk_lfr_he_cnt[1];
916 916
917 917 //update the low severity error counter
918 918 hk_lfr_le_update( );
919 919
920 920 //update the medium severity error counter
921 921 hk_lfr_me_update();
922 922
923 923 //update the high severity error counter
924 924 hk_lfr_he_cnt = 0;
925 925
926 926 // update housekeeping packet counters, convert unsigned int numbers in 2 bytes numbers
927 927 // HE
928 928 housekeeping_packet.hk_lfr_he_cnt[0] = (unsigned char) ((hk_lfr_he_cnt & BYTE0_MASK) >> SHIFT_1_BYTE);
929 929 housekeeping_packet.hk_lfr_he_cnt[1] = (unsigned char) (hk_lfr_he_cnt & BYTE1_MASK);
930 930
931 931 }
932 932
933 933 void set_hk_lfr_time_not_synchro()
934 934 {
935 935 static unsigned char synchroLost = 1;
936 936 int synchronizationBit;
937 937
938 938 // get the synchronization bit
939 939 synchronizationBit =
940 940 (time_management_regs->coarse_time & VAL_LFR_SYNCHRONIZED) >> BIT_SYNCHRONIZATION; // 1000 0000 0000 0000
941 941
942 942 switch (synchronizationBit)
943 943 {
944 944 case 0:
945 945 if (synchroLost == 1)
946 946 {
947 947 synchroLost = 0;
948 948 }
949 949 break;
950 950 case 1:
951 951 if (synchroLost == 0 )
952 952 {
953 953 synchroLost = 1;
954 954 increase_unsigned_char_counter(&housekeeping_packet.hk_lfr_time_not_synchro);
955 955 update_hk_lfr_last_er_fields( RID_LE_LFR_TIME, CODE_NOT_SYNCHRO );
956 956 }
957 957 break;
958 958 default:
959 959 PRINTF1("in hk_lfr_time_not_synchro *** unexpected value for synchronizationBit = %d\n", synchronizationBit);
960 960 break;
961 961 }
962 962
963 963 }
964 964
965 965 void set_hk_lfr_ahb_correctable() // CRITICITY L
966 966 {
967 967 /** This function builds the error counter hk_lfr_ahb_correctable using the statistics provided
968 968 * by the Cache Control Register (ASI 2, offset 0) and in the Register Protection Control Register (ASR16) on the
969 969 * detected errors in the cache, in the integer unit and in the floating point unit.
970 970 *
971 971 * @param void
972 972 *
973 973 * @return void
974 974 *
975 975 * All errors are summed to set the value of the hk_lfr_ahb_correctable counter.
976 976 *
977 977 */
978 978
979 979 unsigned int ahb_correctable;
980 980 unsigned int instructionErrorCounter;
981 981 unsigned int dataErrorCounter;
982 982 unsigned int fprfErrorCounter;
983 983 unsigned int iurfErrorCounter;
984 984
985 985 instructionErrorCounter = 0;
986 986 dataErrorCounter = 0;
987 987 fprfErrorCounter = 0;
988 988 iurfErrorCounter = 0;
989 989
990 990 CCR_getInstructionAndDataErrorCounters( &instructionErrorCounter, &dataErrorCounter);
991 991 ASR16_get_FPRF_IURF_ErrorCounters( &fprfErrorCounter, &iurfErrorCounter);
992 992
993 993 ahb_correctable = instructionErrorCounter
994 994 + dataErrorCounter
995 995 + fprfErrorCounter
996 996 + iurfErrorCounter
997 997 + housekeeping_packet.hk_lfr_ahb_correctable;
998 998
999 999 housekeeping_packet.hk_lfr_ahb_correctable = (unsigned char) (ahb_correctable & INT8_ALL_F); // [1111 1111]
1000 1000
1001 1001 }
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