##// END OF EJS Templates
ASM restart sequence updated at the interrupt service routine level...
paul -
r259:af93852650f9 R3a
parent child
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@@ -1,2 +1,2
1 1 3081d1f9bb20b2b64a192585337a292a9804e0c5 LFR_basic-parameters
2 4ffa7549495b4d1e5ddbda520569468a5e3b8779 header/lfr_common_headers
2 ad7698268954c5d3d203a3b3ad09fcdf2d536472 header/lfr_common_headers
@@ -13,6 +13,8
13 13 #define VENDORID_GAISLER 0x01
14 14
15 15 // CCR
16 #define POS_FT 19
17 //
16 18 #define POS_ITE 12
17 19 #define COUNTER_FIELD_ITE 0x00003000 // 0000 0000 0000 0000 0011 0000 0000 0000
18 20 #define COUNTER_MASK_ITE 0xffffcfff // 1111 1111 1111 1111 1100 1111 1111 1111
@@ -28,10 +30,16
28 30 #define COUNTER_MASK_DDE 0xffffff3f // 1111 1111 1111 1111 1111 1111 0011 1111
29 31
30 32 // ASR16
33 #define POS_FPFTID 30
31 34 #define POS_FPRF 27
35 #define POS_FDI 16 // FP RF protection enable/disable
36 #define POS_IUFTID 14
37 #define POS_IURF 11
38 #define POS_IDI 0 // IU RF protection enable/disable
39
32 40 #define COUNTER_FIELD_FPRF 0x38000000 // 0011 1000 0000 0000 0000 0000 0000 0000
33 41 #define COUNTER_MASK_FPRF 0xc7ffffff // 1100 0111 1111 1111 1111 1111 1111 1111
34 #define POS_IURF 11
42
35 43 #define COUNTER_FIELD_IURF 0x00003800 // 0000 0000 0000 0000 0011 1000 0000 0000
36 44 #define COUNTER_MASK_IURF 0xffffc7ff // 1111 1111 1111 1111 1100 0111 1111 1111
37 45
@@ -92,32 +100,6 static void CCR_enableDataCache()
92 100 CCR_setValue(cacheControlRegister);
93 101 }
94 102
95 static void CCR_faultTolerantScheme()
96 {
97 // [20:19] FT scheme (FT) - “00” = no FT, “01” = 4-bit checking implemented
98 unsigned int cacheControlRegister;
99 unsigned int *plugAndPlayRegister;
100 unsigned int vendorId;
101 unsigned int deviceId;
102
103 plugAndPlayRegister = (unsigned int*) REGS_ADDR_PLUGANDPLAY;
104 vendorId = ( (*plugAndPlayRegister) & 0xff000000 ) >> 24;
105 deviceId = ( (*plugAndPlayRegister) & 0x00fff000 ) >> 12;
106
107 if( (vendorId == VENDORID_GAISLER) & (deviceId ==DEVICEID_LEON3FT) )
108 {
109 PRINTF("in faultTolerantScheme *** Leon3FT detected, configure the CCR FT bits\n");
110 cacheControlRegister = CCR_getValue();
111 cacheControlRegister = (cacheControlRegister | 0xc);
112 CCR_setValue(cacheControlRegister);
113 }
114 else
115 {
116 PRINTF("in faultTolerantScheme *** not a Leon3FT, no need to configure the CCR FT bits\n");
117 PRINTF2(" *** vendorID = 0x%x, deviceId = 0x%x\n", vendorId, deviceId);
118 }
119 }
120
121 103 static void CCR_enableInstructionBurstFetch()
122 104 {
123 105 // [16] Instruction burst fetch (IB). This bit enables burst fill during instruction fetch.
@@ -128,7 +110,7 static void CCR_enableInstructionBurstFe
128 110 CCR_setValue(cacheControlRegister);
129 111 }
130 112
131 static void CCR_getInstructionAndDataErrorCounters( unsigned int* instructionErrorCounter, unsigned int* dataErrorCounter )
113 void CCR_getInstructionAndDataErrorCounters( unsigned int* instructionErrorCounter, unsigned int* dataErrorCounter )
132 114 {
133 115 // [13:12] Instruction Tag Errors (ITE) - Number of detected parity errors in the instruction tag cache.
134 116 // Only available if fault-tolerance is enabled (FT field in this register is non-zero).
@@ -163,7 +145,12 static void CCR_getInstructionAndDataErr
163 145 //*******************************************
164 146 // ASR16 Register protection control register
165 147
166 static void ASR16_get_FPRF_IURF_ErrorCounters( unsigned int* fprfErrorCounter, unsigned int* iurfErrorCounter)
148 static void ASR16_resetRegisterProtectionControlRegister()
149 {
150 *asr16Ptr = 0x00;
151 }
152
153 void ASR16_get_FPRF_IURF_ErrorCounters( unsigned int* fprfErrorCounter, unsigned int* iurfErrorCounter)
167 154 {
168 155 /** This function is used to retrieve the integer unit register file error counter and the floating point unit
169 156 * register file error counter
@@ -189,4 +176,46 static void ASR16_get_FPRF_IURF_ErrorCou
189 176 *asr16Ptr = asr16;
190 177 }
191 178
179 static void faultTolerantScheme()
180 {
181 // [20:19] FT scheme (FT) - “00” = no FT, “01” = 4-bit checking implemented
182 unsigned int cacheControlRegister;
183 unsigned int *plugAndPlayRegister;
184 unsigned int vendorId;
185 unsigned int deviceId;
186
187 plugAndPlayRegister = (unsigned int*) REGS_ADDR_PLUGANDPLAY;
188 vendorId = ( (*plugAndPlayRegister) & 0xff000000 ) >> 24;
189 deviceId = ( (*plugAndPlayRegister) & 0x00fff000 ) >> 12;
190
191 cacheControlRegister = CCR_getValue();
192
193 if( (vendorId == VENDORID_GAISLER) & (deviceId ==DEVICEID_LEON3FT) )
194 {
195 PRINTF("in faultTolerantScheme *** Leon3FT detected\n");
196 PRINTF2(" *** vendorID = 0x%x, deviceId = 0x%x\n", vendorId, deviceId);
197 PRINTF1("ASR16 IU RF protection, bit 0 (IDI) is: 0x%x (0 => protection enabled)\n",
198 (*asr16Ptr >> POS_IDI) & 1);
199 PRINTF1("ASR16 FP RF protection, bit 16 (FDI) is: 0x%x (0 => protection enabled)\n",
200 (*asr16Ptr >> POS_FDI) & 1);
201 PRINTF1("ASR16 IU FT ID bits [15:14] is: 0x%x (2 => 8-bit parity without restart)\n",
202 (*asr16Ptr >> POS_IUFTID) & 0x3);
203 PRINTF1("ASR16 FP FT ID bits [31:30] is: 0x%x (1 => 4-bit parity with restart)\n",
204 (*asr16Ptr >> POS_FPFTID) & 0x03);
205 PRINTF1("CCR FT bits [20:19] are: 0x%x (1 => 4-bit parity with restart)\n",
206 (cacheControlRegister >> POS_FT) & 0x3 );
207
208 // CCR The FFT bits are just read, the FT scheme is set to “01” = 4-bit checking implemented by default
209
210 // ASR16 Ancillary State Register configuration (Register protection control register)
211 // IU RF protection is set by default, bit 0 IDI = 0
212 // FP RF protection is set by default, bit 16 FDI = 0
213 }
214 else
215 {
216 PRINTF("in faultTolerantScheme *** not a Leon3FT not detected\n");
217 PRINTF2(" *** vendorID = 0x%x, deviceId = 0x%x\n", vendorId, deviceId);
218 }
219 }
220
192 221 #endif /* GSCMEMORY_HPP_ */
@@ -10,6 +10,7
10 10 #include "fsw_spacewire.h"
11 11 #include "lfr_cpu_usage_report.h"
12 12
13
13 14 enum lfr_reset_cause_t{
14 15 UNKNOWN_CAUSE,
15 16 POWER_ON,
@@ -20,6 +21,8 enum lfr_reset_cause_t{
20 21 };
21 22
22 23 extern gptimer_regs_t *gptimer_regs;
24 extern void ASR16_get_FPRF_IURF_ErrorCounters( unsigned int*, unsigned int* );
25 extern void CCR_getInstructionAndDataErrorCounters( unsigned int*, unsigned int* );
23 26
24 27 #define LFR_RESET_CAUSE_UNKNOWN_CAUSE 0
25 28
@@ -82,6 +82,8 typedef struct asm_msg
82 82 unsigned int fineTimeSBM;
83 83 } asm_msg;
84 84
85 extern unsigned char thisIsAnASMRestart;
86
85 87 extern volatile int sm_f0[ ];
86 88 extern volatile int sm_f1[ ];
87 89 extern volatile int sm_f2[ ];
@@ -32,6 +32,7 int fdSPW = 0;
32 32 int fdUART = 0;
33 33 unsigned char lfrCurrentMode;
34 34 unsigned char pa_bia_status_info;
35 unsigned char thisIsAnASMRestart = 0;
35 36
36 37 // WAVEFORMS GLOBAL VARIABLES // 2048 * 3 * 4 + 2 * 4 = 24576 + 8 bytes = 24584
37 38 // 97 * 256 = 24832 => delta = 248 bytes = 62 words
@@ -81,19 +81,22 void initCache()
81 81
82 82 unsigned int cacheControlRegister;
83 83
84 CCR_resetCacheControlRegister();
85 ASR16_resetRegisterProtectionControlRegister();
86
84 87 cacheControlRegister = CCR_getValue();
85 PRINTF1("(0) cacheControlRegister = %x\n", cacheControlRegister);
86
87 CCR_resetCacheControlRegister();
88 PRINTF1("(0) CCR - Cache Control Register = %x\n", cacheControlRegister);
89 PRINTF1("(0) ASR16 = %x\n", *asr16Ptr);
88 90
89 91 CCR_enableInstructionCache(); // ICS bits
90 92 CCR_enableDataCache(); // DCS bits
91 93 CCR_enableInstructionBurstFetch(); // IB bit
92 94
95 faultTolerantScheme();
96
93 97 cacheControlRegister = CCR_getValue();
94 PRINTF1("(1) cacheControlRegister = %x\n", cacheControlRegister);
95
96 CCR_faultTolerantScheme();
98 PRINTF1("(1) CCR - Cache Control Register = %x\n", cacheControlRegister);
99 PRINTF1("(1) ASR16 Register protection control register = %x\n", *asr16Ptr);
97 100
98 101 PRINTF("\n");
99 102 }
@@ -198,8 +201,6 rtems_task Init( rtems_task_argument ign
198 201
199 202 // **************************
200 203 // <SPACEWIRE INITIALIZATION>
201 grspw_timecode_callback = &timecode_irq_handler;
202
203 204 status_spw = spacewire_open_link(); // (1) open the link
204 205 if ( status_spw != RTEMS_SUCCESSFUL )
205 206 {
@@ -268,8 +269,11 rtems_task Init( rtems_task_argument ign
268 269
269 270 set_hk_lfr_sc_potential_flag( true );
270 271
271 // start the timer used for the detection of missing parameters (started also by the timecode_irq_handler ISR)
272 status = rtems_timer_fire_after( timecode_timer_id, TIMECODE_TIMER_TIMEOUT, timecode_timer_routine, NULL );
272 // start the timer to detect a missing spacewire timecode
273 // the timeout is larger because the spw IP needs to receive several valid timecodes before generating a tickout
274 // if a tickout is generated, the timer is restarted
275 status = rtems_timer_fire_after( timecode_timer_id, TIMECODE_TIMER_TIMEOUT_INIT, timecode_timer_routine, NULL );
276 grspw_timecode_callback = &timecode_irq_handler;
273 277
274 278 status = rtems_task_delete(RTEMS_SELF);
275 279
@@ -232,21 +232,21 rtems_task hous_task(rtems_task_argument
232 232 PRINTF1("in HOUS *** ERR get_message_queue_id_send %d\n", status)
233 233 }
234 234
235 BOOT_PRINTF("in HOUS ***\n")
235 BOOT_PRINTF("in HOUS ***\n");
236 236
237 237 if (rtems_rate_monotonic_ident( name_hk_rate_monotonic, &HK_id) != RTEMS_SUCCESSFUL) {
238 238 status = rtems_rate_monotonic_create( name_hk_rate_monotonic, &HK_id );
239 239 if( status != RTEMS_SUCCESSFUL ) {
240 PRINTF1( "rtems_rate_monotonic_create failed with status of %d\n", status )
240 PRINTF1( "rtems_rate_monotonic_create failed with status of %d\n", status );
241 241 }
242 242 }
243 243
244 244 status = rtems_rate_monotonic_cancel(HK_id);
245 245 if( status != RTEMS_SUCCESSFUL ) {
246 PRINTF1( "ERR *** in HOUS *** rtems_rate_monotonic_cancel(HK_id) ***code: %d\n", status )
246 PRINTF1( "ERR *** in HOUS *** rtems_rate_monotonic_cancel(HK_id) ***code: %d\n", status );
247 247 }
248 248 else {
249 DEBUG_PRINTF("OK *** in HOUS *** rtems_rate_monotonic_cancel(HK_id)\n")
249 DEBUG_PRINTF("OK *** in HOUS *** rtems_rate_monotonic_cancel(HK_id)\n");
250 250 }
251 251
252 252 // startup phase
@@ -339,7 +339,7 rtems_task dumb_task( rtems_task_argumen
339 339 unsigned int fine_time = 0;
340 340 rtems_event_set event_out;
341 341
342 char *DumbMessages[14] = {"in DUMB *** default", // RTEMS_EVENT_0
342 char *DumbMessages[15] = {"in DUMB *** default", // RTEMS_EVENT_0
343 343 "in DUMB *** timecode_irq_handler", // RTEMS_EVENT_1
344 344 "in DUMB *** f3 buffer changed", // RTEMS_EVENT_2
345 345 "in DUMB *** in SMIQ *** Error sending event to AVF0", // RTEMS_EVENT_3
@@ -352,7 +352,8 rtems_task dumb_task( rtems_task_argumen
352 352 "VHDL ERR *** waveform picker", // RTEMS_EVENT_10
353 353 "VHDL ERR *** unexpected ready matrix values", // RTEMS_EVENT_11
354 354 "WATCHDOG timer", // RTEMS_EVENT_12
355 "TIMECODE timer" // RTEMS_EVENT_13
355 "TIMECODE timer", // RTEMS_EVENT_13
356 "TIMECODE ISR" // RTEMS_EVENT_14
356 357 };
357 358
358 359 BOOT_PRINTF("in DUMB *** \n")
@@ -360,7 +361,8 rtems_task dumb_task( rtems_task_argumen
360 361 while(1){
361 362 rtems_event_receive(RTEMS_EVENT_0 | RTEMS_EVENT_1 | RTEMS_EVENT_2 | RTEMS_EVENT_3
362 363 | RTEMS_EVENT_4 | RTEMS_EVENT_5 | RTEMS_EVENT_6 | RTEMS_EVENT_7
363 | RTEMS_EVENT_8 | RTEMS_EVENT_9 | RTEMS_EVENT_12 | RTEMS_EVENT_13,
364 | RTEMS_EVENT_8 | RTEMS_EVENT_9 | RTEMS_EVENT_12 | RTEMS_EVENT_13
365 | RTEMS_EVENT_14,
364 366 RTEMS_WAIT | RTEMS_EVENT_ANY, RTEMS_NO_TIMEOUT, &event_out); // wait for an RTEMS_EVENT
365 367 intEventOut = (unsigned int) event_out;
366 368 for ( i=0; i<32; i++)
@@ -377,6 +379,10 rtems_task dumb_task( rtems_task_argumen
377 379 {
378 380 PRINTF1("%s\n", DumbMessages[13])
379 381 }
382 if (i==14)
383 {
384 PRINTF1("%s\n", DumbMessages[1])
385 }
380 386 }
381 387 }
382 388 }
@@ -735,3 +741,43 void set_hk_lfr_time_not_synchro()
735 741 }
736 742
737 743 }
744
745 void set_hk_lfr_ahb_correctable()
746 {
747 /** This function builds the error counter hk_lfr_ahb_correctable using the statistics provided
748 * by the Cache Control Register (ASI 2, offset 0) and in the Register Protection Control Register (ASR16) on the
749 * detected errors in the cache, in the integer unit and in the floating point unit.
750 *
751 * @param void
752 *
753 * @return void
754 *
755 * All errors are summed to set the value of the hk_lfr_ahb_correctable counter.
756 *
757 */
758
759 unsigned int ahb_correctable;
760 unsigned int instructionErrorCounter;
761 unsigned int dataErrorCounter;
762 unsigned int fprfErrorCounter;
763 unsigned int iurfErrorCounter;
764
765 CCR_getInstructionAndDataErrorCounters( &instructionErrorCounter, &dataErrorCounter);
766 ASR16_get_FPRF_IURF_ErrorCounters( &fprfErrorCounter, &iurfErrorCounter);
767
768 ahb_correctable = instructionErrorCounter
769 + dataErrorCounter
770 + fprfErrorCounter
771 + iurfErrorCounter
772 + housekeeping_packet.hk_lfr_ahb_correctable;
773
774 if (ahb_correctable > 255)
775 {
776 housekeeping_packet.hk_lfr_ahb_correctable = 255;
777 }
778 else
779 {
780 housekeeping_packet.hk_lfr_ahb_correctable = ahb_correctable;
781 }
782
783 }
@@ -680,11 +680,14 void increase_unsigned_char_counter( uns
680 680
681 681 rtems_timer_service_routine timecode_timer_routine( rtems_id timer_id, void *user_data )
682 682 {
683 static unsigned char initStep = 1;
683 684
684 685 unsigned char currentTimecodeCtr;
685 686
686 687 currentTimecodeCtr = (unsigned char) (grspwPtr[0] & TIMECODE_MASK);
687 688
689 if (initStep == 1)
690 {
688 691 if (currentTimecodeCtr == previousTimecodeCtr)
689 692 {
690 693 //************************
@@ -705,6 +708,14 rtems_timer_service_routine timecode_tim
705 708 // this is why the timer has fired
706 709 increase_unsigned_char_counter( &housekeeping_packet.hk_lfr_timecode_invalid );
707 710 }
711 }
712 else
713 {
714 initStep = 1;
715 //************************
716 // HK_LFR_TIMECODE_MISSING
717 increase_unsigned_char_counter( &housekeeping_packet.hk_lfr_timecode_missing );
718 }
708 719
709 720 rtems_event_send( Task_id[TASKID_DUMB], RTEMS_EVENT_13 );
710 721 }
@@ -824,6 +835,10 void timecode_irq_handler( void *pDev, v
824 835 // launch the timecode timer to detect missing or invalid timecodes
825 836 previousTimecodeCtr = incomingTimecode; // update the previousTimecodeCtr value
826 837 status = rtems_timer_fire_after( timecode_timer_id, TIMECODE_TIMER_TIMEOUT, timecode_timer_routine, NULL );
838 if (status != RTEMS_SUCCESSFUL)
839 {
840 rtems_event_send( Task_id[TASKID_DUMB], RTEMS_EVENT_14 );
841 }
827 842 }
828 843
829 844 void init_header_cwf( Header_TM_LFR_SCIENCE_CWF_t *header )
@@ -41,7 +41,7 rtems_task avf0_task( rtems_task_argumen
41 41 rtems_event_set event_out;
42 42 rtems_status_code status;
43 43 rtems_id queue_id_prc0;
44 asm_msg msgForMATR;
44 asm_msg msgForPRC;
45 45 ring_node *nodeForAveraging;
46 46 ring_node *ring_node_tab[8];
47 47 ring_node_asm *current_ring_node_asm_burst_sbm_f0;
@@ -78,9 +78,9 rtems_task avf0_task( rtems_task_argumen
78 78
79 79 //****************************************
80 80 // initialize the mesage for the MATR task
81 msgForMATR.norm = current_ring_node_asm_norm_f0;
82 msgForMATR.burst_sbm = current_ring_node_asm_burst_sbm_f0;
83 msgForMATR.event = 0x00; // this composite event will be sent to the PRC0 task
81 msgForPRC.norm = current_ring_node_asm_norm_f0;
82 msgForPRC.burst_sbm = current_ring_node_asm_burst_sbm_f0;
83 msgForPRC.event = 0x00; // this composite event will be sent to the PRC0 task
84 84 //
85 85 //****************************************
86 86
@@ -98,7 +98,7 rtems_task avf0_task( rtems_task_argumen
98 98 current_ring_node_asm_burst_sbm_f0->matrix,
99 99 ring_node_tab,
100 100 nb_norm_bp1, nb_sbm_bp1,
101 &msgForMATR );
101 &msgForPRC );
102 102
103 103 // update nb_average
104 104 nb_norm_bp1 = nb_norm_bp1 + NB_SM_BEFORE_AVF0;
@@ -114,11 +114,11 rtems_task avf0_task( rtems_task_argumen
114 114 current_ring_node_asm_burst_sbm_f0 = current_ring_node_asm_burst_sbm_f0->next;
115 115 if ( lfrCurrentMode == LFR_MODE_BURST )
116 116 {
117 msgForMATR.event = msgForMATR.event | RTEMS_EVENT_BURST_BP1_F0;
117 msgForPRC.event = msgForPRC.event | RTEMS_EVENT_BURST_BP1_F0;
118 118 }
119 119 else if ( (lfrCurrentMode == LFR_MODE_SBM1) || (lfrCurrentMode == LFR_MODE_SBM2) )
120 120 {
121 msgForMATR.event = msgForMATR.event | RTEMS_EVENT_SBM_BP1_F0;
121 msgForPRC.event = msgForPRC.event | RTEMS_EVENT_SBM_BP1_F0;
122 122 }
123 123 }
124 124
@@ -127,11 +127,11 rtems_task avf0_task( rtems_task_argumen
127 127 nb_sbm_bp2 = 0;
128 128 if ( lfrCurrentMode == LFR_MODE_BURST )
129 129 {
130 msgForMATR.event = msgForMATR.event | RTEMS_EVENT_BURST_BP2_F0;
130 msgForPRC.event = msgForPRC.event | RTEMS_EVENT_BURST_BP2_F0;
131 131 }
132 132 else if ( (lfrCurrentMode == LFR_MODE_SBM1) || (lfrCurrentMode == LFR_MODE_SBM2) )
133 133 {
134 msgForMATR.event = msgForMATR.event | RTEMS_EVENT_SBM_BP2_F0;
134 msgForPRC.event = msgForPRC.event | RTEMS_EVENT_SBM_BP2_F0;
135 135 }
136 136 }
137 137
@@ -143,7 +143,7 rtems_task avf0_task( rtems_task_argumen
143 143 if ( (lfrCurrentMode == LFR_MODE_NORMAL)
144 144 || (lfrCurrentMode == LFR_MODE_SBM1) || (lfrCurrentMode == LFR_MODE_SBM2) )
145 145 {
146 msgForMATR.event = msgForMATR.event | RTEMS_EVENT_NORM_BP1_F0;
146 msgForPRC.event = msgForPRC.event | RTEMS_EVENT_NORM_BP1_F0;
147 147 }
148 148 }
149 149
@@ -153,7 +153,7 rtems_task avf0_task( rtems_task_argumen
153 153 if ( (lfrCurrentMode == LFR_MODE_NORMAL)
154 154 || (lfrCurrentMode == LFR_MODE_SBM1) || (lfrCurrentMode == LFR_MODE_SBM2) )
155 155 {
156 msgForMATR.event = msgForMATR.event | RTEMS_EVENT_NORM_BP2_F0;
156 msgForPRC.event = msgForPRC.event | RTEMS_EVENT_NORM_BP2_F0;
157 157 }
158 158 }
159 159
@@ -163,19 +163,19 rtems_task avf0_task( rtems_task_argumen
163 163 if ( (lfrCurrentMode == LFR_MODE_NORMAL)
164 164 || (lfrCurrentMode == LFR_MODE_SBM1) || (lfrCurrentMode == LFR_MODE_SBM2) )
165 165 {
166 msgForMATR.event = msgForMATR.event | RTEMS_EVENT_NORM_ASM_F0;
166 msgForPRC.event = msgForPRC.event | RTEMS_EVENT_NORM_ASM_F0;
167 167 }
168 168 }
169 169
170 170 //*************************
171 // send the message to MATR
172 if (msgForMATR.event != 0x00)
171 // send the message to PRC
172 if (msgForPRC.event != 0x00)
173 173 {
174 status = rtems_message_queue_send( queue_id_prc0, (char *) &msgForMATR, MSG_QUEUE_SIZE_PRC0);
174 status = rtems_message_queue_send( queue_id_prc0, (char *) &msgForPRC, MSG_QUEUE_SIZE_PRC0);
175 175 }
176 176
177 177 if (status != RTEMS_SUCCESSFUL) {
178 PRINTF1("in AVF0 *** Error sending message to MATR, code %d\n", status)
178 PRINTF1("in AVF0 *** Error sending message to PRC, code %d\n", status)
179 179 }
180 180 }
181 181 }
@@ -42,7 +42,7 rtems_task avf1_task( rtems_task_argumen
42 42 rtems_event_set event_out;
43 43 rtems_status_code status;
44 44 rtems_id queue_id_prc1;
45 asm_msg msgForMATR;
45 asm_msg msgForPRC;
46 46 ring_node *nodeForAveraging;
47 47 ring_node *ring_node_tab[NB_SM_BEFORE_AVF0];
48 48 ring_node_asm *current_ring_node_asm_burst_sbm_f1;
@@ -79,9 +79,9 rtems_task avf1_task( rtems_task_argumen
79 79
80 80 //****************************************
81 81 // initialize the mesage for the MATR task
82 msgForMATR.norm = current_ring_node_asm_norm_f1;
83 msgForMATR.burst_sbm = current_ring_node_asm_burst_sbm_f1;
84 msgForMATR.event = 0x00; // this composite event will be sent to the PRC1 task
82 msgForPRC.norm = current_ring_node_asm_norm_f1;
83 msgForPRC.burst_sbm = current_ring_node_asm_burst_sbm_f1;
84 msgForPRC.event = 0x00; // this composite event will be sent to the PRC1 task
85 85 //
86 86 //****************************************
87 87
@@ -99,7 +99,7 rtems_task avf1_task( rtems_task_argumen
99 99 current_ring_node_asm_burst_sbm_f1->matrix,
100 100 ring_node_tab,
101 101 nb_norm_bp1, nb_sbm_bp1,
102 &msgForMATR );
102 &msgForPRC );
103 103
104 104 // update nb_average
105 105 nb_norm_bp1 = nb_norm_bp1 + NB_SM_BEFORE_AVF1;
@@ -115,11 +115,11 rtems_task avf1_task( rtems_task_argumen
115 115 current_ring_node_asm_burst_sbm_f1 = current_ring_node_asm_burst_sbm_f1->next;
116 116 if ( lfrCurrentMode == LFR_MODE_BURST )
117 117 {
118 msgForMATR.event = msgForMATR.event | RTEMS_EVENT_BURST_BP1_F1;
118 msgForPRC.event = msgForPRC.event | RTEMS_EVENT_BURST_BP1_F1;
119 119 }
120 120 else if ( lfrCurrentMode == LFR_MODE_SBM2 )
121 121 {
122 msgForMATR.event = msgForMATR.event | RTEMS_EVENT_SBM_BP1_F1;
122 msgForPRC.event = msgForPRC.event | RTEMS_EVENT_SBM_BP1_F1;
123 123 }
124 124 }
125 125
@@ -128,11 +128,11 rtems_task avf1_task( rtems_task_argumen
128 128 nb_sbm_bp2 = 0;
129 129 if ( lfrCurrentMode == LFR_MODE_BURST )
130 130 {
131 msgForMATR.event = msgForMATR.event | RTEMS_EVENT_BURST_BP2_F1;
131 msgForPRC.event = msgForPRC.event | RTEMS_EVENT_BURST_BP2_F1;
132 132 }
133 133 else if ( lfrCurrentMode == LFR_MODE_SBM2 )
134 134 {
135 msgForMATR.event = msgForMATR.event | RTEMS_EVENT_SBM_BP2_F1;
135 msgForPRC.event = msgForPRC.event | RTEMS_EVENT_SBM_BP2_F1;
136 136 }
137 137 }
138 138
@@ -144,7 +144,7 rtems_task avf1_task( rtems_task_argumen
144 144 if ( (lfrCurrentMode == LFR_MODE_NORMAL)
145 145 || (lfrCurrentMode == LFR_MODE_SBM1) || (lfrCurrentMode == LFR_MODE_SBM2) )
146 146 {
147 msgForMATR.event = msgForMATR.event | RTEMS_EVENT_NORM_BP1_F1;
147 msgForPRC.event = msgForPRC.event | RTEMS_EVENT_NORM_BP1_F1;
148 148 }
149 149 }
150 150
@@ -154,7 +154,7 rtems_task avf1_task( rtems_task_argumen
154 154 if ( (lfrCurrentMode == LFR_MODE_NORMAL)
155 155 || (lfrCurrentMode == LFR_MODE_SBM1) || (lfrCurrentMode == LFR_MODE_SBM2) )
156 156 {
157 msgForMATR.event = msgForMATR.event | RTEMS_EVENT_NORM_BP2_F1;
157 msgForPRC.event = msgForPRC.event | RTEMS_EVENT_NORM_BP2_F1;
158 158 }
159 159 }
160 160
@@ -164,15 +164,15 rtems_task avf1_task( rtems_task_argumen
164 164 if ( (lfrCurrentMode == LFR_MODE_NORMAL)
165 165 || (lfrCurrentMode == LFR_MODE_SBM1) || (lfrCurrentMode == LFR_MODE_SBM2) )
166 166 {
167 msgForMATR.event = msgForMATR.event | RTEMS_EVENT_NORM_ASM_F1;
167 msgForPRC.event = msgForPRC.event | RTEMS_EVENT_NORM_ASM_F1;
168 168 }
169 169 }
170 170
171 171 //*************************
172 // send the message to MATR
173 if (msgForMATR.event != 0x00)
172 // send the message to PRC
173 if (msgForPRC.event != 0x00)
174 174 {
175 status = rtems_message_queue_send( queue_id_prc1, (char *) &msgForMATR, MSG_QUEUE_SIZE_PRC1);
175 status = rtems_message_queue_send( queue_id_prc1, (char *) &msgForPRC, MSG_QUEUE_SIZE_PRC1);
176 176 }
177 177
178 178 if (status != RTEMS_SUCCESSFUL) {
@@ -38,7 +38,7 rtems_task avf2_task( rtems_task_argumen
38 38 rtems_event_set event_out;
39 39 rtems_status_code status;
40 40 rtems_id queue_id_prc2;
41 asm_msg msgForMATR;
41 asm_msg msgForPRC;
42 42 ring_node *nodeForAveraging;
43 43 ring_node_asm *current_ring_node_asm_norm_f2;
44 44
@@ -67,9 +67,9 rtems_task avf2_task( rtems_task_argumen
67 67
68 68 //****************************************
69 69 // initialize the mesage for the MATR task
70 msgForMATR.norm = current_ring_node_asm_norm_f2;
71 msgForMATR.burst_sbm = NULL;
72 msgForMATR.event = 0x00; // this composite event will be sent to the PRC2 task
70 msgForPRC.norm = current_ring_node_asm_norm_f2;
71 msgForPRC.burst_sbm = NULL;
72 msgForPRC.event = 0x00; // this composite event will be sent to the PRC2 task
73 73 //
74 74 //****************************************
75 75
@@ -79,7 +79,7 rtems_task avf2_task( rtems_task_argumen
79 79 SM_average_f2( current_ring_node_asm_norm_f2->matrix,
80 80 nodeForAveraging,
81 81 nb_norm_bp1,
82 &msgForMATR );
82 &msgForPRC );
83 83
84 84 // update nb_average
85 85 nb_norm_bp1 = nb_norm_bp1 + NB_SM_BEFORE_AVF2;
@@ -94,7 +94,7 rtems_task avf2_task( rtems_task_argumen
94 94 if ( (lfrCurrentMode == LFR_MODE_NORMAL) || (lfrCurrentMode == LFR_MODE_SBM1)
95 95 || (lfrCurrentMode == LFR_MODE_SBM2) )
96 96 {
97 msgForMATR.event = msgForMATR.event | RTEMS_EVENT_NORM_BP1_F2;
97 msgForPRC.event = msgForPRC.event | RTEMS_EVENT_NORM_BP1_F2;
98 98 }
99 99 }
100 100
@@ -104,7 +104,7 rtems_task avf2_task( rtems_task_argumen
104 104 if ( (lfrCurrentMode == LFR_MODE_NORMAL) || (lfrCurrentMode == LFR_MODE_SBM1)
105 105 || (lfrCurrentMode == LFR_MODE_SBM2) )
106 106 {
107 msgForMATR.event = msgForMATR.event | RTEMS_EVENT_NORM_BP2_F2;
107 msgForPRC.event = msgForPRC.event | RTEMS_EVENT_NORM_BP2_F2;
108 108 }
109 109 }
110 110
@@ -114,19 +114,19 rtems_task avf2_task( rtems_task_argumen
114 114 if ( (lfrCurrentMode == LFR_MODE_NORMAL) || (lfrCurrentMode == LFR_MODE_SBM1)
115 115 || (lfrCurrentMode == LFR_MODE_SBM2) )
116 116 {
117 msgForMATR.event = msgForMATR.event | RTEMS_EVENT_NORM_ASM_F2;
117 msgForPRC.event = msgForPRC.event | RTEMS_EVENT_NORM_ASM_F2;
118 118 }
119 119 }
120 120
121 121 //*************************
122 // send the message to MATR
123 if (msgForMATR.event != 0x00)
122 // send the message to PRC2
123 if (msgForPRC.event != 0x00)
124 124 {
125 status = rtems_message_queue_send( queue_id_prc2, (char *) &msgForMATR, MSG_QUEUE_SIZE_PRC2);
125 status = rtems_message_queue_send( queue_id_prc2, (char *) &msgForPRC, MSG_QUEUE_SIZE_PRC2);
126 126 }
127 127
128 128 if (status != RTEMS_SUCCESSFUL) {
129 PRINTF1("in AVF2 *** Error sending message to MATR, code %d\n", status)
129 PRINTF1("in AVF2 *** Error sending message to PRC2, code %d\n", status)
130 130 }
131 131 }
132 132 }
@@ -16,6 +16,13 unsigned int nb_sm_f0_aux_f1;
16 16 unsigned int nb_sm_f1;
17 17 unsigned int nb_sm_f0_aux_f2;
18 18
19 typedef enum restartState_t
20 {
21 WAIT_FOR_F2,
22 WAIT_FOR_F1,
23 WAIT_FOR_F0
24 } restartState;
25
19 26 //************************
20 27 // spectral matrices rings
21 28 ring_node sm_ring_f0[ NB_RING_NODES_SM_F0 ];
@@ -118,7 +125,7 void spectral_matrices_isr_f1( unsigned
118 125 unsigned char status;
119 126 ring_node *full_ring_node;
120 127
121 status = (statusReg & 0x0c) >> 2; // [1100] get the status_ready_matrix_f0_x bits
128 status = (statusReg & 0x0c) >> 2; // [1100] get the status_ready_matrix_f1_x bits
122 129
123 130 switch(status)
124 131 {
@@ -175,7 +182,7 void spectral_matrices_isr_f2( unsigned
175 182 unsigned char status;
176 183 rtems_status_code status_code;
177 184
178 status = (statusReg & 0x30) >> 4; // [0011 0000] get the status_ready_matrix_f0_x bits
185 status = (statusReg & 0x30) >> 4; // [0011 0000] get the status_ready_matrix_f2_x bits
179 186
180 187 switch(status)
181 188 {
@@ -235,15 +242,48 rtems_isr spectral_matrices_isr( rtems_v
235 242
236 243 unsigned char statusReg;
237 244
245 static restartState state = WAIT_FOR_F2;
246
238 247 statusReg = spectral_matrix_regs->status;
239 248
249 if (thisIsAnASMRestart == 0)
250 { // this is not a restart sequence, process incoming matrices normally
240 251 spectral_matrices_isr_f0( statusReg );
241 252
242 253 spectral_matrices_isr_f1( statusReg );
243 254
244 255 spectral_matrices_isr_f2( statusReg );
256 }
257 else
258 { // a restart sequence has to be launched
259 switch (state) {
260 case WAIT_FOR_F2:
261 if ((statusReg & 0x30) != 0x00) // [0011 0000] check the status_ready_matrix_f2_x bits
262 {
263 state = WAIT_FOR_F1;
264 }
265 break;
266 case WAIT_FOR_F1:
267 if ((statusReg & 0x0c) != 0x00) // [0000 1100] check the status_ready_matrix_f1_x bits
268 {
269 state = WAIT_FOR_F0;
270 }
271 break;
272 case WAIT_FOR_F0:
273 if ((statusReg & 0x03) != 0x00) // [0000 0011] check the status_ready_matrix_f0_x bits
274 {
275 state = WAIT_FOR_F2;
276 thisIsAnASMRestart = 0;
277 }
278 break;
279 default:
280 break;
281 }
282 reset_sm_status();
283 }
245 284
246 285 spectral_matrix_isr_error_handler( statusReg );
286
247 287 }
248 288
249 289 //******************
@@ -403,7 +443,7 void BP_send_s1_s2(char *data, rtems_id
403 443
404 444 // SEND PACKET
405 445 // before lastValidTransitionDate, the data are drops even if they are ready
406 // this guarantees that no SBM packets will be received before the requestion enter mode time
446 // this guarantees that no SBM packets will be received before the requested enter mode time
407 447 if ( time_management_regs->coarse_time >= lastValidEnterModeTime)
408 448 {
409 449 status = rtems_message_queue_send( queue_id, data, nbBytesToSend);
@@ -228,12 +228,12 int action_enter_mode(ccsdsTelecommandPa
228 228 default:
229 229 break;
230 230 }
231 }
232 231
233 232 if (status != RTEMS_SUCCESSFUL)
234 233 {
235 234 status = LFR_EXE_ERROR;
236 235 }
236 }
237 237
238 238 return status;
239 239 }
@@ -507,6 +507,8 int restart_asm_activities( unsigned cha
507 507
508 508 status = stop_spectral_matrices();
509 509
510 thisIsAnASMRestart = 1;
511
510 512 status = restart_asm_tasks( lfrRequestedMode );
511 513
512 514 launch_spectral_matrix();
@@ -530,7 +532,7 int stop_spectral_matrices( void )
530 532 status = RTEMS_SUCCESSFUL;
531 533
532 534 // (1) mask interruptions
533 LEON_Mask_interrupt( IRQ_SPECTRAL_MATRIX ); // clear spectral matrix interrupt
535 LEON_Mask_interrupt( IRQ_SPECTRAL_MATRIX ); // mask spectral matrix interrupt
534 536
535 537 // (2) reset spectral matrices registers
536 538 set_sm_irq_onNewMatrix( 0 ); // stop the spectral matrices
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