##// END OF EJS Templates
ASM restart sequence updated at the interrupt service routine level...
paul -
r259:af93852650f9 R3a
parent child
Show More
@@ -1,2 +1,2
1 3081d1f9bb20b2b64a192585337a292a9804e0c5 LFR_basic-parameters
1 3081d1f9bb20b2b64a192585337a292a9804e0c5 LFR_basic-parameters
2 4ffa7549495b4d1e5ddbda520569468a5e3b8779 header/lfr_common_headers
2 ad7698268954c5d3d203a3b3ad09fcdf2d536472 header/lfr_common_headers
@@ -1,192 +1,221
1 #ifndef GSCMEMORY_HPP_
1 #ifndef GSCMEMORY_HPP_
2 #define GSCMEMORY_HPP_
2 #define GSCMEMORY_HPP_
3
3
4 #ifndef LEON3
4 #ifndef LEON3
5 #define LEON3
5 #define LEON3
6 #endif
6 #endif
7
7
8 #define REGS_ADDR_PLUGANDPLAY 0xFFFFF000
8 #define REGS_ADDR_PLUGANDPLAY 0xFFFFF000
9 #define ASR16_REG_ADDRESS 0x90400040 // Ancillary State Register 16 = Register protection control register (FT only)
9 #define ASR16_REG_ADDRESS 0x90400040 // Ancillary State Register 16 = Register protection control register (FT only)
10
10
11 #define DEVICEID_LEON3 0x003
11 #define DEVICEID_LEON3 0x003
12 #define DEVICEID_LEON3FT 0x053
12 #define DEVICEID_LEON3FT 0x053
13 #define VENDORID_GAISLER 0x01
13 #define VENDORID_GAISLER 0x01
14
14
15 // CCR
15 // CCR
16 #define POS_FT 19
17 //
16 #define POS_ITE 12
18 #define POS_ITE 12
17 #define COUNTER_FIELD_ITE 0x00003000 // 0000 0000 0000 0000 0011 0000 0000 0000
19 #define COUNTER_FIELD_ITE 0x00003000 // 0000 0000 0000 0000 0011 0000 0000 0000
18 #define COUNTER_MASK_ITE 0xffffcfff // 1111 1111 1111 1111 1100 1111 1111 1111
20 #define COUNTER_MASK_ITE 0xffffcfff // 1111 1111 1111 1111 1100 1111 1111 1111
19 #define POS_IDE 10
21 #define POS_IDE 10
20 #define COUNTER_FIELD_IDE 0x00000c00 // 0000 0000 0000 0000 0000 1100 0000 0000
22 #define COUNTER_FIELD_IDE 0x00000c00 // 0000 0000 0000 0000 0000 1100 0000 0000
21 #define COUNTER_MASK_IDE 0xfffff3ff // 1111 1111 1111 1111 1111 0011 1111 1111
23 #define COUNTER_MASK_IDE 0xfffff3ff // 1111 1111 1111 1111 1111 0011 1111 1111
22 //
24 //
23 #define POS_DTE 8
25 #define POS_DTE 8
24 #define COUNTER_FIELD_DTE 0x00000300 // 0000 0000 0000 0000 0000 0011 0000 0000
26 #define COUNTER_FIELD_DTE 0x00000300 // 0000 0000 0000 0000 0000 0011 0000 0000
25 #define COUNTER_MASK_DTE 0xfffffcff // 1111 1111 1111 1111 1111 1100 1111 1111
27 #define COUNTER_MASK_DTE 0xfffffcff // 1111 1111 1111 1111 1111 1100 1111 1111
26 #define POS_DDE 6
28 #define POS_DDE 6
27 #define COUNTER_FIELD_DDE 0x000000c0 // 0000 0000 0000 0000 0000 0000 1100 0000
29 #define COUNTER_FIELD_DDE 0x000000c0 // 0000 0000 0000 0000 0000 0000 1100 0000
28 #define COUNTER_MASK_DDE 0xffffff3f // 1111 1111 1111 1111 1111 1111 0011 1111
30 #define COUNTER_MASK_DDE 0xffffff3f // 1111 1111 1111 1111 1111 1111 0011 1111
29
31
30 // ASR16
32 // ASR16
33 #define POS_FPFTID 30
31 #define POS_FPRF 27
34 #define POS_FPRF 27
35 #define POS_FDI 16 // FP RF protection enable/disable
36 #define POS_IUFTID 14
37 #define POS_IURF 11
38 #define POS_IDI 0 // IU RF protection enable/disable
39
32 #define COUNTER_FIELD_FPRF 0x38000000 // 0011 1000 0000 0000 0000 0000 0000 0000
40 #define COUNTER_FIELD_FPRF 0x38000000 // 0011 1000 0000 0000 0000 0000 0000 0000
33 #define COUNTER_MASK_FPRF 0xc7ffffff // 1100 0111 1111 1111 1111 1111 1111 1111
41 #define COUNTER_MASK_FPRF 0xc7ffffff // 1100 0111 1111 1111 1111 1111 1111 1111
34 #define POS_IURF 11
42
35 #define COUNTER_FIELD_IURF 0x00003800 // 0000 0000 0000 0000 0011 1000 0000 0000
43 #define COUNTER_FIELD_IURF 0x00003800 // 0000 0000 0000 0000 0011 1000 0000 0000
36 #define COUNTER_MASK_IURF 0xffffc7ff // 1111 1111 1111 1111 1100 0111 1111 1111
44 #define COUNTER_MASK_IURF 0xffffc7ff // 1111 1111 1111 1111 1100 0111 1111 1111
37
45
38 volatile unsigned int *asr16Ptr = (volatile unsigned int *) ASR16_REG_ADDRESS;
46 volatile unsigned int *asr16Ptr = (volatile unsigned int *) ASR16_REG_ADDRESS;
39
47
40 static inline void flushCache()
48 static inline void flushCache()
41 {
49 {
42 /**
50 /**
43 * Flush the data cache and the instruction cache.
51 * Flush the data cache and the instruction cache.
44 *
52 *
45 * @param void
53 * @param void
46 *
54 *
47 * @return void
55 * @return void
48 */
56 */
49
57
50 asm("flush");
58 asm("flush");
51 }
59 }
52
60
53 //***************************
61 //***************************
54 // CCR Cache control register
62 // CCR Cache control register
55
63
56 static unsigned int CCR_getValue()
64 static unsigned int CCR_getValue()
57 {
65 {
58 unsigned int cacheControlRegister = 0;
66 unsigned int cacheControlRegister = 0;
59 __asm__ __volatile__("lda [%%g0] 2, %0" : "=r"(cacheControlRegister) : );
67 __asm__ __volatile__("lda [%%g0] 2, %0" : "=r"(cacheControlRegister) : );
60 return cacheControlRegister;
68 return cacheControlRegister;
61 }
69 }
62
70
63 static void CCR_setValue(unsigned int cacheControlRegister)
71 static void CCR_setValue(unsigned int cacheControlRegister)
64 {
72 {
65 __asm__ __volatile__("sta %0, [%%g0] 2" : : "r"(cacheControlRegister));
73 __asm__ __volatile__("sta %0, [%%g0] 2" : : "r"(cacheControlRegister));
66 }
74 }
67
75
68 static void CCR_resetCacheControlRegister()
76 static void CCR_resetCacheControlRegister()
69 {
77 {
70 unsigned int cacheControlRegister;
78 unsigned int cacheControlRegister;
71 cacheControlRegister = 0x00;
79 cacheControlRegister = 0x00;
72 CCR_setValue(cacheControlRegister);
80 CCR_setValue(cacheControlRegister);
73 }
81 }
74
82
75 static void CCR_enableInstructionCache()
83 static void CCR_enableInstructionCache()
76 {
84 {
77 // [1:0] Instruction Cache state (ICS)
85 // [1:0] Instruction Cache state (ICS)
78 // Indicates the current data cache state according to the following: X0 = disabled, 01 = frozen, 11 = enabled.
86 // Indicates the current data cache state according to the following: X0 = disabled, 01 = frozen, 11 = enabled.
79 unsigned int cacheControlRegister;
87 unsigned int cacheControlRegister;
80 cacheControlRegister = CCR_getValue();
88 cacheControlRegister = CCR_getValue();
81 cacheControlRegister = (cacheControlRegister | 0x3);
89 cacheControlRegister = (cacheControlRegister | 0x3);
82 CCR_setValue(cacheControlRegister);
90 CCR_setValue(cacheControlRegister);
83 }
91 }
84
92
85 static void CCR_enableDataCache()
93 static void CCR_enableDataCache()
86 {
94 {
87 // [3:2] Data Cache state (DCS)
95 // [3:2] Data Cache state (DCS)
88 // Indicates the current data cache state according to the following: X0 = disabled, 01 = frozen, 11 = enabled.
96 // Indicates the current data cache state according to the following: X0 = disabled, 01 = frozen, 11 = enabled.
89 unsigned int cacheControlRegister;
97 unsigned int cacheControlRegister;
90 cacheControlRegister = CCR_getValue();
98 cacheControlRegister = CCR_getValue();
91 cacheControlRegister = (cacheControlRegister | 0xc);
99 cacheControlRegister = (cacheControlRegister | 0xc);
92 CCR_setValue(cacheControlRegister);
100 CCR_setValue(cacheControlRegister);
93 }
101 }
94
102
95 static void CCR_faultTolerantScheme()
96 {
97 // [20:19] FT scheme (FT) - “00” = no FT, “01” = 4-bit checking implemented
98 unsigned int cacheControlRegister;
99 unsigned int *plugAndPlayRegister;
100 unsigned int vendorId;
101 unsigned int deviceId;
102
103 plugAndPlayRegister = (unsigned int*) REGS_ADDR_PLUGANDPLAY;
104 vendorId = ( (*plugAndPlayRegister) & 0xff000000 ) >> 24;
105 deviceId = ( (*plugAndPlayRegister) & 0x00fff000 ) >> 12;
106
107 if( (vendorId == VENDORID_GAISLER) & (deviceId ==DEVICEID_LEON3FT) )
108 {
109 PRINTF("in faultTolerantScheme *** Leon3FT detected, configure the CCR FT bits\n");
110 cacheControlRegister = CCR_getValue();
111 cacheControlRegister = (cacheControlRegister | 0xc);
112 CCR_setValue(cacheControlRegister);
113 }
114 else
115 {
116 PRINTF("in faultTolerantScheme *** not a Leon3FT, no need to configure the CCR FT bits\n");
117 PRINTF2(" *** vendorID = 0x%x, deviceId = 0x%x\n", vendorId, deviceId);
118 }
119 }
120
121 static void CCR_enableInstructionBurstFetch()
103 static void CCR_enableInstructionBurstFetch()
122 {
104 {
123 // [16] Instruction burst fetch (IB). This bit enables burst fill during instruction fetch.
105 // [16] Instruction burst fetch (IB). This bit enables burst fill during instruction fetch.
124 unsigned int cacheControlRegister;
106 unsigned int cacheControlRegister;
125 cacheControlRegister = CCR_getValue();
107 cacheControlRegister = CCR_getValue();
126 // set the bit IB to 1
108 // set the bit IB to 1
127 cacheControlRegister = (cacheControlRegister | 0x10000);
109 cacheControlRegister = (cacheControlRegister | 0x10000);
128 CCR_setValue(cacheControlRegister);
110 CCR_setValue(cacheControlRegister);
129 }
111 }
130
112
131 static void CCR_getInstructionAndDataErrorCounters( unsigned int* instructionErrorCounter, unsigned int* dataErrorCounter )
113 void CCR_getInstructionAndDataErrorCounters( unsigned int* instructionErrorCounter, unsigned int* dataErrorCounter )
132 {
114 {
133 // [13:12] Instruction Tag Errors (ITE) - Number of detected parity errors in the instruction tag cache.
115 // [13:12] Instruction Tag Errors (ITE) - Number of detected parity errors in the instruction tag cache.
134 // Only available if fault-tolerance is enabled (FT field in this register is non-zero).
116 // Only available if fault-tolerance is enabled (FT field in this register is non-zero).
135 // [11:10] Instruction Data Errors (IDE) - Number of detected parity errors in the instruction data cache.
117 // [11:10] Instruction Data Errors (IDE) - Number of detected parity errors in the instruction data cache.
136 // Only available if fault-tolerance is enabled (FT field in this register is non-zero).
118 // Only available if fault-tolerance is enabled (FT field in this register is non-zero).
137
119
138 unsigned int cacheControlRegister;
120 unsigned int cacheControlRegister;
139 unsigned int iTE;
121 unsigned int iTE;
140 unsigned int iDE;
122 unsigned int iDE;
141 unsigned int dTE;
123 unsigned int dTE;
142 unsigned int dDE;
124 unsigned int dDE;
143
125
144 cacheControlRegister = CCR_getValue();
126 cacheControlRegister = CCR_getValue();
145 iTE = (cacheControlRegister & COUNTER_FIELD_ITE) >> POS_ITE;
127 iTE = (cacheControlRegister & COUNTER_FIELD_ITE) >> POS_ITE;
146 iDE = (cacheControlRegister & COUNTER_FIELD_IDE) >> POS_IDE;
128 iDE = (cacheControlRegister & COUNTER_FIELD_IDE) >> POS_IDE;
147 dTE = (cacheControlRegister & COUNTER_FIELD_DTE) >> POS_DTE;
129 dTE = (cacheControlRegister & COUNTER_FIELD_DTE) >> POS_DTE;
148 dDE = (cacheControlRegister & COUNTER_FIELD_DDE) >> POS_DDE;
130 dDE = (cacheControlRegister & COUNTER_FIELD_DDE) >> POS_DDE;
149
131
150 *instructionErrorCounter = iTE + iDE;
132 *instructionErrorCounter = iTE + iDE;
151 *dataErrorCounter = dTE + dDE;
133 *dataErrorCounter = dTE + dDE;
152
134
153 // reset counters
135 // reset counters
154 cacheControlRegister = cacheControlRegister
136 cacheControlRegister = cacheControlRegister
155 & COUNTER_FIELD_ITE
137 & COUNTER_FIELD_ITE
156 & COUNTER_FIELD_IDE
138 & COUNTER_FIELD_IDE
157 & COUNTER_FIELD_DTE
139 & COUNTER_FIELD_DTE
158 & COUNTER_FIELD_DDE;
140 & COUNTER_FIELD_DDE;
159
141
160 CCR_setValue(cacheControlRegister);
142 CCR_setValue(cacheControlRegister);
161 }
143 }
162
144
163 //*******************************************
145 //*******************************************
164 // ASR16 Register protection control register
146 // ASR16 Register protection control register
165
147
166 static void ASR16_get_FPRF_IURF_ErrorCounters( unsigned int* fprfErrorCounter, unsigned int* iurfErrorCounter)
148 static void ASR16_resetRegisterProtectionControlRegister()
149 {
150 *asr16Ptr = 0x00;
151 }
152
153 void ASR16_get_FPRF_IURF_ErrorCounters( unsigned int* fprfErrorCounter, unsigned int* iurfErrorCounter)
167 {
154 {
168 /** This function is used to retrieve the integer unit register file error counter and the floating point unit
155 /** This function is used to retrieve the integer unit register file error counter and the floating point unit
169 * register file error counter
156 * register file error counter
170 *
157 *
171 * @return void
158 * @return void
172 *
159 *
173 * [29:27] FP RF error counter - Number of detected parity errors in the FP register file.
160 * [29:27] FP RF error counter - Number of detected parity errors in the FP register file.
174 * [13:11] IU RF error counter - Number of detected parity errors in the IU register file.
161 * [13:11] IU RF error counter - Number of detected parity errors in the IU register file.
175 *
162 *
176 */
163 */
177
164
178 unsigned int asr16;
165 unsigned int asr16;
179
166
180 asr16 = *asr16Ptr;
167 asr16 = *asr16Ptr;
181 *fprfErrorCounter = ( asr16 & COUNTER_FIELD_FPRF ) >> POS_FPRF;
168 *fprfErrorCounter = ( asr16 & COUNTER_FIELD_FPRF ) >> POS_FPRF;
182 *iurfErrorCounter = ( asr16 & COUNTER_FIELD_IURF ) >> POS_IURF;
169 *iurfErrorCounter = ( asr16 & COUNTER_FIELD_IURF ) >> POS_IURF;
183
170
184 // reset the counter to 0
171 // reset the counter to 0
185 asr16 = asr16
172 asr16 = asr16
186 & COUNTER_MASK_FPRF
173 & COUNTER_MASK_FPRF
187 & COUNTER_FIELD_IURF;
174 & COUNTER_FIELD_IURF;
188
175
189 *asr16Ptr = asr16;
176 *asr16Ptr = asr16;
190 }
177 }
191
178
179 static void faultTolerantScheme()
180 {
181 // [20:19] FT scheme (FT) - “00” = no FT, “01” = 4-bit checking implemented
182 unsigned int cacheControlRegister;
183 unsigned int *plugAndPlayRegister;
184 unsigned int vendorId;
185 unsigned int deviceId;
186
187 plugAndPlayRegister = (unsigned int*) REGS_ADDR_PLUGANDPLAY;
188 vendorId = ( (*plugAndPlayRegister) & 0xff000000 ) >> 24;
189 deviceId = ( (*plugAndPlayRegister) & 0x00fff000 ) >> 12;
190
191 cacheControlRegister = CCR_getValue();
192
193 if( (vendorId == VENDORID_GAISLER) & (deviceId ==DEVICEID_LEON3FT) )
194 {
195 PRINTF("in faultTolerantScheme *** Leon3FT detected\n");
196 PRINTF2(" *** vendorID = 0x%x, deviceId = 0x%x\n", vendorId, deviceId);
197 PRINTF1("ASR16 IU RF protection, bit 0 (IDI) is: 0x%x (0 => protection enabled)\n",
198 (*asr16Ptr >> POS_IDI) & 1);
199 PRINTF1("ASR16 FP RF protection, bit 16 (FDI) is: 0x%x (0 => protection enabled)\n",
200 (*asr16Ptr >> POS_FDI) & 1);
201 PRINTF1("ASR16 IU FT ID bits [15:14] is: 0x%x (2 => 8-bit parity without restart)\n",
202 (*asr16Ptr >> POS_IUFTID) & 0x3);
203 PRINTF1("ASR16 FP FT ID bits [31:30] is: 0x%x (1 => 4-bit parity with restart)\n",
204 (*asr16Ptr >> POS_FPFTID) & 0x03);
205 PRINTF1("CCR FT bits [20:19] are: 0x%x (1 => 4-bit parity with restart)\n",
206 (cacheControlRegister >> POS_FT) & 0x3 );
207
208 // CCR The FFT bits are just read, the FT scheme is set to “01” = 4-bit checking implemented by default
209
210 // ASR16 Ancillary State Register configuration (Register protection control register)
211 // IU RF protection is set by default, bit 0 IDI = 0
212 // FP RF protection is set by default, bit 16 FDI = 0
213 }
214 else
215 {
216 PRINTF("in faultTolerantScheme *** not a Leon3FT not detected\n");
217 PRINTF2(" *** vendorID = 0x%x, deviceId = 0x%x\n", vendorId, deviceId);
218 }
219 }
220
192 #endif /* GSCMEMORY_HPP_ */
221 #endif /* GSCMEMORY_HPP_ */
@@ -1,79 +1,82
1 #ifndef FSW_MISC_H_INCLUDED
1 #ifndef FSW_MISC_H_INCLUDED
2 #define FSW_MISC_H_INCLUDED
2 #define FSW_MISC_H_INCLUDED
3
3
4 #include <rtems.h>
4 #include <rtems.h>
5 #include <stdio.h>
5 #include <stdio.h>
6 #include <grspw.h>
6 #include <grspw.h>
7 #include <grlib_regs.h>
7 #include <grlib_regs.h>
8
8
9 #include "fsw_params.h"
9 #include "fsw_params.h"
10 #include "fsw_spacewire.h"
10 #include "fsw_spacewire.h"
11 #include "lfr_cpu_usage_report.h"
11 #include "lfr_cpu_usage_report.h"
12
12
13
13 enum lfr_reset_cause_t{
14 enum lfr_reset_cause_t{
14 UNKNOWN_CAUSE,
15 UNKNOWN_CAUSE,
15 POWER_ON,
16 POWER_ON,
16 TC_RESET,
17 TC_RESET,
17 WATCHDOG,
18 WATCHDOG,
18 ERROR_RESET,
19 ERROR_RESET,
19 UNEXP_RESET
20 UNEXP_RESET
20 };
21 };
21
22
22 extern gptimer_regs_t *gptimer_regs;
23 extern gptimer_regs_t *gptimer_regs;
24 extern void ASR16_get_FPRF_IURF_ErrorCounters( unsigned int*, unsigned int* );
25 extern void CCR_getInstructionAndDataErrorCounters( unsigned int*, unsigned int* );
23
26
24 #define LFR_RESET_CAUSE_UNKNOWN_CAUSE 0
27 #define LFR_RESET_CAUSE_UNKNOWN_CAUSE 0
25
28
26 rtems_name name_hk_rate_monotonic; // name of the HK rate monotonic
29 rtems_name name_hk_rate_monotonic; // name of the HK rate monotonic
27 rtems_id HK_id; // id of the HK rate monotonic period
30 rtems_id HK_id; // id of the HK rate monotonic period
28
31
29 void timer_configure( unsigned char timer, unsigned int clock_divider,
32 void timer_configure( unsigned char timer, unsigned int clock_divider,
30 unsigned char interrupt_level, rtems_isr (*timer_isr)() );
33 unsigned char interrupt_level, rtems_isr (*timer_isr)() );
31 void timer_start( unsigned char timer );
34 void timer_start( unsigned char timer );
32 void timer_stop( unsigned char timer );
35 void timer_stop( unsigned char timer );
33 void timer_set_clock_divider(unsigned char timer, unsigned int clock_divider);
36 void timer_set_clock_divider(unsigned char timer, unsigned int clock_divider);
34
37
35 // WATCHDOG
38 // WATCHDOG
36 rtems_isr watchdog_isr( rtems_vector_number vector );
39 rtems_isr watchdog_isr( rtems_vector_number vector );
37 void watchdog_configure(void);
40 void watchdog_configure(void);
38 void watchdog_stop(void);
41 void watchdog_stop(void);
39 void watchdog_start(void);
42 void watchdog_start(void);
40
43
41 // SERIAL LINK
44 // SERIAL LINK
42 int send_console_outputs_on_apbuart_port( void );
45 int send_console_outputs_on_apbuart_port( void );
43 int enable_apbuart_transmitter( void );
46 int enable_apbuart_transmitter( void );
44 void set_apbuart_scaler_reload_register(unsigned int regs, unsigned int value);
47 void set_apbuart_scaler_reload_register(unsigned int regs, unsigned int value);
45
48
46 // RTEMS TASKS
49 // RTEMS TASKS
47 rtems_task load_task( rtems_task_argument argument );
50 rtems_task load_task( rtems_task_argument argument );
48 rtems_task hous_task( rtems_task_argument argument );
51 rtems_task hous_task( rtems_task_argument argument );
49 rtems_task dumb_task( rtems_task_argument unused );
52 rtems_task dumb_task( rtems_task_argument unused );
50
53
51 void init_housekeeping_parameters( void );
54 void init_housekeeping_parameters( void );
52 void increment_seq_counter(unsigned short *packetSequenceControl);
55 void increment_seq_counter(unsigned short *packetSequenceControl);
53 void getTime( unsigned char *time);
56 void getTime( unsigned char *time);
54 unsigned long long int getTimeAsUnsignedLongLongInt( );
57 unsigned long long int getTimeAsUnsignedLongLongInt( );
55 void send_dumb_hk( void );
58 void send_dumb_hk( void );
56 void get_temperatures( unsigned char *temperatures );
59 void get_temperatures( unsigned char *temperatures );
57 void get_v_e1_e2_f3( unsigned char *spacecraft_potential );
60 void get_v_e1_e2_f3( unsigned char *spacecraft_potential );
58 void get_cpu_load( unsigned char *resource_statistics );
61 void get_cpu_load( unsigned char *resource_statistics );
59 void set_hk_lfr_sc_potential_flag( bool state );
62 void set_hk_lfr_sc_potential_flag( bool state );
60 void set_hk_lfr_mag_fields_flag( bool state );
63 void set_hk_lfr_mag_fields_flag( bool state );
61 void set_hk_lfr_calib_enable( bool state );
64 void set_hk_lfr_calib_enable( bool state );
62 void set_hk_lfr_reset_cause( enum lfr_reset_cause_t lfr_reset_cause );
65 void set_hk_lfr_reset_cause( enum lfr_reset_cause_t lfr_reset_cause );
63 void hk_lfr_le_me_he_update();
66 void hk_lfr_le_me_he_update();
64 void set_hk_lfr_time_not_synchro();
67 void set_hk_lfr_time_not_synchro();
65
68
66 extern int sched_yield( void );
69 extern int sched_yield( void );
67 extern void rtems_cpu_usage_reset();
70 extern void rtems_cpu_usage_reset();
68 extern ring_node *current_ring_node_f3;
71 extern ring_node *current_ring_node_f3;
69 extern ring_node *ring_node_to_send_cwf_f3;
72 extern ring_node *ring_node_to_send_cwf_f3;
70 extern ring_node waveform_ring_f3[];
73 extern ring_node waveform_ring_f3[];
71 extern unsigned short sequenceCounterHK;
74 extern unsigned short sequenceCounterHK;
72
75
73 extern unsigned char hk_lfr_q_sd_fifo_size_max;
76 extern unsigned char hk_lfr_q_sd_fifo_size_max;
74 extern unsigned char hk_lfr_q_rv_fifo_size_max;
77 extern unsigned char hk_lfr_q_rv_fifo_size_max;
75 extern unsigned char hk_lfr_q_p0_fifo_size_max;
78 extern unsigned char hk_lfr_q_p0_fifo_size_max;
76 extern unsigned char hk_lfr_q_p1_fifo_size_max;
79 extern unsigned char hk_lfr_q_p1_fifo_size_max;
77 extern unsigned char hk_lfr_q_p2_fifo_size_max;
80 extern unsigned char hk_lfr_q_p2_fifo_size_max;
78
81
79 #endif // FSW_MISC_H_INCLUDED
82 #endif // FSW_MISC_H_INCLUDED
@@ -1,330 +1,332
1 #ifndef FSW_PROCESSING_H_INCLUDED
1 #ifndef FSW_PROCESSING_H_INCLUDED
2 #define FSW_PROCESSING_H_INCLUDED
2 #define FSW_PROCESSING_H_INCLUDED
3
3
4 #include <rtems.h>
4 #include <rtems.h>
5 #include <grspw.h>
5 #include <grspw.h>
6 #include <math.h>
6 #include <math.h>
7 #include <stdlib.h> // abs() is in the stdlib
7 #include <stdlib.h> // abs() is in the stdlib
8 #include <stdio.h>
8 #include <stdio.h>
9 #include <math.h>
9 #include <math.h>
10 #include <grlib_regs.h>
10 #include <grlib_regs.h>
11
11
12 #include "fsw_params.h"
12 #include "fsw_params.h"
13
13
14 typedef struct ring_node_asm
14 typedef struct ring_node_asm
15 {
15 {
16 struct ring_node_asm *next;
16 struct ring_node_asm *next;
17 float matrix[ TOTAL_SIZE_SM ];
17 float matrix[ TOTAL_SIZE_SM ];
18 unsigned int status;
18 unsigned int status;
19 } ring_node_asm;
19 } ring_node_asm;
20
20
21 typedef struct
21 typedef struct
22 {
22 {
23 unsigned char targetLogicalAddress;
23 unsigned char targetLogicalAddress;
24 unsigned char protocolIdentifier;
24 unsigned char protocolIdentifier;
25 unsigned char reserved;
25 unsigned char reserved;
26 unsigned char userApplication;
26 unsigned char userApplication;
27 unsigned char packetID[2];
27 unsigned char packetID[2];
28 unsigned char packetSequenceControl[2];
28 unsigned char packetSequenceControl[2];
29 unsigned char packetLength[2];
29 unsigned char packetLength[2];
30 // DATA FIELD HEADER
30 // DATA FIELD HEADER
31 unsigned char spare1_pusVersion_spare2;
31 unsigned char spare1_pusVersion_spare2;
32 unsigned char serviceType;
32 unsigned char serviceType;
33 unsigned char serviceSubType;
33 unsigned char serviceSubType;
34 unsigned char destinationID;
34 unsigned char destinationID;
35 unsigned char time[6];
35 unsigned char time[6];
36 // AUXILIARY HEADER
36 // AUXILIARY HEADER
37 unsigned char sid;
37 unsigned char sid;
38 unsigned char biaStatusInfo;
38 unsigned char biaStatusInfo;
39 unsigned char sy_lfr_common_parameters_spare;
39 unsigned char sy_lfr_common_parameters_spare;
40 unsigned char sy_lfr_common_parameters;
40 unsigned char sy_lfr_common_parameters;
41 unsigned char acquisitionTime[6];
41 unsigned char acquisitionTime[6];
42 unsigned char pa_lfr_bp_blk_nr[2];
42 unsigned char pa_lfr_bp_blk_nr[2];
43 // SOURCE DATA
43 // SOURCE DATA
44 unsigned char data[ 780 ]; // MAX size is 26 bins * 30 Bytes [TM_LFR_SCIENCE_BURST_BP2_F1]
44 unsigned char data[ 780 ]; // MAX size is 26 bins * 30 Bytes [TM_LFR_SCIENCE_BURST_BP2_F1]
45 } bp_packet;
45 } bp_packet;
46
46
47 typedef struct
47 typedef struct
48 {
48 {
49 unsigned char targetLogicalAddress;
49 unsigned char targetLogicalAddress;
50 unsigned char protocolIdentifier;
50 unsigned char protocolIdentifier;
51 unsigned char reserved;
51 unsigned char reserved;
52 unsigned char userApplication;
52 unsigned char userApplication;
53 unsigned char packetID[2];
53 unsigned char packetID[2];
54 unsigned char packetSequenceControl[2];
54 unsigned char packetSequenceControl[2];
55 unsigned char packetLength[2];
55 unsigned char packetLength[2];
56 // DATA FIELD HEADER
56 // DATA FIELD HEADER
57 unsigned char spare1_pusVersion_spare2;
57 unsigned char spare1_pusVersion_spare2;
58 unsigned char serviceType;
58 unsigned char serviceType;
59 unsigned char serviceSubType;
59 unsigned char serviceSubType;
60 unsigned char destinationID;
60 unsigned char destinationID;
61 unsigned char time[6];
61 unsigned char time[6];
62 // AUXILIARY HEADER
62 // AUXILIARY HEADER
63 unsigned char sid;
63 unsigned char sid;
64 unsigned char biaStatusInfo;
64 unsigned char biaStatusInfo;
65 unsigned char sy_lfr_common_parameters_spare;
65 unsigned char sy_lfr_common_parameters_spare;
66 unsigned char sy_lfr_common_parameters;
66 unsigned char sy_lfr_common_parameters;
67 unsigned char acquisitionTime[6];
67 unsigned char acquisitionTime[6];
68 unsigned char source_data_spare;
68 unsigned char source_data_spare;
69 unsigned char pa_lfr_bp_blk_nr[2];
69 unsigned char pa_lfr_bp_blk_nr[2];
70 // SOURCE DATA
70 // SOURCE DATA
71 unsigned char data[ 143 ]; // 13 bins * 11 Bytes
71 unsigned char data[ 143 ]; // 13 bins * 11 Bytes
72 } bp_packet_with_spare; // only for TM_LFR_SCIENCE_NORMAL_BP1_F0 and F1
72 } bp_packet_with_spare; // only for TM_LFR_SCIENCE_NORMAL_BP1_F0 and F1
73
73
74 typedef struct asm_msg
74 typedef struct asm_msg
75 {
75 {
76 ring_node_asm *norm;
76 ring_node_asm *norm;
77 ring_node_asm *burst_sbm;
77 ring_node_asm *burst_sbm;
78 rtems_event_set event;
78 rtems_event_set event;
79 unsigned int coarseTimeNORM;
79 unsigned int coarseTimeNORM;
80 unsigned int fineTimeNORM;
80 unsigned int fineTimeNORM;
81 unsigned int coarseTimeSBM;
81 unsigned int coarseTimeSBM;
82 unsigned int fineTimeSBM;
82 unsigned int fineTimeSBM;
83 } asm_msg;
83 } asm_msg;
84
84
85 extern unsigned char thisIsAnASMRestart;
86
85 extern volatile int sm_f0[ ];
87 extern volatile int sm_f0[ ];
86 extern volatile int sm_f1[ ];
88 extern volatile int sm_f1[ ];
87 extern volatile int sm_f2[ ];
89 extern volatile int sm_f2[ ];
88
90
89 // parameters
91 // parameters
90 extern struct param_local_str param_local;
92 extern struct param_local_str param_local;
91 extern Packet_TM_LFR_PARAMETER_DUMP_t parameter_dump_packet;
93 extern Packet_TM_LFR_PARAMETER_DUMP_t parameter_dump_packet;
92
94
93 // registers
95 // registers
94 extern time_management_regs_t *time_management_regs;
96 extern time_management_regs_t *time_management_regs;
95 extern volatile spectral_matrix_regs_t *spectral_matrix_regs;
97 extern volatile spectral_matrix_regs_t *spectral_matrix_regs;
96
98
97 extern rtems_name misc_name[5];
99 extern rtems_name misc_name[5];
98 extern rtems_id Task_id[20]; /* array of task ids */
100 extern rtems_id Task_id[20]; /* array of task ids */
99
101
100 ring_node * getRingNodeForAveraging( unsigned char frequencyChannel);
102 ring_node * getRingNodeForAveraging( unsigned char frequencyChannel);
101 // ISR
103 // ISR
102 rtems_isr spectral_matrices_isr( rtems_vector_number vector );
104 rtems_isr spectral_matrices_isr( rtems_vector_number vector );
103
105
104 //******************
106 //******************
105 // Spectral Matrices
107 // Spectral Matrices
106 void reset_nb_sm( void );
108 void reset_nb_sm( void );
107 // SM
109 // SM
108 void SM_init_rings( void );
110 void SM_init_rings( void );
109 void SM_reset_current_ring_nodes( void );
111 void SM_reset_current_ring_nodes( void );
110 // ASM
112 // ASM
111 void ASM_generic_init_ring(ring_node_asm *ring, unsigned char nbNodes );
113 void ASM_generic_init_ring(ring_node_asm *ring, unsigned char nbNodes );
112
114
113 //*****************
115 //*****************
114 // Basic Parameters
116 // Basic Parameters
115
117
116 void BP_reset_current_ring_nodes( void );
118 void BP_reset_current_ring_nodes( void );
117 void BP_init_header(bp_packet *packet,
119 void BP_init_header(bp_packet *packet,
118 unsigned int apid, unsigned char sid,
120 unsigned int apid, unsigned char sid,
119 unsigned int packetLength , unsigned char blkNr);
121 unsigned int packetLength , unsigned char blkNr);
120 void BP_init_header_with_spare(bp_packet_with_spare *packet,
122 void BP_init_header_with_spare(bp_packet_with_spare *packet,
121 unsigned int apid, unsigned char sid,
123 unsigned int apid, unsigned char sid,
122 unsigned int packetLength, unsigned char blkNr );
124 unsigned int packetLength, unsigned char blkNr );
123 void BP_send( char *data,
125 void BP_send( char *data,
124 rtems_id queue_id,
126 rtems_id queue_id,
125 unsigned int nbBytesToSend , unsigned int sid );
127 unsigned int nbBytesToSend , unsigned int sid );
126 void BP_send_s1_s2(char *data,
128 void BP_send_s1_s2(char *data,
127 rtems_id queue_id,
129 rtems_id queue_id,
128 unsigned int nbBytesToSend, unsigned int sid );
130 unsigned int nbBytesToSend, unsigned int sid );
129
131
130 //******************
132 //******************
131 // general functions
133 // general functions
132 void reset_sm_status( void );
134 void reset_sm_status( void );
133 void reset_spectral_matrix_regs( void );
135 void reset_spectral_matrix_regs( void );
134 void set_time(unsigned char *time, unsigned char *timeInBuffer );
136 void set_time(unsigned char *time, unsigned char *timeInBuffer );
135 unsigned long long int get_acquisition_time( unsigned char *timePtr );
137 unsigned long long int get_acquisition_time( unsigned char *timePtr );
136 unsigned char getSID( rtems_event_set event );
138 unsigned char getSID( rtems_event_set event );
137
139
138 extern rtems_status_code get_message_queue_id_prc1( rtems_id *queue_id );
140 extern rtems_status_code get_message_queue_id_prc1( rtems_id *queue_id );
139 extern rtems_status_code get_message_queue_id_prc2( rtems_id *queue_id );
141 extern rtems_status_code get_message_queue_id_prc2( rtems_id *queue_id );
140
142
141 //***************************************
143 //***************************************
142 // DEFINITIONS OF STATIC INLINE FUNCTIONS
144 // DEFINITIONS OF STATIC INLINE FUNCTIONS
143 static inline void SM_average(float *averaged_spec_mat_NORM, float *averaged_spec_mat_SBM,
145 static inline void SM_average(float *averaged_spec_mat_NORM, float *averaged_spec_mat_SBM,
144 ring_node *ring_node_tab[],
146 ring_node *ring_node_tab[],
145 unsigned int nbAverageNORM, unsigned int nbAverageSBM,
147 unsigned int nbAverageNORM, unsigned int nbAverageSBM,
146 asm_msg *msgForMATR );
148 asm_msg *msgForMATR );
147
149
148 static inline void SM_average_debug(float *averaged_spec_mat_NORM, float *averaged_spec_mat_SBM,
150 static inline void SM_average_debug(float *averaged_spec_mat_NORM, float *averaged_spec_mat_SBM,
149 ring_node *ring_node_tab[],
151 ring_node *ring_node_tab[],
150 unsigned int nbAverageNORM, unsigned int nbAverageSBM,
152 unsigned int nbAverageNORM, unsigned int nbAverageSBM,
151 asm_msg *msgForMATR );
153 asm_msg *msgForMATR );
152
154
153 void ASM_patch( float *inputASM, float *outputASM );
155 void ASM_patch( float *inputASM, float *outputASM );
154
156
155 void extractReImVectors(float *inputASM, float *outputASM, unsigned int asmComponent );
157 void extractReImVectors(float *inputASM, float *outputASM, unsigned int asmComponent );
156
158
157 static inline void ASM_reorganize_and_divide(float *averaged_spec_mat, float *averaged_spec_mat_reorganized,
159 static inline void ASM_reorganize_and_divide(float *averaged_spec_mat, float *averaged_spec_mat_reorganized,
158 float divider );
160 float divider );
159
161
160 static inline void ASM_compress_reorganize_and_divide(float *averaged_spec_mat, float *compressed_spec_mat,
162 static inline void ASM_compress_reorganize_and_divide(float *averaged_spec_mat, float *compressed_spec_mat,
161 float divider,
163 float divider,
162 unsigned char nbBinsCompressedMatrix, unsigned char nbBinsToAverage , unsigned char ASMIndexStart);
164 unsigned char nbBinsCompressedMatrix, unsigned char nbBinsToAverage , unsigned char ASMIndexStart);
163
165
164 static inline void ASM_convert(volatile float *input_matrix, char *output_matrix);
166 static inline void ASM_convert(volatile float *input_matrix, char *output_matrix);
165
167
166 void SM_average( float *averaged_spec_mat_NORM, float *averaged_spec_mat_SBM,
168 void SM_average( float *averaged_spec_mat_NORM, float *averaged_spec_mat_SBM,
167 ring_node *ring_node_tab[],
169 ring_node *ring_node_tab[],
168 unsigned int nbAverageNORM, unsigned int nbAverageSBM,
170 unsigned int nbAverageNORM, unsigned int nbAverageSBM,
169 asm_msg *msgForMATR )
171 asm_msg *msgForMATR )
170 {
172 {
171 float sum;
173 float sum;
172 unsigned int i;
174 unsigned int i;
173
175
174 for(i=0; i<TOTAL_SIZE_SM; i++)
176 for(i=0; i<TOTAL_SIZE_SM; i++)
175 {
177 {
176 sum = ( (int *) (ring_node_tab[0]->buffer_address) ) [ i ]
178 sum = ( (int *) (ring_node_tab[0]->buffer_address) ) [ i ]
177 + ( (int *) (ring_node_tab[1]->buffer_address) ) [ i ]
179 + ( (int *) (ring_node_tab[1]->buffer_address) ) [ i ]
178 + ( (int *) (ring_node_tab[2]->buffer_address) ) [ i ]
180 + ( (int *) (ring_node_tab[2]->buffer_address) ) [ i ]
179 + ( (int *) (ring_node_tab[3]->buffer_address) ) [ i ]
181 + ( (int *) (ring_node_tab[3]->buffer_address) ) [ i ]
180 + ( (int *) (ring_node_tab[4]->buffer_address) ) [ i ]
182 + ( (int *) (ring_node_tab[4]->buffer_address) ) [ i ]
181 + ( (int *) (ring_node_tab[5]->buffer_address) ) [ i ]
183 + ( (int *) (ring_node_tab[5]->buffer_address) ) [ i ]
182 + ( (int *) (ring_node_tab[6]->buffer_address) ) [ i ]
184 + ( (int *) (ring_node_tab[6]->buffer_address) ) [ i ]
183 + ( (int *) (ring_node_tab[7]->buffer_address) ) [ i ];
185 + ( (int *) (ring_node_tab[7]->buffer_address) ) [ i ];
184
186
185 if ( (nbAverageNORM == 0) && (nbAverageSBM == 0) )
187 if ( (nbAverageNORM == 0) && (nbAverageSBM == 0) )
186 {
188 {
187 averaged_spec_mat_NORM[ i ] = sum;
189 averaged_spec_mat_NORM[ i ] = sum;
188 averaged_spec_mat_SBM[ i ] = sum;
190 averaged_spec_mat_SBM[ i ] = sum;
189 msgForMATR->coarseTimeNORM = ring_node_tab[0]->coarseTime;
191 msgForMATR->coarseTimeNORM = ring_node_tab[0]->coarseTime;
190 msgForMATR->fineTimeNORM = ring_node_tab[0]->fineTime;
192 msgForMATR->fineTimeNORM = ring_node_tab[0]->fineTime;
191 msgForMATR->coarseTimeSBM = ring_node_tab[0]->coarseTime;
193 msgForMATR->coarseTimeSBM = ring_node_tab[0]->coarseTime;
192 msgForMATR->fineTimeSBM = ring_node_tab[0]->fineTime;
194 msgForMATR->fineTimeSBM = ring_node_tab[0]->fineTime;
193 }
195 }
194 else if ( (nbAverageNORM != 0) && (nbAverageSBM != 0) )
196 else if ( (nbAverageNORM != 0) && (nbAverageSBM != 0) )
195 {
197 {
196 averaged_spec_mat_NORM[ i ] = ( averaged_spec_mat_NORM[ i ] + sum );
198 averaged_spec_mat_NORM[ i ] = ( averaged_spec_mat_NORM[ i ] + sum );
197 averaged_spec_mat_SBM[ i ] = ( averaged_spec_mat_SBM[ i ] + sum );
199 averaged_spec_mat_SBM[ i ] = ( averaged_spec_mat_SBM[ i ] + sum );
198 }
200 }
199 else if ( (nbAverageNORM != 0) && (nbAverageSBM == 0) )
201 else if ( (nbAverageNORM != 0) && (nbAverageSBM == 0) )
200 {
202 {
201 averaged_spec_mat_NORM[ i ] = ( averaged_spec_mat_NORM[ i ] + sum );
203 averaged_spec_mat_NORM[ i ] = ( averaged_spec_mat_NORM[ i ] + sum );
202 averaged_spec_mat_SBM[ i ] = sum;
204 averaged_spec_mat_SBM[ i ] = sum;
203 msgForMATR->coarseTimeSBM = ring_node_tab[0]->coarseTime;
205 msgForMATR->coarseTimeSBM = ring_node_tab[0]->coarseTime;
204 msgForMATR->fineTimeSBM = ring_node_tab[0]->fineTime;
206 msgForMATR->fineTimeSBM = ring_node_tab[0]->fineTime;
205 }
207 }
206 else
208 else
207 {
209 {
208 averaged_spec_mat_NORM[ i ] = sum;
210 averaged_spec_mat_NORM[ i ] = sum;
209 averaged_spec_mat_SBM[ i ] = ( averaged_spec_mat_SBM[ i ] + sum );
211 averaged_spec_mat_SBM[ i ] = ( averaged_spec_mat_SBM[ i ] + sum );
210 msgForMATR->coarseTimeNORM = ring_node_tab[0]->coarseTime;
212 msgForMATR->coarseTimeNORM = ring_node_tab[0]->coarseTime;
211 msgForMATR->fineTimeNORM = ring_node_tab[0]->fineTime;
213 msgForMATR->fineTimeNORM = ring_node_tab[0]->fineTime;
212 // PRINTF2("ERR *** in SM_average *** unexpected parameters %d %d\n", nbAverageNORM, nbAverageSBM)
214 // PRINTF2("ERR *** in SM_average *** unexpected parameters %d %d\n", nbAverageNORM, nbAverageSBM)
213 }
215 }
214 }
216 }
215 }
217 }
216
218
217 void SM_average_debug( float *averaged_spec_mat_NORM, float *averaged_spec_mat_SBM,
219 void SM_average_debug( float *averaged_spec_mat_NORM, float *averaged_spec_mat_SBM,
218 ring_node *ring_node_tab[],
220 ring_node *ring_node_tab[],
219 unsigned int nbAverageNORM, unsigned int nbAverageSBM,
221 unsigned int nbAverageNORM, unsigned int nbAverageSBM,
220 asm_msg *msgForMATR )
222 asm_msg *msgForMATR )
221 {
223 {
222 float sum;
224 float sum;
223 unsigned int i;
225 unsigned int i;
224
226
225 for(i=0; i<TOTAL_SIZE_SM; i++)
227 for(i=0; i<TOTAL_SIZE_SM; i++)
226 {
228 {
227 sum = ( (int *) (ring_node_tab[0]->buffer_address) ) [ i ];
229 sum = ( (int *) (ring_node_tab[0]->buffer_address) ) [ i ];
228 averaged_spec_mat_NORM[ i ] = sum;
230 averaged_spec_mat_NORM[ i ] = sum;
229 averaged_spec_mat_SBM[ i ] = sum;
231 averaged_spec_mat_SBM[ i ] = sum;
230 msgForMATR->coarseTimeNORM = ring_node_tab[0]->coarseTime;
232 msgForMATR->coarseTimeNORM = ring_node_tab[0]->coarseTime;
231 msgForMATR->fineTimeNORM = ring_node_tab[0]->fineTime;
233 msgForMATR->fineTimeNORM = ring_node_tab[0]->fineTime;
232 msgForMATR->coarseTimeSBM = ring_node_tab[0]->coarseTime;
234 msgForMATR->coarseTimeSBM = ring_node_tab[0]->coarseTime;
233 msgForMATR->fineTimeSBM = ring_node_tab[0]->fineTime;
235 msgForMATR->fineTimeSBM = ring_node_tab[0]->fineTime;
234 }
236 }
235 }
237 }
236
238
237 void ASM_reorganize_and_divide( float *averaged_spec_mat, float *averaged_spec_mat_reorganized, float divider )
239 void ASM_reorganize_and_divide( float *averaged_spec_mat, float *averaged_spec_mat_reorganized, float divider )
238 {
240 {
239 int frequencyBin;
241 int frequencyBin;
240 int asmComponent;
242 int asmComponent;
241 unsigned int offsetASM;
243 unsigned int offsetASM;
242 unsigned int offsetASMReorganized;
244 unsigned int offsetASMReorganized;
243
245
244 // BUILD DATA
246 // BUILD DATA
245 for (asmComponent = 0; asmComponent < NB_VALUES_PER_SM; asmComponent++)
247 for (asmComponent = 0; asmComponent < NB_VALUES_PER_SM; asmComponent++)
246 {
248 {
247 for( frequencyBin = 0; frequencyBin < NB_BINS_PER_SM; frequencyBin++ )
249 for( frequencyBin = 0; frequencyBin < NB_BINS_PER_SM; frequencyBin++ )
248 {
250 {
249 offsetASMReorganized =
251 offsetASMReorganized =
250 frequencyBin * NB_VALUES_PER_SM
252 frequencyBin * NB_VALUES_PER_SM
251 + asmComponent;
253 + asmComponent;
252 offsetASM =
254 offsetASM =
253 asmComponent * NB_BINS_PER_SM
255 asmComponent * NB_BINS_PER_SM
254 + frequencyBin;
256 + frequencyBin;
255 averaged_spec_mat_reorganized[offsetASMReorganized ] =
257 averaged_spec_mat_reorganized[offsetASMReorganized ] =
256 averaged_spec_mat[ offsetASM ] / divider;
258 averaged_spec_mat[ offsetASM ] / divider;
257 }
259 }
258 }
260 }
259 }
261 }
260
262
261 void ASM_compress_reorganize_and_divide(float *averaged_spec_mat, float *compressed_spec_mat , float divider,
263 void ASM_compress_reorganize_and_divide(float *averaged_spec_mat, float *compressed_spec_mat , float divider,
262 unsigned char nbBinsCompressedMatrix, unsigned char nbBinsToAverage, unsigned char ASMIndexStart )
264 unsigned char nbBinsCompressedMatrix, unsigned char nbBinsToAverage, unsigned char ASMIndexStart )
263 {
265 {
264 int frequencyBin;
266 int frequencyBin;
265 int asmComponent;
267 int asmComponent;
266 int offsetASM;
268 int offsetASM;
267 int offsetCompressed;
269 int offsetCompressed;
268 int k;
270 int k;
269
271
270 // BUILD DATA
272 // BUILD DATA
271 for (asmComponent = 0; asmComponent < NB_VALUES_PER_SM; asmComponent++)
273 for (asmComponent = 0; asmComponent < NB_VALUES_PER_SM; asmComponent++)
272 {
274 {
273 for( frequencyBin = 0; frequencyBin < nbBins