@@ -1,2 +1,2 | |||
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1 | 1 | 3081d1f9bb20b2b64a192585337a292a9804e0c5 LFR_basic-parameters |
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2 | 4ffa7549495b4d1e5ddbda520569468a5e3b8779 header/lfr_common_headers | |
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2 | ad7698268954c5d3d203a3b3ad09fcdf2d536472 header/lfr_common_headers |
@@ -13,6 +13,8 | |||
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13 | 13 | #define VENDORID_GAISLER 0x01 |
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14 | 14 | |
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15 | 15 | // CCR |
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16 | #define POS_FT 19 | |
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17 | // | |
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16 | 18 | #define POS_ITE 12 |
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17 | 19 | #define COUNTER_FIELD_ITE 0x00003000 // 0000 0000 0000 0000 0011 0000 0000 0000 |
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18 | 20 | #define COUNTER_MASK_ITE 0xffffcfff // 1111 1111 1111 1111 1100 1111 1111 1111 |
@@ -28,10 +30,16 | |||
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28 | 30 | #define COUNTER_MASK_DDE 0xffffff3f // 1111 1111 1111 1111 1111 1111 0011 1111 |
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29 | 31 | |
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30 | 32 | // ASR16 |
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33 | #define POS_FPFTID 30 | |
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31 | 34 | #define POS_FPRF 27 |
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35 | #define POS_FDI 16 // FP RF protection enable/disable | |
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36 | #define POS_IUFTID 14 | |
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37 | #define POS_IURF 11 | |
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38 | #define POS_IDI 0 // IU RF protection enable/disable | |
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39 | ||
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32 | 40 | #define COUNTER_FIELD_FPRF 0x38000000 // 0011 1000 0000 0000 0000 0000 0000 0000 |
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33 | 41 | #define COUNTER_MASK_FPRF 0xc7ffffff // 1100 0111 1111 1111 1111 1111 1111 1111 |
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34 | #define POS_IURF 11 | |
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42 | ||
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35 | 43 | #define COUNTER_FIELD_IURF 0x00003800 // 0000 0000 0000 0000 0011 1000 0000 0000 |
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36 | 44 | #define COUNTER_MASK_IURF 0xffffc7ff // 1111 1111 1111 1111 1100 0111 1111 1111 |
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37 | 45 | |
@@ -92,32 +100,6 static void CCR_enableDataCache() | |||
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92 | 100 | CCR_setValue(cacheControlRegister); |
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93 | 101 | } |
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94 | 102 | |
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95 | static void CCR_faultTolerantScheme() | |
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96 | { | |
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97 | // [20:19] FT scheme (FT) - “00” = no FT, “01” = 4-bit checking implemented | |
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98 | unsigned int cacheControlRegister; | |
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99 | unsigned int *plugAndPlayRegister; | |
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100 | unsigned int vendorId; | |
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101 | unsigned int deviceId; | |
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102 | ||
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103 | plugAndPlayRegister = (unsigned int*) REGS_ADDR_PLUGANDPLAY; | |
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104 | vendorId = ( (*plugAndPlayRegister) & 0xff000000 ) >> 24; | |
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105 | deviceId = ( (*plugAndPlayRegister) & 0x00fff000 ) >> 12; | |
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106 | ||
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107 | if( (vendorId == VENDORID_GAISLER) & (deviceId ==DEVICEID_LEON3FT) ) | |
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108 | { | |
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109 | PRINTF("in faultTolerantScheme *** Leon3FT detected, configure the CCR FT bits\n"); | |
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110 | cacheControlRegister = CCR_getValue(); | |
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111 | cacheControlRegister = (cacheControlRegister | 0xc); | |
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112 | CCR_setValue(cacheControlRegister); | |
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113 | } | |
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114 | else | |
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115 | { | |
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116 | PRINTF("in faultTolerantScheme *** not a Leon3FT, no need to configure the CCR FT bits\n"); | |
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117 | PRINTF2(" *** vendorID = 0x%x, deviceId = 0x%x\n", vendorId, deviceId); | |
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118 | } | |
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119 | } | |
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120 | ||
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121 | 103 | static void CCR_enableInstructionBurstFetch() |
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122 | 104 | { |
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123 | 105 | // [16] Instruction burst fetch (IB). This bit enables burst fill during instruction fetch. |
@@ -128,7 +110,7 static void CCR_enableInstructionBurstFe | |||
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128 | 110 | CCR_setValue(cacheControlRegister); |
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129 | 111 | } |
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130 | 112 | |
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131 |
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113 | void CCR_getInstructionAndDataErrorCounters( unsigned int* instructionErrorCounter, unsigned int* dataErrorCounter ) | |
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132 | 114 | { |
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133 | 115 | // [13:12] Instruction Tag Errors (ITE) - Number of detected parity errors in the instruction tag cache. |
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134 | 116 | // Only available if fault-tolerance is enabled (FT field in this register is non-zero). |
@@ -163,7 +145,12 static void CCR_getInstructionAndDataErr | |||
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163 | 145 | //******************************************* |
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164 | 146 | // ASR16 Register protection control register |
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165 | 147 | |
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166 | static void ASR16_get_FPRF_IURF_ErrorCounters( unsigned int* fprfErrorCounter, unsigned int* iurfErrorCounter) | |
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148 | static void ASR16_resetRegisterProtectionControlRegister() | |
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149 | { | |
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150 | *asr16Ptr = 0x00; | |
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151 | } | |
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152 | ||
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153 | void ASR16_get_FPRF_IURF_ErrorCounters( unsigned int* fprfErrorCounter, unsigned int* iurfErrorCounter) | |
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167 | 154 | { |
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168 | 155 | /** This function is used to retrieve the integer unit register file error counter and the floating point unit |
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169 | 156 | * register file error counter |
@@ -189,4 +176,46 static void ASR16_get_FPRF_IURF_ErrorCou | |||
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189 | 176 | *asr16Ptr = asr16; |
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190 | 177 | } |
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191 | 178 | |
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179 | static void faultTolerantScheme() | |
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180 | { | |
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181 | // [20:19] FT scheme (FT) - “00” = no FT, “01” = 4-bit checking implemented | |
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182 | unsigned int cacheControlRegister; | |
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183 | unsigned int *plugAndPlayRegister; | |
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184 | unsigned int vendorId; | |
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185 | unsigned int deviceId; | |
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186 | ||
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187 | plugAndPlayRegister = (unsigned int*) REGS_ADDR_PLUGANDPLAY; | |
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188 | vendorId = ( (*plugAndPlayRegister) & 0xff000000 ) >> 24; | |
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189 | deviceId = ( (*plugAndPlayRegister) & 0x00fff000 ) >> 12; | |
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190 | ||
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191 | cacheControlRegister = CCR_getValue(); | |
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192 | ||
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193 | if( (vendorId == VENDORID_GAISLER) & (deviceId ==DEVICEID_LEON3FT) ) | |
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194 | { | |
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195 | PRINTF("in faultTolerantScheme *** Leon3FT detected\n"); | |
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196 | PRINTF2(" *** vendorID = 0x%x, deviceId = 0x%x\n", vendorId, deviceId); | |
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197 | PRINTF1("ASR16 IU RF protection, bit 0 (IDI) is: 0x%x (0 => protection enabled)\n", | |
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198 | (*asr16Ptr >> POS_IDI) & 1); | |
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199 | PRINTF1("ASR16 FP RF protection, bit 16 (FDI) is: 0x%x (0 => protection enabled)\n", | |
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200 | (*asr16Ptr >> POS_FDI) & 1); | |
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201 | PRINTF1("ASR16 IU FT ID bits [15:14] is: 0x%x (2 => 8-bit parity without restart)\n", | |
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202 | (*asr16Ptr >> POS_IUFTID) & 0x3); | |
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203 | PRINTF1("ASR16 FP FT ID bits [31:30] is: 0x%x (1 => 4-bit parity with restart)\n", | |
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204 | (*asr16Ptr >> POS_FPFTID) & 0x03); | |
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205 | PRINTF1("CCR FT bits [20:19] are: 0x%x (1 => 4-bit parity with restart)\n", | |
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206 | (cacheControlRegister >> POS_FT) & 0x3 ); | |
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207 | ||
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208 | // CCR The FFT bits are just read, the FT scheme is set to “01” = 4-bit checking implemented by default | |
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209 | ||
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210 | // ASR16 Ancillary State Register configuration (Register protection control register) | |
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211 | // IU RF protection is set by default, bit 0 IDI = 0 | |
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212 | // FP RF protection is set by default, bit 16 FDI = 0 | |
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213 | } | |
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214 | else | |
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215 | { | |
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216 | PRINTF("in faultTolerantScheme *** not a Leon3FT not detected\n"); | |
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217 | PRINTF2(" *** vendorID = 0x%x, deviceId = 0x%x\n", vendorId, deviceId); | |
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218 | } | |
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219 | } | |
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220 | ||
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192 | 221 | #endif /* GSCMEMORY_HPP_ */ |
@@ -10,6 +10,7 | |||
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10 | 10 | #include "fsw_spacewire.h" |
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11 | 11 | #include "lfr_cpu_usage_report.h" |
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12 | 12 | |
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13 | ||
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13 | 14 | enum lfr_reset_cause_t{ |
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14 | 15 | UNKNOWN_CAUSE, |
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15 | 16 | POWER_ON, |
@@ -20,6 +21,8 enum lfr_reset_cause_t{ | |||
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20 | 21 | }; |
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21 | 22 | |
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22 | 23 | extern gptimer_regs_t *gptimer_regs; |
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24 | extern void ASR16_get_FPRF_IURF_ErrorCounters( unsigned int*, unsigned int* ); | |
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25 | extern void CCR_getInstructionAndDataErrorCounters( unsigned int*, unsigned int* ); | |
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23 | 26 | |
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24 | 27 | #define LFR_RESET_CAUSE_UNKNOWN_CAUSE 0 |
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25 | 28 |
@@ -82,6 +82,8 typedef struct asm_msg | |||
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82 | 82 | unsigned int fineTimeSBM; |
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83 | 83 | } asm_msg; |
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84 | 84 | |
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85 | extern unsigned char thisIsAnASMRestart; | |
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86 | ||
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85 | 87 | extern volatile int sm_f0[ ]; |
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86 | 88 | extern volatile int sm_f1[ ]; |
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87 | 89 | extern volatile int sm_f2[ ]; |
@@ -32,6 +32,7 int fdSPW = 0; | |||
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32 | 32 | int fdUART = 0; |
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33 | 33 | unsigned char lfrCurrentMode; |
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34 | 34 | unsigned char pa_bia_status_info; |
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35 | unsigned char thisIsAnASMRestart = 0; | |
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35 | 36 | |
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36 | 37 | // WAVEFORMS GLOBAL VARIABLES // 2048 * 3 * 4 + 2 * 4 = 24576 + 8 bytes = 24584 |
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37 | 38 | // 97 * 256 = 24832 => delta = 248 bytes = 62 words |
@@ -81,19 +81,22 void initCache() | |||
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81 | 81 | |
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82 | 82 | unsigned int cacheControlRegister; |
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83 | 83 | |
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84 | CCR_resetCacheControlRegister(); | |
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85 | ASR16_resetRegisterProtectionControlRegister(); | |
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86 | ||
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84 | 87 | cacheControlRegister = CCR_getValue(); |
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85 |
PRINTF1("(0) |
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86 | ||
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87 | CCR_resetCacheControlRegister(); | |
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88 | PRINTF1("(0) CCR - Cache Control Register = %x\n", cacheControlRegister); | |
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89 | PRINTF1("(0) ASR16 = %x\n", *asr16Ptr); | |
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88 | 90 | |
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89 | 91 | CCR_enableInstructionCache(); // ICS bits |
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90 | 92 | CCR_enableDataCache(); // DCS bits |
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91 | 93 | CCR_enableInstructionBurstFetch(); // IB bit |
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92 | 94 | |
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95 | faultTolerantScheme(); | |
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96 | ||
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93 | 97 | cacheControlRegister = CCR_getValue(); |
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94 |
PRINTF1("(1) |
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95 | ||
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96 | CCR_faultTolerantScheme(); | |
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98 | PRINTF1("(1) CCR - Cache Control Register = %x\n", cacheControlRegister); | |
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99 | PRINTF1("(1) ASR16 Register protection control register = %x\n", *asr16Ptr); | |
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97 | 100 | |
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98 | 101 | PRINTF("\n"); |
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99 | 102 | } |
@@ -198,8 +201,6 rtems_task Init( rtems_task_argument ign | |||
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198 | 201 | |
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199 | 202 | // ************************** |
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200 | 203 | // <SPACEWIRE INITIALIZATION> |
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201 | grspw_timecode_callback = &timecode_irq_handler; | |
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202 | ||
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203 | 204 | status_spw = spacewire_open_link(); // (1) open the link |
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204 | 205 | if ( status_spw != RTEMS_SUCCESSFUL ) |
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205 | 206 | { |
@@ -268,8 +269,11 rtems_task Init( rtems_task_argument ign | |||
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268 | 269 | |
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269 | 270 | set_hk_lfr_sc_potential_flag( true ); |
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270 | 271 | |
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271 |
// start the timer |
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272 | status = rtems_timer_fire_after( timecode_timer_id, TIMECODE_TIMER_TIMEOUT, timecode_timer_routine, NULL ); | |
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272 | // start the timer to detect a missing spacewire timecode | |
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273 | // the timeout is larger because the spw IP needs to receive several valid timecodes before generating a tickout | |
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274 | // if a tickout is generated, the timer is restarted | |
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275 | status = rtems_timer_fire_after( timecode_timer_id, TIMECODE_TIMER_TIMEOUT_INIT, timecode_timer_routine, NULL ); | |
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276 | grspw_timecode_callback = &timecode_irq_handler; | |
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273 | 277 | |
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274 | 278 | status = rtems_task_delete(RTEMS_SELF); |
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275 | 279 |
@@ -232,21 +232,21 rtems_task hous_task(rtems_task_argument | |||
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232 | 232 | PRINTF1("in HOUS *** ERR get_message_queue_id_send %d\n", status) |
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233 | 233 | } |
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234 | 234 | |
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235 | BOOT_PRINTF("in HOUS ***\n") | |
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235 | BOOT_PRINTF("in HOUS ***\n"); | |
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236 | 236 | |
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237 | 237 | if (rtems_rate_monotonic_ident( name_hk_rate_monotonic, &HK_id) != RTEMS_SUCCESSFUL) { |
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238 | 238 | status = rtems_rate_monotonic_create( name_hk_rate_monotonic, &HK_id ); |
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239 | 239 | if( status != RTEMS_SUCCESSFUL ) { |
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240 | PRINTF1( "rtems_rate_monotonic_create failed with status of %d\n", status ) | |
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240 | PRINTF1( "rtems_rate_monotonic_create failed with status of %d\n", status ); | |
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241 | 241 | } |
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242 | 242 | } |
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243 | 243 | |
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244 | 244 | status = rtems_rate_monotonic_cancel(HK_id); |
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245 | 245 | if( status != RTEMS_SUCCESSFUL ) { |
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246 | PRINTF1( "ERR *** in HOUS *** rtems_rate_monotonic_cancel(HK_id) ***code: %d\n", status ) | |
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246 | PRINTF1( "ERR *** in HOUS *** rtems_rate_monotonic_cancel(HK_id) ***code: %d\n", status ); | |
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247 | 247 | } |
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248 | 248 | else { |
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249 | DEBUG_PRINTF("OK *** in HOUS *** rtems_rate_monotonic_cancel(HK_id)\n") | |
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249 | DEBUG_PRINTF("OK *** in HOUS *** rtems_rate_monotonic_cancel(HK_id)\n"); | |
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250 | 250 | } |
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251 | 251 | |
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252 | 252 | // startup phase |
@@ -339,7 +339,7 rtems_task dumb_task( rtems_task_argumen | |||
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339 | 339 | unsigned int fine_time = 0; |
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340 | 340 | rtems_event_set event_out; |
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341 | 341 | |
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342 |
char *DumbMessages[1 |
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342 | char *DumbMessages[15] = {"in DUMB *** default", // RTEMS_EVENT_0 | |
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343 | 343 | "in DUMB *** timecode_irq_handler", // RTEMS_EVENT_1 |
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344 | 344 | "in DUMB *** f3 buffer changed", // RTEMS_EVENT_2 |
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345 | 345 | "in DUMB *** in SMIQ *** Error sending event to AVF0", // RTEMS_EVENT_3 |
@@ -352,7 +352,8 rtems_task dumb_task( rtems_task_argumen | |||
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352 | 352 | "VHDL ERR *** waveform picker", // RTEMS_EVENT_10 |
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353 | 353 | "VHDL ERR *** unexpected ready matrix values", // RTEMS_EVENT_11 |
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354 | 354 | "WATCHDOG timer", // RTEMS_EVENT_12 |
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355 |
"TIMECODE timer" |
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355 | "TIMECODE timer", // RTEMS_EVENT_13 | |
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356 | "TIMECODE ISR" // RTEMS_EVENT_14 | |
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356 | 357 | }; |
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357 | 358 | |
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358 | 359 | BOOT_PRINTF("in DUMB *** \n") |
@@ -360,7 +361,8 rtems_task dumb_task( rtems_task_argumen | |||
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360 | 361 | while(1){ |
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361 | 362 | rtems_event_receive(RTEMS_EVENT_0 | RTEMS_EVENT_1 | RTEMS_EVENT_2 | RTEMS_EVENT_3 |
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362 | 363 | | RTEMS_EVENT_4 | RTEMS_EVENT_5 | RTEMS_EVENT_6 | RTEMS_EVENT_7 |
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363 |
| RTEMS_EVENT_8 | RTEMS_EVENT_9 | RTEMS_EVENT_12 | RTEMS_EVENT_13 |
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364 | | RTEMS_EVENT_8 | RTEMS_EVENT_9 | RTEMS_EVENT_12 | RTEMS_EVENT_13 | |
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365 | | RTEMS_EVENT_14, | |
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364 | 366 | RTEMS_WAIT | RTEMS_EVENT_ANY, RTEMS_NO_TIMEOUT, &event_out); // wait for an RTEMS_EVENT |
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365 | 367 | intEventOut = (unsigned int) event_out; |
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366 | 368 | for ( i=0; i<32; i++) |
@@ -377,6 +379,10 rtems_task dumb_task( rtems_task_argumen | |||
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377 | 379 | { |
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378 | 380 | PRINTF1("%s\n", DumbMessages[13]) |
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379 | 381 | } |
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382 | if (i==14) | |
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383 | { | |
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384 | PRINTF1("%s\n", DumbMessages[1]) | |
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385 | } | |
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380 | 386 | } |
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381 | 387 | } |
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382 | 388 | } |
@@ -735,3 +741,43 void set_hk_lfr_time_not_synchro() | |||
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735 | 741 | } |
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736 | 742 | |
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737 | 743 | } |
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744 | ||
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745 | void set_hk_lfr_ahb_correctable() | |
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746 | { | |
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747 | /** This function builds the error counter hk_lfr_ahb_correctable using the statistics provided | |
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748 | * by the Cache Control Register (ASI 2, offset 0) and in the Register Protection Control Register (ASR16) on the | |
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749 | * detected errors in the cache, in the integer unit and in the floating point unit. | |
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750 | * | |
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751 | * @param void | |
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752 | * | |
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753 | * @return void | |
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754 | * | |
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755 | * All errors are summed to set the value of the hk_lfr_ahb_correctable counter. | |
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756 | * | |
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757 | */ | |
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758 | ||
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759 | unsigned int ahb_correctable; | |
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760 | unsigned int instructionErrorCounter; | |
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761 | unsigned int dataErrorCounter; | |
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762 | unsigned int fprfErrorCounter; | |
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763 | unsigned int iurfErrorCounter; | |
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764 | ||
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765 | CCR_getInstructionAndDataErrorCounters( &instructionErrorCounter, &dataErrorCounter); | |
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766 | ASR16_get_FPRF_IURF_ErrorCounters( &fprfErrorCounter, &iurfErrorCounter); | |
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767 | ||
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768 | ahb_correctable = instructionErrorCounter | |
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769 | + dataErrorCounter | |
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770 | + fprfErrorCounter | |
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771 | + iurfErrorCounter | |
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772 | + housekeeping_packet.hk_lfr_ahb_correctable; | |
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773 | ||
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774 | if (ahb_correctable > 255) | |
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775 | { | |
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776 | housekeeping_packet.hk_lfr_ahb_correctable = 255; | |
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777 | } | |
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778 | else | |
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779 | { | |
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780 | housekeeping_packet.hk_lfr_ahb_correctable = ahb_correctable; | |
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781 | } | |
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782 | ||
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783 | } |
@@ -680,11 +680,14 void increase_unsigned_char_counter( uns | |||
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680 | 680 | |
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681 | 681 | rtems_timer_service_routine timecode_timer_routine( rtems_id timer_id, void *user_data ) |
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682 | 682 | { |
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683 | static unsigned char initStep = 1; | |
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683 | 684 | |
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684 | 685 | unsigned char currentTimecodeCtr; |
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685 | 686 | |
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686 | 687 | currentTimecodeCtr = (unsigned char) (grspwPtr[0] & TIMECODE_MASK); |
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687 | 688 | |
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689 | if (initStep == 1) | |
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690 | { | |
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688 | 691 | if (currentTimecodeCtr == previousTimecodeCtr) |
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689 | 692 | { |
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690 | 693 | //************************ |
@@ -705,6 +708,14 rtems_timer_service_routine timecode_tim | |||
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705 | 708 | // this is why the timer has fired |
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706 | 709 | increase_unsigned_char_counter( &housekeeping_packet.hk_lfr_timecode_invalid ); |
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707 | 710 | } |
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711 | } | |
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712 | else | |
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713 | { | |
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714 | initStep = 1; | |
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715 | //************************ | |
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716 | // HK_LFR_TIMECODE_MISSING | |
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717 | increase_unsigned_char_counter( &housekeeping_packet.hk_lfr_timecode_missing ); | |
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718 | } | |
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708 | 719 | |
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709 | 720 | rtems_event_send( Task_id[TASKID_DUMB], RTEMS_EVENT_13 ); |
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710 | 721 | } |
@@ -824,6 +835,10 void timecode_irq_handler( void *pDev, v | |||
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824 | 835 | // launch the timecode timer to detect missing or invalid timecodes |
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825 | 836 | previousTimecodeCtr = incomingTimecode; // update the previousTimecodeCtr value |
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826 | 837 | status = rtems_timer_fire_after( timecode_timer_id, TIMECODE_TIMER_TIMEOUT, timecode_timer_routine, NULL ); |
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838 | if (status != RTEMS_SUCCESSFUL) | |
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839 | { | |
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840 | rtems_event_send( Task_id[TASKID_DUMB], RTEMS_EVENT_14 ); | |
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841 | } | |
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827 | 842 | } |
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828 | 843 | |
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829 | 844 | void init_header_cwf( Header_TM_LFR_SCIENCE_CWF_t *header ) |
@@ -41,7 +41,7 rtems_task avf0_task( rtems_task_argumen | |||
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41 | 41 | rtems_event_set event_out; |
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42 | 42 | rtems_status_code status; |
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43 | 43 | rtems_id queue_id_prc0; |
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44 |
asm_msg msgFor |
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44 | asm_msg msgForPRC; | |
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45 | 45 | ring_node *nodeForAveraging; |
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46 | 46 | ring_node *ring_node_tab[8]; |
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47 | 47 | ring_node_asm *current_ring_node_asm_burst_sbm_f0; |
@@ -78,9 +78,9 rtems_task avf0_task( rtems_task_argumen | |||
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78 | 78 | |
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79 | 79 | //**************************************** |
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80 | 80 | // initialize the mesage for the MATR task |
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81 |
msgFor |
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82 |
msgFor |
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83 |
msgFor |
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81 | msgForPRC.norm = current_ring_node_asm_norm_f0; | |
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82 | msgForPRC.burst_sbm = current_ring_node_asm_burst_sbm_f0; | |
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83 | msgForPRC.event = 0x00; // this composite event will be sent to the PRC0 task | |
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84 | 84 | // |
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85 | 85 | //**************************************** |
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86 | 86 | |
@@ -98,7 +98,7 rtems_task avf0_task( rtems_task_argumen | |||
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98 | 98 | current_ring_node_asm_burst_sbm_f0->matrix, |
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99 | 99 | ring_node_tab, |
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100 | 100 | nb_norm_bp1, nb_sbm_bp1, |
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101 |
&msgFor |
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101 | &msgForPRC ); | |
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102 | 102 | |
|
103 | 103 | // update nb_average |
|
104 | 104 | nb_norm_bp1 = nb_norm_bp1 + NB_SM_BEFORE_AVF0; |
@@ -114,11 +114,11 rtems_task avf0_task( rtems_task_argumen | |||
|
114 | 114 | current_ring_node_asm_burst_sbm_f0 = current_ring_node_asm_burst_sbm_f0->next; |
|
115 | 115 | if ( lfrCurrentMode == LFR_MODE_BURST ) |
|
116 | 116 | { |
|
117 |
msgFor |
|
|
117 | msgForPRC.event = msgForPRC.event | RTEMS_EVENT_BURST_BP1_F0; | |
|
118 | 118 | } |
|
119 | 119 | else if ( (lfrCurrentMode == LFR_MODE_SBM1) || (lfrCurrentMode == LFR_MODE_SBM2) ) |
|
120 | 120 | { |
|
121 |
msgFor |
|
|
121 | msgForPRC.event = msgForPRC.event | RTEMS_EVENT_SBM_BP1_F0; | |
|
122 | 122 | } |
|
123 | 123 | } |
|
124 | 124 | |
@@ -127,11 +127,11 rtems_task avf0_task( rtems_task_argumen | |||
|
127 | 127 | nb_sbm_bp2 = 0; |
|
128 | 128 | if ( lfrCurrentMode == LFR_MODE_BURST ) |
|
129 | 129 | { |
|
130 |
msgFor |
|
|
130 | msgForPRC.event = msgForPRC.event | RTEMS_EVENT_BURST_BP2_F0; | |
|
131 | 131 | } |
|
132 | 132 | else if ( (lfrCurrentMode == LFR_MODE_SBM1) || (lfrCurrentMode == LFR_MODE_SBM2) ) |
|
133 | 133 | { |
|
134 |
msgFor |
|
|
134 | msgForPRC.event = msgForPRC.event | RTEMS_EVENT_SBM_BP2_F0; | |
|
135 | 135 | } |
|
136 | 136 | } |
|
137 | 137 | |
@@ -143,7 +143,7 rtems_task avf0_task( rtems_task_argumen | |||
|
143 | 143 | if ( (lfrCurrentMode == LFR_MODE_NORMAL) |
|
144 | 144 | || (lfrCurrentMode == LFR_MODE_SBM1) || (lfrCurrentMode == LFR_MODE_SBM2) ) |
|
145 | 145 | { |
|
146 |
msgFor |
|
|
146 | msgForPRC.event = msgForPRC.event | RTEMS_EVENT_NORM_BP1_F0; | |
|
147 | 147 | } |
|
148 | 148 | } |
|
149 | 149 | |
@@ -153,7 +153,7 rtems_task avf0_task( rtems_task_argumen | |||
|
153 | 153 | if ( (lfrCurrentMode == LFR_MODE_NORMAL) |
|
154 | 154 | || (lfrCurrentMode == LFR_MODE_SBM1) || (lfrCurrentMode == LFR_MODE_SBM2) ) |
|
155 | 155 | { |
|
156 |
msgFor |
|
|
156 | msgForPRC.event = msgForPRC.event | RTEMS_EVENT_NORM_BP2_F0; | |
|
157 | 157 | } |
|
158 | 158 | } |
|
159 | 159 | |
@@ -163,19 +163,19 rtems_task avf0_task( rtems_task_argumen | |||
|
163 | 163 | if ( (lfrCurrentMode == LFR_MODE_NORMAL) |
|
164 | 164 | || (lfrCurrentMode == LFR_MODE_SBM1) || (lfrCurrentMode == LFR_MODE_SBM2) ) |
|
165 | 165 | { |
|
166 |
msgFor |
|
|
166 | msgForPRC.event = msgForPRC.event | RTEMS_EVENT_NORM_ASM_F0; | |
|
167 | 167 | } |
|
168 | 168 | } |
|
169 | 169 | |
|
170 | 170 | //************************* |
|
171 |
// send the message to |
|
|
172 |
if (msgFor |
|
|
171 | // send the message to PRC | |
|
172 | if (msgForPRC.event != 0x00) | |
|
173 | 173 | { |
|
174 |
status = rtems_message_queue_send( queue_id_prc0, (char *) &msgFor |
|
|
174 | status = rtems_message_queue_send( queue_id_prc0, (char *) &msgForPRC, MSG_QUEUE_SIZE_PRC0); | |
|
175 | 175 | } |
|
176 | 176 | |
|
177 | 177 | if (status != RTEMS_SUCCESSFUL) { |
|
178 |
PRINTF1("in AVF0 *** Error sending message to |
|
|
178 | PRINTF1("in AVF0 *** Error sending message to PRC, code %d\n", status) | |
|
179 | 179 | } |
|
180 | 180 | } |
|
181 | 181 | } |
@@ -42,7 +42,7 rtems_task avf1_task( rtems_task_argumen | |||
|
42 | 42 | rtems_event_set event_out; |
|
43 | 43 | rtems_status_code status; |
|
44 | 44 | rtems_id queue_id_prc1; |
|
45 |
asm_msg msgFor |
|
|
45 | asm_msg msgForPRC; | |
|
46 | 46 | ring_node *nodeForAveraging; |
|
47 | 47 | ring_node *ring_node_tab[NB_SM_BEFORE_AVF0]; |
|
48 | 48 | ring_node_asm *current_ring_node_asm_burst_sbm_f1; |
@@ -79,9 +79,9 rtems_task avf1_task( rtems_task_argumen | |||
|
79 | 79 | |
|
80 | 80 | //**************************************** |
|
81 | 81 | // initialize the mesage for the MATR task |
|
82 |
msgFor |
|
|
83 |
msgFor |
|
|
84 |
msgFor |
|
|
82 | msgForPRC.norm = current_ring_node_asm_norm_f1; | |
|
83 | msgForPRC.burst_sbm = current_ring_node_asm_burst_sbm_f1; | |
|
84 | msgForPRC.event = 0x00; // this composite event will be sent to the PRC1 task | |
|
85 | 85 | // |
|
86 | 86 | //**************************************** |
|
87 | 87 | |
@@ -99,7 +99,7 rtems_task avf1_task( rtems_task_argumen | |||
|
99 | 99 | current_ring_node_asm_burst_sbm_f1->matrix, |
|
100 | 100 | ring_node_tab, |
|
101 | 101 | nb_norm_bp1, nb_sbm_bp1, |
|
102 |
&msgFor |
|
|
102 | &msgForPRC ); | |
|
103 | 103 | |
|
104 | 104 | // update nb_average |
|
105 | 105 | nb_norm_bp1 = nb_norm_bp1 + NB_SM_BEFORE_AVF1; |
@@ -115,11 +115,11 rtems_task avf1_task( rtems_task_argumen | |||
|
115 | 115 | current_ring_node_asm_burst_sbm_f1 = current_ring_node_asm_burst_sbm_f1->next; |
|
116 | 116 | if ( lfrCurrentMode == LFR_MODE_BURST ) |
|
117 | 117 | { |
|
118 |
msgFor |
|
|
118 | msgForPRC.event = msgForPRC.event | RTEMS_EVENT_BURST_BP1_F1; | |
|
119 | 119 | } |
|
120 | 120 | else if ( lfrCurrentMode == LFR_MODE_SBM2 ) |
|
121 | 121 | { |
|
122 |
msgFor |
|
|
122 | msgForPRC.event = msgForPRC.event | RTEMS_EVENT_SBM_BP1_F1; | |
|
123 | 123 | } |
|
124 | 124 | } |
|
125 | 125 | |
@@ -128,11 +128,11 rtems_task avf1_task( rtems_task_argumen | |||
|
128 | 128 | nb_sbm_bp2 = 0; |
|
129 | 129 | if ( lfrCurrentMode == LFR_MODE_BURST ) |
|
130 | 130 | { |
|
131 |
msgFor |
|
|
131 | msgForPRC.event = msgForPRC.event | RTEMS_EVENT_BURST_BP2_F1; | |
|
132 | 132 | } |
|
133 | 133 | else if ( lfrCurrentMode == LFR_MODE_SBM2 ) |
|
134 | 134 | { |
|
135 |
msgFor |
|
|
135 | msgForPRC.event = msgForPRC.event | RTEMS_EVENT_SBM_BP2_F1; | |
|
136 | 136 | } |
|
137 | 137 | } |
|
138 | 138 | |
@@ -144,7 +144,7 rtems_task avf1_task( rtems_task_argumen | |||
|
144 | 144 | if ( (lfrCurrentMode == LFR_MODE_NORMAL) |
|
145 | 145 | || (lfrCurrentMode == LFR_MODE_SBM1) || (lfrCurrentMode == LFR_MODE_SBM2) ) |
|
146 | 146 | { |
|
147 |
msgFor |
|
|
147 | msgForPRC.event = msgForPRC.event | RTEMS_EVENT_NORM_BP1_F1; | |
|
148 | 148 | } |
|
149 | 149 | } |
|
150 | 150 | |
@@ -154,7 +154,7 rtems_task avf1_task( rtems_task_argumen | |||
|
154 | 154 | if ( (lfrCurrentMode == LFR_MODE_NORMAL) |
|
155 | 155 | || (lfrCurrentMode == LFR_MODE_SBM1) || (lfrCurrentMode == LFR_MODE_SBM2) ) |
|
156 | 156 | { |
|
157 |
msgFor |
|
|
157 | msgForPRC.event = msgForPRC.event | RTEMS_EVENT_NORM_BP2_F1; | |
|
158 | 158 | } |
|
159 | 159 | } |
|
160 | 160 | |
@@ -164,15 +164,15 rtems_task avf1_task( rtems_task_argumen | |||
|
164 | 164 | if ( (lfrCurrentMode == LFR_MODE_NORMAL) |
|
165 | 165 | || (lfrCurrentMode == LFR_MODE_SBM1) || (lfrCurrentMode == LFR_MODE_SBM2) ) |
|
166 | 166 | { |
|
167 |
msgFor |
|
|
167 | msgForPRC.event = msgForPRC.event | RTEMS_EVENT_NORM_ASM_F1; | |
|
168 | 168 | } |
|
169 | 169 | } |
|
170 | 170 | |
|
171 | 171 | //************************* |
|
172 |
// send the message to |
|
|
173 |
if (msgFor |
|
|
172 | // send the message to PRC | |
|
173 | if (msgForPRC.event != 0x00) | |
|
174 | 174 | { |
|
175 |
status = rtems_message_queue_send( queue_id_prc1, (char *) &msgFor |
|
|
175 | status = rtems_message_queue_send( queue_id_prc1, (char *) &msgForPRC, MSG_QUEUE_SIZE_PRC1); | |
|
176 | 176 | } |
|
177 | 177 | |
|
178 | 178 | if (status != RTEMS_SUCCESSFUL) { |
@@ -38,7 +38,7 rtems_task avf2_task( rtems_task_argumen | |||
|
38 | 38 | rtems_event_set event_out; |
|
39 | 39 | rtems_status_code status; |
|
40 | 40 | rtems_id queue_id_prc2; |
|
41 |
asm_msg msgFor |
|
|
41 | asm_msg msgForPRC; | |
|
42 | 42 | ring_node *nodeForAveraging; |
|
43 | 43 | ring_node_asm *current_ring_node_asm_norm_f2; |
|
44 | 44 | |
@@ -67,9 +67,9 rtems_task avf2_task( rtems_task_argumen | |||
|
67 | 67 | |
|
68 | 68 | //**************************************** |
|
69 | 69 | // initialize the mesage for the MATR task |
|
70 |
msgFor |
|
|
71 |
msgFor |
|
|
72 |
msgFor |
|
|
70 | msgForPRC.norm = current_ring_node_asm_norm_f2; | |
|
71 | msgForPRC.burst_sbm = NULL; | |
|
72 | msgForPRC.event = 0x00; // this composite event will be sent to the PRC2 task | |
|
73 | 73 | // |
|
74 | 74 | //**************************************** |
|
75 | 75 | |
@@ -79,7 +79,7 rtems_task avf2_task( rtems_task_argumen | |||
|
79 | 79 | SM_average_f2( current_ring_node_asm_norm_f2->matrix, |
|
80 | 80 | nodeForAveraging, |
|
81 | 81 | nb_norm_bp1, |
|
82 |
&msgFor |
|
|
82 | &msgForPRC ); | |
|
83 | 83 | |
|
84 | 84 | // update nb_average |
|
85 | 85 | nb_norm_bp1 = nb_norm_bp1 + NB_SM_BEFORE_AVF2; |
@@ -94,7 +94,7 rtems_task avf2_task( rtems_task_argumen | |||
|
94 | 94 | if ( (lfrCurrentMode == LFR_MODE_NORMAL) || (lfrCurrentMode == LFR_MODE_SBM1) |
|
95 | 95 | || (lfrCurrentMode == LFR_MODE_SBM2) ) |
|
96 | 96 | { |
|
97 |
msgFor |
|
|
97 | msgForPRC.event = msgForPRC.event | RTEMS_EVENT_NORM_BP1_F2; | |
|
98 | 98 | } |
|
99 | 99 | } |
|
100 | 100 | |
@@ -104,7 +104,7 rtems_task avf2_task( rtems_task_argumen | |||
|
104 | 104 | if ( (lfrCurrentMode == LFR_MODE_NORMAL) || (lfrCurrentMode == LFR_MODE_SBM1) |
|
105 | 105 | || (lfrCurrentMode == LFR_MODE_SBM2) ) |
|
106 | 106 | { |
|
107 |
msgFor |
|
|
107 | msgForPRC.event = msgForPRC.event | RTEMS_EVENT_NORM_BP2_F2; | |
|
108 | 108 | } |
|
109 | 109 | } |
|
110 | 110 | |
@@ -114,19 +114,19 rtems_task avf2_task( rtems_task_argumen | |||
|
114 | 114 | if ( (lfrCurrentMode == LFR_MODE_NORMAL) || (lfrCurrentMode == LFR_MODE_SBM1) |
|
115 | 115 | || (lfrCurrentMode == LFR_MODE_SBM2) ) |
|
116 | 116 | { |
|
117 |
msgFor |
|
|
117 | msgForPRC.event = msgForPRC.event | RTEMS_EVENT_NORM_ASM_F2; | |
|
118 | 118 | } |
|
119 | 119 | } |
|
120 | 120 | |
|
121 | 121 | //************************* |
|
122 |
// send the message to |
|
|
123 |
if (msgFor |
|
|
122 | // send the message to PRC2 | |
|
123 | if (msgForPRC.event != 0x00) | |
|
124 | 124 | { |
|
125 |
status = rtems_message_queue_send( queue_id_prc2, (char *) &msgFor |
|
|
125 | status = rtems_message_queue_send( queue_id_prc2, (char *) &msgForPRC, MSG_QUEUE_SIZE_PRC2); | |
|
126 | 126 | } |
|
127 | 127 | |
|
128 | 128 | if (status != RTEMS_SUCCESSFUL) { |
|
129 |
PRINTF1("in AVF2 *** Error sending message to |
|
|
129 | PRINTF1("in AVF2 *** Error sending message to PRC2, code %d\n", status) | |
|
130 | 130 | } |
|
131 | 131 | } |
|
132 | 132 | } |
@@ -16,6 +16,13 unsigned int nb_sm_f0_aux_f1; | |||
|
16 | 16 | unsigned int nb_sm_f1; |
|
17 | 17 | unsigned int nb_sm_f0_aux_f2; |
|
18 | 18 | |
|
19 | typedef enum restartState_t | |
|
20 | { | |
|
21 | WAIT_FOR_F2, | |
|
22 | WAIT_FOR_F1, | |
|
23 | WAIT_FOR_F0 | |
|
24 | } restartState; | |
|
25 | ||
|
19 | 26 | //************************ |
|
20 | 27 | // spectral matrices rings |
|
21 | 28 | ring_node sm_ring_f0[ NB_RING_NODES_SM_F0 ]; |
@@ -118,7 +125,7 void spectral_matrices_isr_f1( unsigned | |||
|
118 | 125 | unsigned char status; |
|
119 | 126 | ring_node *full_ring_node; |
|
120 | 127 | |
|
121 |
status = (statusReg & 0x0c) >> 2; // [1100] get the status_ready_matrix_f |
|
|
128 | status = (statusReg & 0x0c) >> 2; // [1100] get the status_ready_matrix_f1_x bits | |
|
122 | 129 | |
|
123 | 130 | switch(status) |
|
124 | 131 | { |
@@ -175,7 +182,7 void spectral_matrices_isr_f2( unsigned | |||
|
175 | 182 | unsigned char status; |
|
176 | 183 | rtems_status_code status_code; |
|
177 | 184 | |
|
178 |
status = (statusReg & 0x30) >> 4; // [0011 0000] get the status_ready_matrix_f |
|
|
185 | status = (statusReg & 0x30) >> 4; // [0011 0000] get the status_ready_matrix_f2_x bits | |
|
179 | 186 | |
|
180 | 187 | switch(status) |
|
181 | 188 | { |
@@ -235,15 +242,48 rtems_isr spectral_matrices_isr( rtems_v | |||
|
235 | 242 | |
|
236 | 243 | unsigned char statusReg; |
|
237 | 244 | |
|
245 | static restartState state = WAIT_FOR_F2; | |
|
246 | ||
|
238 | 247 | statusReg = spectral_matrix_regs->status; |
|
239 | 248 | |
|
249 | if (thisIsAnASMRestart == 0) | |
|
250 | { // this is not a restart sequence, process incoming matrices normally | |
|
240 | 251 | spectral_matrices_isr_f0( statusReg ); |
|
241 | 252 | |
|
242 | 253 | spectral_matrices_isr_f1( statusReg ); |
|
243 | 254 | |
|
244 | 255 | spectral_matrices_isr_f2( statusReg ); |
|
256 | } | |
|
257 | else | |
|
258 | { // a restart sequence has to be launched | |
|
259 | switch (state) { | |
|
260 | case WAIT_FOR_F2: | |
|
261 | if ((statusReg & 0x30) != 0x00) // [0011 0000] check the status_ready_matrix_f2_x bits | |
|
262 | { | |
|
263 | state = WAIT_FOR_F1; | |
|
264 | } | |
|
265 | break; | |
|
266 | case WAIT_FOR_F1: | |
|
267 | if ((statusReg & 0x0c) != 0x00) // [0000 1100] check the status_ready_matrix_f1_x bits | |
|
268 | { | |
|
269 | state = WAIT_FOR_F0; | |
|
270 | } | |
|
271 | break; | |
|
272 | case WAIT_FOR_F0: | |
|
273 | if ((statusReg & 0x03) != 0x00) // [0000 0011] check the status_ready_matrix_f0_x bits | |
|
274 | { | |
|
275 | state = WAIT_FOR_F2; | |
|
276 | thisIsAnASMRestart = 0; | |
|
277 | } | |
|
278 | break; | |
|
279 | default: | |
|
280 | break; | |
|
281 | } | |
|
282 | reset_sm_status(); | |
|
283 | } | |
|
245 | 284 | |
|
246 | 285 | spectral_matrix_isr_error_handler( statusReg ); |
|
286 | ||
|
247 | 287 | } |
|
248 | 288 | |
|
249 | 289 | //****************** |
@@ -403,7 +443,7 void BP_send_s1_s2(char *data, rtems_id | |||
|
403 | 443 | |
|
404 | 444 | // SEND PACKET |
|
405 | 445 | // before lastValidTransitionDate, the data are drops even if they are ready |
|
406 |
// this guarantees that no SBM packets will be received before the request |
|
|
446 | // this guarantees that no SBM packets will be received before the requested enter mode time | |
|
407 | 447 | if ( time_management_regs->coarse_time >= lastValidEnterModeTime) |
|
408 | 448 | { |
|
409 | 449 | status = rtems_message_queue_send( queue_id, data, nbBytesToSend); |
@@ -228,12 +228,12 int action_enter_mode(ccsdsTelecommandPa | |||
|
228 | 228 | default: |
|
229 | 229 | break; |
|
230 | 230 | } |
|
231 | } | |
|
232 | 231 | |
|
233 | 232 | if (status != RTEMS_SUCCESSFUL) |
|
234 | 233 | { |
|
235 | 234 | status = LFR_EXE_ERROR; |
|
236 | 235 | } |
|
236 | } | |
|
237 | 237 | |
|
238 | 238 | return status; |
|
239 | 239 | } |
@@ -507,6 +507,8 int restart_asm_activities( unsigned cha | |||
|
507 | 507 | |
|
508 | 508 | status = stop_spectral_matrices(); |
|
509 | 509 | |
|
510 | thisIsAnASMRestart = 1; | |
|
511 | ||
|
510 | 512 | status = restart_asm_tasks( lfrRequestedMode ); |
|
511 | 513 | |
|
512 | 514 | launch_spectral_matrix(); |
@@ -530,7 +532,7 int stop_spectral_matrices( void ) | |||
|
530 | 532 | status = RTEMS_SUCCESSFUL; |
|
531 | 533 | |
|
532 | 534 | // (1) mask interruptions |
|
533 |
LEON_Mask_interrupt( IRQ_SPECTRAL_MATRIX ); // |
|
|
535 | LEON_Mask_interrupt( IRQ_SPECTRAL_MATRIX ); // mask spectral matrix interrupt | |
|
534 | 536 | |
|
535 | 537 | // (2) reset spectral matrices registers |
|
536 | 538 | set_sm_irq_onNewMatrix( 0 ); // stop the spectral matrices |
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