##// END OF EJS Templates
-O3 used for optimization...
paul -
r309:a80efd176164 R3_plus draft
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@@ -1,14 +1,14
1 1 cmake_minimum_required (VERSION 2.6)
2 2 project (LFR_FSW)
3 3
4 4 if(NOT CMAKE_BUILD_TYPE)
5 5 set(CMAKE_BUILD_TYPE "Release" CACHE STRING
6 6 "Choose the type of build, options are: Debug Release RelWithDebInfo MinSizeRel." FORCE)
7 7 endif(NOT CMAKE_BUILD_TYPE)
8 8
9 9 set(LFR_BP_SRC ${CMAKE_CURRENT_SOURCE_DIR}/LFR_basic-parameters/basic_parameters.c)
10 10
11 11 SET(CMAKE_MODULE_PATH ${CMAKE_MODULE_PATH} "${CMAKE_CURRENT_SOURCE_DIR}/sparc/")
12 12
13 13 add_subdirectory(src)
14 add_subdirectory(timegen)
14 #add_subdirectory(timegen)
@@ -1,221 +1,221
1 1 #ifndef GSCMEMORY_HPP_
2 2 #define GSCMEMORY_HPP_
3 3
4 4 #ifndef LEON3
5 5 #define LEON3
6 6 #endif
7 7
8 8 #define REGS_ADDR_PLUGANDPLAY 0xFFFFF000
9 9 #define ASR16_REG_ADDRESS 0x90400040 // Ancillary State Register 16 = Register protection control register (FT only)
10 10
11 11 #define DEVICEID_LEON3 0x003
12 12 #define DEVICEID_LEON3FT 0x053
13 13 #define VENDORID_GAISLER 0x01
14 14
15 15 // CCR
16 16 #define POS_FT 19
17 17 //
18 18 #define POS_ITE 12
19 19 #define COUNTER_FIELD_ITE 0x00003000 // 0000 0000 0000 0000 0011 0000 0000 0000
20 20 #define COUNTER_MASK_ITE 0xffffcfff // 1111 1111 1111 1111 1100 1111 1111 1111
21 21 #define POS_IDE 10
22 22 #define COUNTER_FIELD_IDE 0x00000c00 // 0000 0000 0000 0000 0000 1100 0000 0000
23 23 #define COUNTER_MASK_IDE 0xfffff3ff // 1111 1111 1111 1111 1111 0011 1111 1111
24 24 //
25 25 #define POS_DTE 8
26 26 #define COUNTER_FIELD_DTE 0x00000300 // 0000 0000 0000 0000 0000 0011 0000 0000
27 27 #define COUNTER_MASK_DTE 0xfffffcff // 1111 1111 1111 1111 1111 1100 1111 1111
28 28 #define POS_DDE 6
29 29 #define COUNTER_FIELD_DDE 0x000000c0 // 0000 0000 0000 0000 0000 0000 1100 0000
30 30 #define COUNTER_MASK_DDE 0xffffff3f // 1111 1111 1111 1111 1111 1111 0011 1111
31 31
32 32 // ASR16
33 33 #define POS_FPFTID 30
34 34 #define POS_FPRF 27
35 35 #define POS_FDI 16 // FP RF protection enable/disable
36 36 #define POS_IUFTID 14
37 37 #define POS_IURF 11
38 38 #define POS_IDI 0 // IU RF protection enable/disable
39 39
40 40 #define COUNTER_FIELD_FPRF 0x38000000 // 0011 1000 0000 0000 0000 0000 0000 0000
41 41 #define COUNTER_MASK_FPRF 0xc7ffffff // 1100 0111 1111 1111 1111 1111 1111 1111
42 42
43 43 #define COUNTER_FIELD_IURF 0x00003800 // 0000 0000 0000 0000 0011 1000 0000 0000
44 44 #define COUNTER_MASK_IURF 0xffffc7ff // 1111 1111 1111 1111 1100 0111 1111 1111
45 45
46 46 volatile unsigned int *asr16Ptr = (volatile unsigned int *) ASR16_REG_ADDRESS;
47 47
48 48 static inline void flushCache()
49 49 {
50 50 /**
51 51 * Flush the data cache and the instruction cache.
52 52 *
53 53 * @param void
54 54 *
55 55 * @return void
56 56 */
57 57
58 58 asm("flush");
59 59 }
60 60
61 61 //***************************
62 62 // CCR Cache control register
63 63
64 64 static unsigned int CCR_getValue()
65 65 {
66 66 unsigned int cacheControlRegister = 0;
67 67 __asm__ __volatile__("lda [%%g0] 2, %0" : "=r"(cacheControlRegister) : );
68 68 return cacheControlRegister;
69 69 }
70 70
71 71 static void CCR_setValue(unsigned int cacheControlRegister)
72 72 {
73 73 __asm__ __volatile__("sta %0, [%%g0] 2" : : "r"(cacheControlRegister));
74 74 }
75 75
76 76 static void CCR_resetCacheControlRegister()
77 77 {
78 78 unsigned int cacheControlRegister;
79 79 cacheControlRegister = 0x00;
80 80 CCR_setValue(cacheControlRegister);
81 81 }
82 82
83 83 static void CCR_enableInstructionCache()
84 84 {
85 85 // [1:0] Instruction Cache state (ICS)
86 86 // Indicates the current data cache state according to the following: X0 = disabled, 01 = frozen, 11 = enabled.
87 87 unsigned int cacheControlRegister;
88 88 cacheControlRegister = CCR_getValue();
89 89 cacheControlRegister = (cacheControlRegister | 0x3);
90 90 CCR_setValue(cacheControlRegister);
91 91 }
92 92
93 93 static void CCR_enableDataCache()
94 94 {
95 95 // [3:2] Data Cache state (DCS)
96 96 // Indicates the current data cache state according to the following: X0 = disabled, 01 = frozen, 11 = enabled.
97 97 unsigned int cacheControlRegister;
98 98 cacheControlRegister = CCR_getValue();
99 99 cacheControlRegister = (cacheControlRegister | 0xc);
100 100 CCR_setValue(cacheControlRegister);
101 101 }
102 102
103 103 static void CCR_enableInstructionBurstFetch()
104 104 {
105 105 // [16] Instruction burst fetch (IB). This bit enables burst fill during instruction fetch.
106 106 unsigned int cacheControlRegister;
107 107 cacheControlRegister = CCR_getValue();
108 108 // set the bit IB to 1
109 109 cacheControlRegister = (cacheControlRegister | 0x10000);
110 110 CCR_setValue(cacheControlRegister);
111 111 }
112 112
113 113 void CCR_getInstructionAndDataErrorCounters( unsigned int* instructionErrorCounter, unsigned int* dataErrorCounter )
114 114 {
115 115 // [13:12] Instruction Tag Errors (ITE) - Number of detected parity errors in the instruction tag cache.
116 116 // Only available if fault-tolerance is enabled (FT field in this register is non-zero).
117 117 // [11:10] Instruction Data Errors (IDE) - Number of detected parity errors in the instruction data cache.
118 118 // Only available if fault-tolerance is enabled (FT field in this register is non-zero).
119 119
120 120 unsigned int cacheControlRegister;
121 121 unsigned int iTE;
122 122 unsigned int iDE;
123 123 unsigned int dTE;
124 124 unsigned int dDE;
125 125
126 126 cacheControlRegister = CCR_getValue();
127 127 iTE = (cacheControlRegister & COUNTER_FIELD_ITE) >> POS_ITE;
128 128 iDE = (cacheControlRegister & COUNTER_FIELD_IDE) >> POS_IDE;
129 129 dTE = (cacheControlRegister & COUNTER_FIELD_DTE) >> POS_DTE;
130 130 dDE = (cacheControlRegister & COUNTER_FIELD_DDE) >> POS_DDE;
131 131
132 132 *instructionErrorCounter = iTE + iDE;
133 133 *dataErrorCounter = dTE + dDE;
134 134
135 135 // reset counters
136 136 cacheControlRegister = cacheControlRegister
137 137 & COUNTER_FIELD_ITE
138 138 & COUNTER_FIELD_IDE
139 139 & COUNTER_FIELD_DTE
140 140 & COUNTER_FIELD_DDE;
141 141
142 142 CCR_setValue(cacheControlRegister);
143 143 }
144 144
145 145 //*******************************************
146 146 // ASR16 Register protection control register
147 147
148 148 static void ASR16_resetRegisterProtectionControlRegister()
149 149 {
150 150 *asr16Ptr = 0x00;
151 151 }
152 152
153 153 void ASR16_get_FPRF_IURF_ErrorCounters( unsigned int* fprfErrorCounter, unsigned int* iurfErrorCounter)
154 154 {
155 155 /** This function is used to retrieve the integer unit register file error counter and the floating point unit
156 156 * register file error counter
157 157 *
158 158 * @return void
159 159 *
160 160 * [29:27] FP RF error counter - Number of detected parity errors in the FP register file.
161 161 * [13:11] IU RF error counter - Number of detected parity errors in the IU register file.
162 162 *
163 163 */
164 164
165 165 unsigned int asr16;
166 166
167 167 asr16 = *asr16Ptr;
168 168 *fprfErrorCounter = ( asr16 & COUNTER_FIELD_FPRF ) >> POS_FPRF;
169 169 *iurfErrorCounter = ( asr16 & COUNTER_FIELD_IURF ) >> POS_IURF;
170 170
171 171 // reset the counter to 0
172 172 asr16 = asr16
173 173 & COUNTER_MASK_FPRF
174 174 & COUNTER_FIELD_IURF;
175 175
176 176 *asr16Ptr = asr16;
177 177 }
178 178
179 179 static void faultTolerantScheme()
180 180 {
181 181 // [20:19] FT scheme (FT) - “00” = no FT, “01” = 4-bit checking implemented
182 182 unsigned int cacheControlRegister;
183 183 unsigned int *plugAndPlayRegister;
184 184 unsigned int vendorId;
185 185 unsigned int deviceId;
186 186
187 187 plugAndPlayRegister = (unsigned int*) REGS_ADDR_PLUGANDPLAY;
188 188 vendorId = ( (*plugAndPlayRegister) & 0xff000000 ) >> 24;
189 189 deviceId = ( (*plugAndPlayRegister) & 0x00fff000 ) >> 12;
190 190
191 191 cacheControlRegister = CCR_getValue();
192 192
193 193 if( (vendorId == VENDORID_GAISLER) & (deviceId ==DEVICEID_LEON3FT) )
194 194 {
195 195 PRINTF("in faultTolerantScheme *** Leon3FT detected\n");
196 196 PRINTF2(" *** vendorID = 0x%x, deviceId = 0x%x\n", vendorId, deviceId);
197 197 PRINTF1("ASR16 IU RF protection, bit 0 (IDI) is: 0x%x (0 => protection enabled)\n",
198 198 (*asr16Ptr >> POS_IDI) & 1);
199 199 PRINTF1("ASR16 FP RF protection, bit 16 (FDI) is: 0x%x (0 => protection enabled)\n",
200 200 (*asr16Ptr >> POS_FDI) & 1);
201 201 PRINTF1("ASR16 IU FT ID bits [15:14] is: 0x%x (2 => 8-bit parity without restart)\n",
202 202 (*asr16Ptr >> POS_IUFTID) & 0x3);
203 203 PRINTF1("ASR16 FP FT ID bits [31:30] is: 0x%x (1 => 4-bit parity with restart)\n",
204 204 (*asr16Ptr >> POS_FPFTID) & 0x03);
205 205 PRINTF1("CCR FT bits [20:19] are: 0x%x (1 => 4-bit parity with restart)\n",
206 206 (cacheControlRegister >> POS_FT) & 0x3 );
207 207
208 208 // CCR The FFT bits are just read, the FT scheme is set to “01” = 4-bit checking implemented by default
209 209
210 210 // ASR16 Ancillary State Register configuration (Register protection control register)
211 211 // IU RF protection is set by default, bit 0 IDI = 0
212 212 // FP RF protection is set by default, bit 16 FDI = 0
213 213 }
214 214 else
215 215 {
216 PRINTF("in faultTolerantScheme *** not a Leon3FT not detected\n");
216 PRINTF("in faultTolerantScheme *** Leon3FT not detected\n");
217 217 PRINTF2(" *** vendorID = 0x%x, deviceId = 0x%x\n", vendorId, deviceId);
218 218 }
219 219 }
220 220
221 221 #endif /* GSCMEMORY_HPP_ */
@@ -1,14 +1,14
1 1 # LOAD FSW USING LINK 1
2 2 SpwPlugin0.StarDundeeSelectLinkNumber( 1 )
3 3
4 dsu3plugin0.openFile("/home/pleroy/DEV/DEV_PLE/FSW-qt/bin/fsw")
4 dsu3plugin0.openFile("/home/pleroy/DEV/DEV_PLE/build-DEV_PLE-Desktop-Default/src/fsw")
5 5 #dsu3plugin0.openFile("/opt/LFR/LFR-FSW/2.0.2.3/fsw")
6 6 dsu3plugin0.loadFile()
7 7
8 8 dsu3plugin0.run()
9 9
10 10 # START SENDING TIMECODES AT 1 Hz
11 11 #SpwPlugin0.StarDundeeStartTimecodes( 1 )
12 12
13 13 # it is possible to change the time code frequency
14 14 #RMAPPlugin0.changeTimecodeFrequency(2)
@@ -1,8 +1,9
1 1 set(CMAKE_SYSTEM_NAME rtems)
2 2
3 3 set(CMAKE_C_COMPILER /opt/rtems-4.10/bin/sparc-rtems-gcc)
4 4 set(CMAKE_CXX_COMPILER /opt/rtems-4.10/bin/sparc-rtems-g++)
5 5 set(CMAKE_LINKER /opt/rtems-4.10/bin/sparc-rtems-g++)
6 6 SET(CMAKE_EXE_LINKER_FLAGS "-static")
7 set(CMAKE_C_FLAGS_RELEASE "-O3")
7 8 set(CMAKE_C_LINK_EXECUTABLE "<CMAKE_LINKER> <FLAGS> <CMAKE_CXX_LINK_FLAGS> <LINK_FLAGS> <OBJECTS> -o <TARGET> <LINK_LIBRARIES>")
8 9 include_directories("/opt/rtems-4.10/sparc-rtems/leon3/lib/include")
@@ -1,105 +1,105
1 1 cmake_minimum_required (VERSION 2.6)
2 project (FSW)
2 project (fsw)
3 3
4 4 include(sparc-rtems)
5 5
6 6 include_directories("../header"
7 7 "../header/lfr_common_headers"
8 8 "../header/processing"
9 9 "../LFR_basic-parameters"
10 10 "../src")
11 11
12 12 set(SOURCES wf_handler.c
13 13 tc_handler.c
14 14 fsw_misc.c
15 15 fsw_init.c
16 16 fsw_globals.c
17 17 fsw_spacewire.c
18 18 tc_load_dump_parameters.c
19 19 tm_lfr_tc_exe.c
20 20 tc_acceptance.c
21 21 processing/fsw_processing.c
22 22 processing/avf0_prc0.c
23 23 processing/avf1_prc1.c
24 24 processing/avf2_prc2.c
25 25 lfr_cpu_usage_report.c
26 26 ${LFR_BP_SRC}
27 27 ../header/wf_handler.h
28 28 ../header/tc_handler.h
29 29 ../header/grlib_regs.h
30 30 ../header/fsw_misc.h
31 31 ../header/fsw_init.h
32 32 ../header/fsw_spacewire.h
33 33 ../header/tc_load_dump_parameters.h
34 34 ../header/tm_lfr_tc_exe.h
35 35 ../header/tc_acceptance.h
36 36 ../header/processing/fsw_processing.h
37 37 ../header/processing/avf0_prc0.h
38 38 ../header/processing/avf1_prc1.h
39 39 ../header/processing/avf2_prc2.h
40 40 ../header/fsw_params_wf_handler.h
41 41 ../header/lfr_cpu_usage_report.h
42 42 ../header/lfr_common_headers/ccsds_types.h
43 43 ../header/lfr_common_headers/fsw_params.h
44 44 ../header/lfr_common_headers/fsw_params_nb_bytes.h
45 45 ../header/lfr_common_headers/fsw_params_processing.h
46 46 ../header/lfr_common_headers/tm_byte_positions.h
47 47 ../LFR_basic-parameters/basic_parameters.h
48 48 ../LFR_basic-parameters/basic_parameters_params.h
49 49 ../header/GscMemoryLPP.hpp
50 50 )
51 51
52 52
53 53 option(FSW_verbose "Enable verbose LFR" ON)
54 54 option(FSW_boot_messages "Enable LFR boot messages" ON)
55 55 option(FSW_debug_messages "Enable LFR debug messages" ON)
56 56 option(FSW_cpu_usage_report "Enable LFR cpu usage report" OFF)
57 57 option(FSW_stack_report "Enable LFR stack report" OFF)
58 58 option(FSW_vhdl_dev "?" OFF)
59 59 option(FSW_lpp_dpu_destid "Set to debug at LPP" ON)
60 60 option(FSW_debug_watchdog "Enable debug watchdog" OFF)
61 61 option(FSW_debug_tch "?" OFF)
62 62
63 63 set(SW_VERSION_N1 "3" CACHE STRING "Choose N1 FSW Version." FORCE)
64 64 set(SW_VERSION_N2 "1" CACHE STRING "Choose N2 FSW Version." FORCE)
65 65 set(SW_VERSION_N3 "0" CACHE STRING "Choose N3 FSW Version." FORCE)
66 66 set(SW_VERSION_N4 "4" CACHE STRING "Choose N4 FSW Version." FORCE)
67 67
68 68
69 69 if(FSW_verbose)
70 70 add_definitions(-DPRINT_MESSAGES_ON_CONSOLE)
71 71 endif()
72 72 if(FSW_boot_messages)
73 73 add_definitions(-DBOOT_MESSAGES)
74 74 endif()
75 75 if(FSW_debug_messages)
76 76 add_definitions(-DDEBUG_MESSAGES)
77 77 endif()
78 78 if(FSW_cpu_usage_report)
79 79 add_definitions(-DPRINT_TASK_STATISTICS)
80 80 endif()
81 81 if(FSW_stack_report)
82 82 add_definitions(-DPRINT_STACK_REPORT)
83 83 endif()
84 84 if(FSW_vhdl_dev)
85 85 add_definitions(-DVHDL_DEV)
86 86 endif()
87 87 if(FSW_lpp_dpu_destid)
88 88 add_definitions(-DLPP_DPU_DESTID)
89 89 endif()
90 90 if(FSW_debug_watchdog)
91 91 add_definitions(-DDEBUG_WATCHDOG)
92 92 endif()
93 93 if(FSW_debug_tch)
94 94 add_definitions(-DDEBUG_TCH)
95 95 endif()
96 96
97 97 add_definitions(-DMSB_FIRST_TCH)
98 98
99 99 add_definitions(-DSWVERSION=-1-0)
100 100 add_definitions(-DSW_VERSION_N1=${SW_VERSION_N1})
101 101 add_definitions(-DSW_VERSION_N2=${SW_VERSION_N2})
102 102 add_definitions(-DSW_VERSION_N3=${SW_VERSION_N3})
103 103 add_definitions(-DSW_VERSION_N4=${SW_VERSION_N4})
104 104
105 add_executable(FSW ${SOURCES})
105 add_executable(fsw ${SOURCES})
@@ -1,939 +1,938
1 1 /** This is the RTEMS initialization module.
2 2 *
3 3 * @file
4 4 * @author P. LEROY
5 5 *
6 6 * This module contains two very different information:
7 7 * - specific instructions to configure the compilation of the RTEMS executive
8 8 * - functions related to the fligth softwre initialization, especially the INIT RTEMS task
9 9 *
10 10 */
11 11
12 12 //*************************
13 13 // GPL reminder to be added
14 14 //*************************
15 15
16 16 #include <rtems.h>
17 17
18 18 /* configuration information */
19 19
20 20 #define CONFIGURE_INIT
21 21
22 22 #include <bsp.h> /* for device driver prototypes */
23 23
24 24 /* configuration information */
25 25
26 26 #define CONFIGURE_APPLICATION_NEEDS_CONSOLE_DRIVER
27 27 #define CONFIGURE_APPLICATION_NEEDS_CLOCK_DRIVER
28 28
29 29 #define CONFIGURE_MAXIMUM_TASKS 20
30 30 #define CONFIGURE_RTEMS_INIT_TASKS_TABLE
31 31 #define CONFIGURE_EXTRA_TASK_STACKS (3 * RTEMS_MINIMUM_STACK_SIZE)
32 32 #define CONFIGURE_LIBIO_MAXIMUM_FILE_DESCRIPTORS 32
33 33 #define CONFIGURE_INIT_TASK_PRIORITY 1 // instead of 100
34 34 #define CONFIGURE_INIT_TASK_MODE (RTEMS_DEFAULT_MODES | RTEMS_NO_PREEMPT)
35 35 #define CONFIGURE_INIT_TASK_ATTRIBUTES (RTEMS_DEFAULT_ATTRIBUTES | RTEMS_FLOATING_POINT)
36 36 #define CONFIGURE_MAXIMUM_DRIVERS 16
37 37 #define CONFIGURE_MAXIMUM_PERIODS 5
38 38 #define CONFIGURE_MAXIMUM_TIMERS 5 // [spiq] [link] [spacewire_reset_link]
39 39 #define CONFIGURE_MAXIMUM_MESSAGE_QUEUES 5
40 40 #ifdef PRINT_STACK_REPORT
41 41 #define CONFIGURE_STACK_CHECKER_ENABLED
42 42 #endif
43 43
44 44 #include <rtems/confdefs.h>
45 45
46 46 /* If --drvmgr was enabled during the configuration of the RTEMS kernel */
47 47 #ifdef RTEMS_DRVMGR_STARTUP
48 48 #ifdef LEON3
49 49 /* Add Timer and UART Driver */
50 50
51 51 #ifdef CONFIGURE_APPLICATION_NEEDS_CLOCK_DRIVER
52 52 #define CONFIGURE_DRIVER_AMBAPP_GAISLER_GPTIMER
53 53 #endif
54 54
55 55 #ifdef CONFIGURE_APPLICATION_NEEDS_CONSOLE_DRIVER
56 56 #define CONFIGURE_DRIVER_AMBAPP_GAISLER_APBUART
57 57 #endif
58 58
59 59 #endif
60 60 #define CONFIGURE_DRIVER_AMBAPP_GAISLER_GRSPW /* GRSPW Driver */
61 61
62 62 #include <drvmgr/drvmgr_confdefs.h>
63 63 #endif
64 64
65 65 #include "fsw_init.h"
66 66 #include "fsw_config.c"
67 67 #include "GscMemoryLPP.hpp"
68 68
69 69 void initCache()
70 70 {
71 71 // ASI 2 contains a few control registers that have not been assigned as ancillary state registers.
72 72 // These should only be read and written using 32-bit LDA/STA instructions.
73 73 // All cache registers are accessed through load/store operations to the alternate address space (LDA/STA), using ASI = 2.
74 74 // The table below shows the register addresses:
75 75 // 0x00 Cache control register
76 76 // 0x04 Reserved
77 77 // 0x08 Instruction cache configuration register
78 78 // 0x0C Data cache configuration register
79 79
80 80 // Cache Control Register Leon3 / Leon3FT
81 81 // 31..30 29 28 27..24 23 22 21 20..19 18 17 16
82 82 // RFT PS TB DS FD FI FT ST IB
83 83 // 15 14 13..12 11..10 9..8 7..6 5 4 3..2 1..0
84 84 // IP DP ITE IDE DTE DDE DF IF DCS ICS
85 85
86 86 unsigned int cacheControlRegister;
87 87
88 88 CCR_resetCacheControlRegister();
89 89 ASR16_resetRegisterProtectionControlRegister();
90 90
91 91 cacheControlRegister = CCR_getValue();
92 92 PRINTF1("(0) CCR - Cache Control Register = %x\n", cacheControlRegister);
93 93 PRINTF1("(0) ASR16 = %x\n", *asr16Ptr);
94 94
95 95 CCR_enableInstructionCache(); // ICS bits
96 96 CCR_enableDataCache(); // DCS bits
97 97 CCR_enableInstructionBurstFetch(); // IB bit
98 98
99 99 faultTolerantScheme();
100 100
101 101 cacheControlRegister = CCR_getValue();
102 102 PRINTF1("(1) CCR - Cache Control Register = %x\n", cacheControlRegister);
103 103 PRINTF1("(1) ASR16 Register protection control register = %x\n", *asr16Ptr);
104 104
105 105 PRINTF("\n");
106 106 }
107 107
108 108 rtems_task Init( rtems_task_argument ignored )
109 109 {
110 110 /** This is the RTEMS INIT taks, it is the first task launched by the system.
111 111 *
112 112 * @param unused is the starting argument of the RTEMS task
113 113 *
114 114 * The INIT task create and run all other RTEMS tasks.
115 115 *
116 116 */
117 117
118 118 //***********
119 119 // INIT CACHE
120 120
121 121 unsigned char *vhdlVersion;
122 122
123 123 reset_lfr();
124 124
125 125 reset_local_time();
126 126
127 127 rtems_cpu_usage_reset();
128 128
129 129 rtems_status_code status;
130 130 rtems_status_code status_spw;
131 131 rtems_isr_entry old_isr_handler;
132 132
133 133 // UART settings
134 134 enable_apbuart_transmitter();
135 135 set_apbuart_scaler_reload_register(REGS_ADDR_APBUART, APBUART_SCALER_RELOAD_VALUE);
136 136
137 137 DEBUG_PRINTF("\n\n\n\n\nIn INIT *** Now the console is on port COM1\n")
138 138
139 139
140 140 PRINTF("\n\n\n\n\n")
141 141
142 142 initCache();
143 143
144 144 PRINTF("*************************\n")
145 145 PRINTF("** LFR Flight Software **\n")
146 146
147 147 PRINTF1("** %d-", SW_VERSION_N1)
148 148 PRINTF1("%d-" , SW_VERSION_N2)
149 149 PRINTF1("%d-" , SW_VERSION_N3)
150 150 PRINTF1("%d **\n", SW_VERSION_N4)
151 151
152 152 vhdlVersion = (unsigned char *) (REGS_ADDR_VHDL_VERSION);
153 153 PRINTF("** VHDL **\n")
154 154 PRINTF1("** %d.", vhdlVersion[1])
155 155 PRINTF1("%d." , vhdlVersion[2])
156 156 PRINTF1("%d **\n", vhdlVersion[3])
157 157 PRINTF("*************************\n")
158 158 PRINTF("\n\n")
159 159
160 160 init_parameter_dump();
161 161 init_kcoefficients_dump();
162 162 init_local_mode_parameters();
163 163 init_housekeeping_parameters();
164 164 init_k_coefficients_prc0();
165 165 init_k_coefficients_prc1();
166 166 init_k_coefficients_prc2();
167 167 pa_bia_status_info = 0x00;
168 168 cp_rpw_sc_rw_f_flags = 0x00;
169 169 cp_rpw_sc_rw1_f1 = 0.0;
170 170 cp_rpw_sc_rw1_f2 = 0.0;
171 171 cp_rpw_sc_rw2_f1 = 0.0;
172 172 cp_rpw_sc_rw2_f2 = 0.0;
173 173 cp_rpw_sc_rw3_f1 = 0.0;
174 174 cp_rpw_sc_rw3_f2 = 0.0;
175 175 cp_rpw_sc_rw4_f1 = 0.0;
176 176 cp_rpw_sc_rw4_f2 = 0.0;
177 177 // initialize filtering parameters
178 178 filterPar.spare_sy_lfr_pas_filter_enabled = DEFAULT_SY_LFR_PAS_FILTER_ENABLED;
179 179 filterPar.sy_lfr_pas_filter_modulus = DEFAULT_SY_LFR_PAS_FILTER_MODULUS;
180 180 filterPar.sy_lfr_pas_filter_tbad = DEFAULT_SY_LFR_PAS_FILTER_TBAD;
181 181 filterPar.sy_lfr_pas_filter_offset = DEFAULT_SY_LFR_PAS_FILTER_OFFSET;
182 182 filterPar.sy_lfr_pas_filter_shift = DEFAULT_SY_LFR_PAS_FILTER_SHIFT;
183 183 filterPar.sy_lfr_sc_rw_delta_f = DEFAULT_SY_LFR_SC_RW_DELTA_F;
184 184 update_last_valid_transition_date( DEFAULT_LAST_VALID_TRANSITION_DATE );
185 185
186 186 // waveform picker initialization
187 187 WFP_init_rings();
188 188 LEON_Clear_interrupt( IRQ_SPARC_GPTIMER_WATCHDOG ); // initialize the waveform rings
189 189 WFP_reset_current_ring_nodes();
190 190 reset_waveform_picker_regs();
191 191
192 192 // spectral matrices initialization
193 193 SM_init_rings(); // initialize spectral matrices rings
194 194 SM_reset_current_ring_nodes();
195 195 reset_spectral_matrix_regs();
196 196
197 197 // configure calibration
198 198 configureCalibration( false ); // true means interleaved mode, false is for normal mode
199 199
200 200 updateLFRCurrentMode( LFR_MODE_STANDBY );
201 201
202 202 BOOT_PRINTF1("in INIT *** lfrCurrentMode is %d\n", lfrCurrentMode)
203 203
204 204 create_names(); // create all names
205 205
206 206 status = create_timecode_timer(); // create the timer used by timecode_irq_handler
207 207 if (status != RTEMS_SUCCESSFUL)
208 208 {
209 209 PRINTF1("in INIT *** ERR in create_timer_timecode, code %d", status)
210 210 }
211 211
212 212 status = create_message_queues(); // create message queues
213 213 if (status != RTEMS_SUCCESSFUL)
214 214 {
215 215 PRINTF1("in INIT *** ERR in create_message_queues, code %d", status)
216 216 }
217 217
218 218 status = create_all_tasks(); // create all tasks
219 219 if (status != RTEMS_SUCCESSFUL)
220 220 {
221 221 PRINTF1("in INIT *** ERR in create_all_tasks, code %d\n", status)
222 222 }
223 223
224 224 // **************************
225 225 // <SPACEWIRE INITIALIZATION>
226 226 status_spw = spacewire_open_link(); // (1) open the link
227 227 if ( status_spw != RTEMS_SUCCESSFUL )
228 228 {
229 229 PRINTF1("in INIT *** ERR spacewire_open_link code %d\n", status_spw )
230 230 }
231 231
232 232 if ( status_spw == RTEMS_SUCCESSFUL ) // (2) configure the link
233 233 {
234 234 status_spw = spacewire_configure_link( fdSPW );
235 235 if ( status_spw != RTEMS_SUCCESSFUL )
236 236 {
237 237 PRINTF1("in INIT *** ERR spacewire_configure_link code %d\n", status_spw )
238 238 }
239 239 }
240 240
241 241 if ( status_spw == RTEMS_SUCCESSFUL) // (3) start the link
242 242 {
243 243 status_spw = spacewire_start_link( fdSPW );
244 244 if ( status_spw != RTEMS_SUCCESSFUL )
245 245 {
246 246 PRINTF1("in INIT *** ERR spacewire_start_link code %d\n", status_spw )
247 247 }
248 248 }
249 249 // </SPACEWIRE INITIALIZATION>
250 250 // ***************************
251 251
252 252 status = start_all_tasks(); // start all tasks
253 253 if (status != RTEMS_SUCCESSFUL)
254 254 {
255 255 PRINTF1("in INIT *** ERR in start_all_tasks, code %d", status)
256 256 }
257 257
258 258 // start RECV and SEND *AFTER* SpaceWire Initialization, due to the timeout of the start call during the initialization
259 259 status = start_recv_send_tasks();
260 260 if ( status != RTEMS_SUCCESSFUL )
261 261 {
262 262 PRINTF1("in INIT *** ERR start_recv_send_tasks code %d\n", status )
263 263 }
264 264
265 265 // suspend science tasks, they will be restarted later depending on the mode
266 266 status = suspend_science_tasks(); // suspend science tasks (not done in stop_current_mode if current mode = STANDBY)
267 267 if (status != RTEMS_SUCCESSFUL)
268 268 {
269 269 PRINTF1("in INIT *** in suspend_science_tasks *** ERR code: %d\n", status)
270 270 }
271 271
272 272 // configure IRQ handling for the waveform picker unit
273 273 status = rtems_interrupt_catch( waveforms_isr,
274 274 IRQ_SPARC_WAVEFORM_PICKER,
275 275 &old_isr_handler) ;
276 276 // configure IRQ handling for the spectral matrices unit
277 277 status = rtems_interrupt_catch( spectral_matrices_isr,
278 278 IRQ_SPARC_SPECTRAL_MATRIX,
279 279 &old_isr_handler) ;
280 280
281 281 // if the spacewire link is not up then send an event to the SPIQ task for link recovery
282 282 if ( status_spw != RTEMS_SUCCESSFUL )
283 283 {
284 284 status = rtems_event_send( Task_id[TASKID_SPIQ], SPW_LINKERR_EVENT );
285 285 if ( status != RTEMS_SUCCESSFUL ) {
286 286 PRINTF1("in INIT *** ERR rtems_event_send to SPIQ code %d\n", status )
287 287 }
288 288 }
289 289
290 290 BOOT_PRINTF("delete INIT\n")
291 291
292 292 set_hk_lfr_sc_potential_flag( true );
293 293
294 294 // start the timer to detect a missing spacewire timecode
295 295 // the timeout is larger because the spw IP needs to receive several valid timecodes before generating a tickout
296 296 // if a tickout is generated, the timer is restarted
297 297 status = rtems_timer_fire_after( timecode_timer_id, TIMECODE_TIMER_TIMEOUT_INIT, timecode_timer_routine, NULL );
298 298
299 299 grspw_timecode_callback = &timecode_irq_handler;
300 300
301 301 status = rtems_task_delete(RTEMS_SELF);
302 302
303 303 }
304 304
305 305 void init_local_mode_parameters( void )
306 306 {
307 307 /** This function initialize the param_local global variable with default values.
308 308 *
309 309 */
310 310
311 311 unsigned int i;
312 312
313 313 // LOCAL PARAMETERS
314 314
315 315 BOOT_PRINTF1("local_sbm1_nb_cwf_max %d \n", param_local.local_sbm1_nb_cwf_max)
316 316 BOOT_PRINTF1("local_sbm2_nb_cwf_max %d \n", param_local.local_sbm2_nb_cwf_max)
317 BOOT_PRINTF1("nb_interrupt_f0_MAX = %d\n", param_local.local_nb_interrupt_f0_MAX)
318 317
319 318 // init sequence counters
320 319
321 320 for(i = 0; i<SEQ_CNT_NB_DEST_ID; i++)
322 321 {
323 322 sequenceCounters_TC_EXE[i] = 0x00;
324 323 sequenceCounters_TM_DUMP[i] = 0x00;
325 324 }
326 325 sequenceCounters_SCIENCE_NORMAL_BURST = 0x00;
327 326 sequenceCounters_SCIENCE_SBM1_SBM2 = 0x00;
328 327 sequenceCounterHK = TM_PACKET_SEQ_CTRL_STANDALONE << 8;
329 328 }
330 329
331 330 void reset_local_time( void )
332 331 {
333 332 time_management_regs->ctrl = time_management_regs->ctrl | 0x02; // [0010] software reset, coarse time = 0x80000000
334 333 }
335 334
336 335 void create_names( void ) // create all names for tasks and queues
337 336 {
338 337 /** This function creates all RTEMS names used in the software for tasks and queues.
339 338 *
340 339 * @return RTEMS directive status codes:
341 340 * - RTEMS_SUCCESSFUL - successful completion
342 341 *
343 342 */
344 343
345 344 // task names
346 345 Task_name[TASKID_RECV] = rtems_build_name( 'R', 'E', 'C', 'V' );
347 346 Task_name[TASKID_ACTN] = rtems_build_name( 'A', 'C', 'T', 'N' );
348 347 Task_name[TASKID_SPIQ] = rtems_build_name( 'S', 'P', 'I', 'Q' );
349 348 Task_name[TASKID_LOAD] = rtems_build_name( 'L', 'O', 'A', 'D' );
350 349 Task_name[TASKID_AVF0] = rtems_build_name( 'A', 'V', 'F', '0' );
351 350 Task_name[TASKID_SWBD] = rtems_build_name( 'S', 'W', 'B', 'D' );
352 351 Task_name[TASKID_WFRM] = rtems_build_name( 'W', 'F', 'R', 'M' );
353 352 Task_name[TASKID_DUMB] = rtems_build_name( 'D', 'U', 'M', 'B' );
354 353 Task_name[TASKID_HOUS] = rtems_build_name( 'H', 'O', 'U', 'S' );
355 354 Task_name[TASKID_PRC0] = rtems_build_name( 'P', 'R', 'C', '0' );
356 355 Task_name[TASKID_CWF3] = rtems_build_name( 'C', 'W', 'F', '3' );
357 356 Task_name[TASKID_CWF2] = rtems_build_name( 'C', 'W', 'F', '2' );
358 357 Task_name[TASKID_CWF1] = rtems_build_name( 'C', 'W', 'F', '1' );
359 358 Task_name[TASKID_SEND] = rtems_build_name( 'S', 'E', 'N', 'D' );
360 359 Task_name[TASKID_LINK] = rtems_build_name( 'L', 'I', 'N', 'K' );
361 360 Task_name[TASKID_AVF1] = rtems_build_name( 'A', 'V', 'F', '1' );
362 361 Task_name[TASKID_PRC1] = rtems_build_name( 'P', 'R', 'C', '1' );
363 362 Task_name[TASKID_AVF2] = rtems_build_name( 'A', 'V', 'F', '2' );
364 363 Task_name[TASKID_PRC2] = rtems_build_name( 'P', 'R', 'C', '2' );
365 364
366 365 // rate monotonic period names
367 366 name_hk_rate_monotonic = rtems_build_name( 'H', 'O', 'U', 'S' );
368 367
369 368 misc_name[QUEUE_RECV] = rtems_build_name( 'Q', '_', 'R', 'V' );
370 369 misc_name[QUEUE_SEND] = rtems_build_name( 'Q', '_', 'S', 'D' );
371 370 misc_name[QUEUE_PRC0] = rtems_build_name( 'Q', '_', 'P', '0' );
372 371 misc_name[QUEUE_PRC1] = rtems_build_name( 'Q', '_', 'P', '1' );
373 372 misc_name[QUEUE_PRC2] = rtems_build_name( 'Q', '_', 'P', '2' );
374 373
375 374 timecode_timer_name = rtems_build_name( 'S', 'P', 'T', 'C' );
376 375 }
377 376
378 377 int create_all_tasks( void ) // create all tasks which run in the software
379 378 {
380 379 /** This function creates all RTEMS tasks used in the software.
381 380 *
382 381 * @return RTEMS directive status codes:
383 382 * - RTEMS_SUCCESSFUL - task created successfully
384 383 * - RTEMS_INVALID_ADDRESS - id is NULL
385 384 * - RTEMS_INVALID_NAME - invalid task name
386 385 * - RTEMS_INVALID_PRIORITY - invalid task priority
387 386 * - RTEMS_MP_NOT_CONFIGURED - multiprocessing not configured
388 387 * - RTEMS_TOO_MANY - too many tasks created
389 388 * - RTEMS_UNSATISFIED - not enough memory for stack/FP context
390 389 * - RTEMS_TOO_MANY - too many global objects
391 390 *
392 391 */
393 392
394 393 rtems_status_code status;
395 394
396 395 //**********
397 396 // SPACEWIRE
398 397 // RECV
399 398 status = rtems_task_create(
400 399 Task_name[TASKID_RECV], TASK_PRIORITY_RECV, RTEMS_MINIMUM_STACK_SIZE,
401 400 RTEMS_DEFAULT_MODES,
402 401 RTEMS_DEFAULT_ATTRIBUTES, &Task_id[TASKID_RECV]
403 402 );
404 403 if (status == RTEMS_SUCCESSFUL) // SEND
405 404 {
406 405 status = rtems_task_create(
407 406 Task_name[TASKID_SEND], TASK_PRIORITY_SEND, RTEMS_MINIMUM_STACK_SIZE * 2,
408 407 RTEMS_DEFAULT_MODES,
409 408 RTEMS_DEFAULT_ATTRIBUTES | RTEMS_FLOATING_POINT, &Task_id[TASKID_SEND]
410 409 );
411 410 }
412 411 if (status == RTEMS_SUCCESSFUL) // LINK
413 412 {
414 413 status = rtems_task_create(
415 414 Task_name[TASKID_LINK], TASK_PRIORITY_LINK, RTEMS_MINIMUM_STACK_SIZE,
416 415 RTEMS_DEFAULT_MODES,
417 416 RTEMS_DEFAULT_ATTRIBUTES, &Task_id[TASKID_LINK]
418 417 );
419 418 }
420 419 if (status == RTEMS_SUCCESSFUL) // ACTN
421 420 {
422 421 status = rtems_task_create(
423 422 Task_name[TASKID_ACTN], TASK_PRIORITY_ACTN, RTEMS_MINIMUM_STACK_SIZE,
424 423 RTEMS_DEFAULT_MODES | RTEMS_NO_PREEMPT,
425 424 RTEMS_DEFAULT_ATTRIBUTES | RTEMS_FLOATING_POINT, &Task_id[TASKID_ACTN]
426 425 );
427 426 }
428 427 if (status == RTEMS_SUCCESSFUL) // SPIQ
429 428 {
430 429 status = rtems_task_create(
431 430 Task_name[TASKID_SPIQ], TASK_PRIORITY_SPIQ, RTEMS_MINIMUM_STACK_SIZE,
432 431 RTEMS_DEFAULT_MODES | RTEMS_NO_PREEMPT,
433 432 RTEMS_DEFAULT_ATTRIBUTES, &Task_id[TASKID_SPIQ]
434 433 );
435 434 }
436 435
437 436 //******************
438 437 // SPECTRAL MATRICES
439 438 if (status == RTEMS_SUCCESSFUL) // AVF0
440 439 {
441 440 status = rtems_task_create(
442 441 Task_name[TASKID_AVF0], TASK_PRIORITY_AVF0, RTEMS_MINIMUM_STACK_SIZE,
443 442 RTEMS_DEFAULT_MODES,
444 443 RTEMS_DEFAULT_ATTRIBUTES | RTEMS_FLOATING_POINT, &Task_id[TASKID_AVF0]
445 444 );
446 445 }
447 446 if (status == RTEMS_SUCCESSFUL) // PRC0
448 447 {
449 448 status = rtems_task_create(
450 449 Task_name[TASKID_PRC0], TASK_PRIORITY_PRC0, RTEMS_MINIMUM_STACK_SIZE * 2,
451 450 RTEMS_DEFAULT_MODES | RTEMS_NO_PREEMPT,
452 451 RTEMS_DEFAULT_ATTRIBUTES | RTEMS_FLOATING_POINT, &Task_id[TASKID_PRC0]
453 452 );
454 453 }
455 454 if (status == RTEMS_SUCCESSFUL) // AVF1
456 455 {
457 456 status = rtems_task_create(
458 457 Task_name[TASKID_AVF1], TASK_PRIORITY_AVF1, RTEMS_MINIMUM_STACK_SIZE,
459 458 RTEMS_DEFAULT_MODES,
460 459 RTEMS_DEFAULT_ATTRIBUTES | RTEMS_FLOATING_POINT, &Task_id[TASKID_AVF1]
461 460 );
462 461 }
463 462 if (status == RTEMS_SUCCESSFUL) // PRC1
464 463 {
465 464 status = rtems_task_create(
466 465 Task_name[TASKID_PRC1], TASK_PRIORITY_PRC1, RTEMS_MINIMUM_STACK_SIZE * 2,
467 466 RTEMS_DEFAULT_MODES | RTEMS_NO_PREEMPT,
468 467 RTEMS_DEFAULT_ATTRIBUTES | RTEMS_FLOATING_POINT, &Task_id[TASKID_PRC1]
469 468 );
470 469 }
471 470 if (status == RTEMS_SUCCESSFUL) // AVF2
472 471 {
473 472 status = rtems_task_create(
474 473 Task_name[TASKID_AVF2], TASK_PRIORITY_AVF2, RTEMS_MINIMUM_STACK_SIZE,
475 474 RTEMS_DEFAULT_MODES,
476 475 RTEMS_DEFAULT_ATTRIBUTES | RTEMS_FLOATING_POINT, &Task_id[TASKID_AVF2]
477 476 );
478 477 }
479 478 if (status == RTEMS_SUCCESSFUL) // PRC2
480 479 {
481 480 status = rtems_task_create(
482 481 Task_name[TASKID_PRC2], TASK_PRIORITY_PRC2, RTEMS_MINIMUM_STACK_SIZE * 2,
483 482 RTEMS_DEFAULT_MODES | RTEMS_NO_PREEMPT,
484 483 RTEMS_DEFAULT_ATTRIBUTES | RTEMS_FLOATING_POINT, &Task_id[TASKID_PRC2]
485 484 );
486 485 }
487 486
488 487 //****************
489 488 // WAVEFORM PICKER
490 489 if (status == RTEMS_SUCCESSFUL) // WFRM
491 490 {
492 491 status = rtems_task_create(
493 492 Task_name[TASKID_WFRM], TASK_PRIORITY_WFRM, RTEMS_MINIMUM_STACK_SIZE,
494 493 RTEMS_DEFAULT_MODES,
495 494 RTEMS_DEFAULT_ATTRIBUTES | RTEMS_FLOATING_POINT, &Task_id[TASKID_WFRM]
496 495 );
497 496 }
498 497 if (status == RTEMS_SUCCESSFUL) // CWF3
499 498 {
500 499 status = rtems_task_create(
501 500 Task_name[TASKID_CWF3], TASK_PRIORITY_CWF3, RTEMS_MINIMUM_STACK_SIZE,
502 501 RTEMS_DEFAULT_MODES,
503 502 RTEMS_DEFAULT_ATTRIBUTES | RTEMS_FLOATING_POINT, &Task_id[TASKID_CWF3]
504 503 );
505 504 }
506 505 if (status == RTEMS_SUCCESSFUL) // CWF2
507 506 {
508 507 status = rtems_task_create(
509 508 Task_name[TASKID_CWF2], TASK_PRIORITY_CWF2, RTEMS_MINIMUM_STACK_SIZE,
510 509 RTEMS_DEFAULT_MODES,
511 510 RTEMS_DEFAULT_ATTRIBUTES | RTEMS_FLOATING_POINT, &Task_id[TASKID_CWF2]
512 511 );
513 512 }
514 513 if (status == RTEMS_SUCCESSFUL) // CWF1
515 514 {
516 515 status = rtems_task_create(
517 516 Task_name[TASKID_CWF1], TASK_PRIORITY_CWF1, RTEMS_MINIMUM_STACK_SIZE,
518 517 RTEMS_DEFAULT_MODES,
519 518 RTEMS_DEFAULT_ATTRIBUTES | RTEMS_FLOATING_POINT, &Task_id[TASKID_CWF1]
520 519 );
521 520 }
522 521 if (status == RTEMS_SUCCESSFUL) // SWBD
523 522 {
524 523 status = rtems_task_create(
525 524 Task_name[TASKID_SWBD], TASK_PRIORITY_SWBD, RTEMS_MINIMUM_STACK_SIZE,
526 525 RTEMS_DEFAULT_MODES,
527 526 RTEMS_DEFAULT_ATTRIBUTES | RTEMS_FLOATING_POINT, &Task_id[TASKID_SWBD]
528 527 );
529 528 }
530 529
531 530 //*****
532 531 // MISC
533 532 if (status == RTEMS_SUCCESSFUL) // LOAD
534 533 {
535 534 status = rtems_task_create(
536 535 Task_name[TASKID_LOAD], TASK_PRIORITY_LOAD, RTEMS_MINIMUM_STACK_SIZE,
537 536 RTEMS_DEFAULT_MODES,
538 537 RTEMS_DEFAULT_ATTRIBUTES, &Task_id[TASKID_LOAD]
539 538 );
540 539 }
541 540 if (status == RTEMS_SUCCESSFUL) // DUMB
542 541 {
543 542 status = rtems_task_create(
544 543 Task_name[TASKID_DUMB], TASK_PRIORITY_DUMB, RTEMS_MINIMUM_STACK_SIZE,
545 544 RTEMS_DEFAULT_MODES,
546 545 RTEMS_DEFAULT_ATTRIBUTES, &Task_id[TASKID_DUMB]
547