##// END OF EJS Templates
-O3 used for optimization...
paul -
r309:a80efd176164 R3_plus draft
parent child
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@@ -1,14 +1,14
1 cmake_minimum_required (VERSION 2.6)
1 cmake_minimum_required (VERSION 2.6)
2 project (LFR_FSW)
2 project (LFR_FSW)
3
3
4 if(NOT CMAKE_BUILD_TYPE)
4 if(NOT CMAKE_BUILD_TYPE)
5 set(CMAKE_BUILD_TYPE "Release" CACHE STRING
5 set(CMAKE_BUILD_TYPE "Release" CACHE STRING
6 "Choose the type of build, options are: Debug Release RelWithDebInfo MinSizeRel." FORCE)
6 "Choose the type of build, options are: Debug Release RelWithDebInfo MinSizeRel." FORCE)
7 endif(NOT CMAKE_BUILD_TYPE)
7 endif(NOT CMAKE_BUILD_TYPE)
8
8
9 set(LFR_BP_SRC ${CMAKE_CURRENT_SOURCE_DIR}/LFR_basic-parameters/basic_parameters.c)
9 set(LFR_BP_SRC ${CMAKE_CURRENT_SOURCE_DIR}/LFR_basic-parameters/basic_parameters.c)
10
10
11 SET(CMAKE_MODULE_PATH ${CMAKE_MODULE_PATH} "${CMAKE_CURRENT_SOURCE_DIR}/sparc/")
11 SET(CMAKE_MODULE_PATH ${CMAKE_MODULE_PATH} "${CMAKE_CURRENT_SOURCE_DIR}/sparc/")
12
12
13 add_subdirectory(src)
13 add_subdirectory(src)
14 add_subdirectory(timegen)
14 #add_subdirectory(timegen)
@@ -1,221 +1,221
1 #ifndef GSCMEMORY_HPP_
1 #ifndef GSCMEMORY_HPP_
2 #define GSCMEMORY_HPP_
2 #define GSCMEMORY_HPP_
3
3
4 #ifndef LEON3
4 #ifndef LEON3
5 #define LEON3
5 #define LEON3
6 #endif
6 #endif
7
7
8 #define REGS_ADDR_PLUGANDPLAY 0xFFFFF000
8 #define REGS_ADDR_PLUGANDPLAY 0xFFFFF000
9 #define ASR16_REG_ADDRESS 0x90400040 // Ancillary State Register 16 = Register protection control register (FT only)
9 #define ASR16_REG_ADDRESS 0x90400040 // Ancillary State Register 16 = Register protection control register (FT only)
10
10
11 #define DEVICEID_LEON3 0x003
11 #define DEVICEID_LEON3 0x003
12 #define DEVICEID_LEON3FT 0x053
12 #define DEVICEID_LEON3FT 0x053
13 #define VENDORID_GAISLER 0x01
13 #define VENDORID_GAISLER 0x01
14
14
15 // CCR
15 // CCR
16 #define POS_FT 19
16 #define POS_FT 19
17 //
17 //
18 #define POS_ITE 12
18 #define POS_ITE 12
19 #define COUNTER_FIELD_ITE 0x00003000 // 0000 0000 0000 0000 0011 0000 0000 0000
19 #define COUNTER_FIELD_ITE 0x00003000 // 0000 0000 0000 0000 0011 0000 0000 0000
20 #define COUNTER_MASK_ITE 0xffffcfff // 1111 1111 1111 1111 1100 1111 1111 1111
20 #define COUNTER_MASK_ITE 0xffffcfff // 1111 1111 1111 1111 1100 1111 1111 1111
21 #define POS_IDE 10
21 #define POS_IDE 10
22 #define COUNTER_FIELD_IDE 0x00000c00 // 0000 0000 0000 0000 0000 1100 0000 0000
22 #define COUNTER_FIELD_IDE 0x00000c00 // 0000 0000 0000 0000 0000 1100 0000 0000
23 #define COUNTER_MASK_IDE 0xfffff3ff // 1111 1111 1111 1111 1111 0011 1111 1111
23 #define COUNTER_MASK_IDE 0xfffff3ff // 1111 1111 1111 1111 1111 0011 1111 1111
24 //
24 //
25 #define POS_DTE 8
25 #define POS_DTE 8
26 #define COUNTER_FIELD_DTE 0x00000300 // 0000 0000 0000 0000 0000 0011 0000 0000
26 #define COUNTER_FIELD_DTE 0x00000300 // 0000 0000 0000 0000 0000 0011 0000 0000
27 #define COUNTER_MASK_DTE 0xfffffcff // 1111 1111 1111 1111 1111 1100 1111 1111
27 #define COUNTER_MASK_DTE 0xfffffcff // 1111 1111 1111 1111 1111 1100 1111 1111
28 #define POS_DDE 6
28 #define POS_DDE 6
29 #define COUNTER_FIELD_DDE 0x000000c0 // 0000 0000 0000 0000 0000 0000 1100 0000
29 #define COUNTER_FIELD_DDE 0x000000c0 // 0000 0000 0000 0000 0000 0000 1100 0000
30 #define COUNTER_MASK_DDE 0xffffff3f // 1111 1111 1111 1111 1111 1111 0011 1111
30 #define COUNTER_MASK_DDE 0xffffff3f // 1111 1111 1111 1111 1111 1111 0011 1111
31
31
32 // ASR16
32 // ASR16
33 #define POS_FPFTID 30
33 #define POS_FPFTID 30
34 #define POS_FPRF 27
34 #define POS_FPRF 27
35 #define POS_FDI 16 // FP RF protection enable/disable
35 #define POS_FDI 16 // FP RF protection enable/disable
36 #define POS_IUFTID 14
36 #define POS_IUFTID 14
37 #define POS_IURF 11
37 #define POS_IURF 11
38 #define POS_IDI 0 // IU RF protection enable/disable
38 #define POS_IDI 0 // IU RF protection enable/disable
39
39
40 #define COUNTER_FIELD_FPRF 0x38000000 // 0011 1000 0000 0000 0000 0000 0000 0000
40 #define COUNTER_FIELD_FPRF 0x38000000 // 0011 1000 0000 0000 0000 0000 0000 0000
41 #define COUNTER_MASK_FPRF 0xc7ffffff // 1100 0111 1111 1111 1111 1111 1111 1111
41 #define COUNTER_MASK_FPRF 0xc7ffffff // 1100 0111 1111 1111 1111 1111 1111 1111
42
42
43 #define COUNTER_FIELD_IURF 0x00003800 // 0000 0000 0000 0000 0011 1000 0000 0000
43 #define COUNTER_FIELD_IURF 0x00003800 // 0000 0000 0000 0000 0011 1000 0000 0000
44 #define COUNTER_MASK_IURF 0xffffc7ff // 1111 1111 1111 1111 1100 0111 1111 1111
44 #define COUNTER_MASK_IURF 0xffffc7ff // 1111 1111 1111 1111 1100 0111 1111 1111
45
45
46 volatile unsigned int *asr16Ptr = (volatile unsigned int *) ASR16_REG_ADDRESS;
46 volatile unsigned int *asr16Ptr = (volatile unsigned int *) ASR16_REG_ADDRESS;
47
47
48 static inline void flushCache()
48 static inline void flushCache()
49 {
49 {
50 /**
50 /**
51 * Flush the data cache and the instruction cache.
51 * Flush the data cache and the instruction cache.
52 *
52 *
53 * @param void
53 * @param void
54 *
54 *
55 * @return void
55 * @return void
56 */
56 */
57
57
58 asm("flush");
58 asm("flush");
59 }
59 }
60
60
61 //***************************
61 //***************************
62 // CCR Cache control register
62 // CCR Cache control register
63
63
64 static unsigned int CCR_getValue()
64 static unsigned int CCR_getValue()
65 {
65 {
66 unsigned int cacheControlRegister = 0;
66 unsigned int cacheControlRegister = 0;
67 __asm__ __volatile__("lda [%%g0] 2, %0" : "=r"(cacheControlRegister) : );
67 __asm__ __volatile__("lda [%%g0] 2, %0" : "=r"(cacheControlRegister) : );
68 return cacheControlRegister;
68 return cacheControlRegister;
69 }
69 }
70
70
71 static void CCR_setValue(unsigned int cacheControlRegister)
71 static void CCR_setValue(unsigned int cacheControlRegister)
72 {
72 {
73 __asm__ __volatile__("sta %0, [%%g0] 2" : : "r"(cacheControlRegister));
73 __asm__ __volatile__("sta %0, [%%g0] 2" : : "r"(cacheControlRegister));
74 }
74 }
75
75
76 static void CCR_resetCacheControlRegister()
76 static void CCR_resetCacheControlRegister()
77 {
77 {
78 unsigned int cacheControlRegister;
78 unsigned int cacheControlRegister;
79 cacheControlRegister = 0x00;
79 cacheControlRegister = 0x00;
80 CCR_setValue(cacheControlRegister);
80 CCR_setValue(cacheControlRegister);
81 }
81 }
82
82
83 static void CCR_enableInstructionCache()
83 static void CCR_enableInstructionCache()
84 {
84 {
85 // [1:0] Instruction Cache state (ICS)
85 // [1:0] Instruction Cache state (ICS)
86 // Indicates the current data cache state according to the following: X0 = disabled, 01 = frozen, 11 = enabled.
86 // Indicates the current data cache state according to the following: X0 = disabled, 01 = frozen, 11 = enabled.
87 unsigned int cacheControlRegister;
87 unsigned int cacheControlRegister;
88 cacheControlRegister = CCR_getValue();
88 cacheControlRegister = CCR_getValue();
89 cacheControlRegister = (cacheControlRegister | 0x3);
89 cacheControlRegister = (cacheControlRegister | 0x3);
90 CCR_setValue(cacheControlRegister);
90 CCR_setValue(cacheControlRegister);
91 }
91 }
92
92
93 static void CCR_enableDataCache()
93 static void CCR_enableDataCache()
94 {
94 {
95 // [3:2] Data Cache state (DCS)
95 // [3:2] Data Cache state (DCS)
96 // Indicates the current data cache state according to the following: X0 = disabled, 01 = frozen, 11 = enabled.
96 // Indicates the current data cache state according to the following: X0 = disabled, 01 = frozen, 11 = enabled.
97 unsigned int cacheControlRegister;
97 unsigned int cacheControlRegister;
98 cacheControlRegister = CCR_getValue();
98 cacheControlRegister = CCR_getValue();
99 cacheControlRegister = (cacheControlRegister | 0xc);
99 cacheControlRegister = (cacheControlRegister | 0xc);
100 CCR_setValue(cacheControlRegister);
100 CCR_setValue(cacheControlRegister);
101 }
101 }
102
102
103 static void CCR_enableInstructionBurstFetch()
103 static void CCR_enableInstructionBurstFetch()
104 {
104 {
105 // [16] Instruction burst fetch (IB). This bit enables burst fill during instruction fetch.
105 // [16] Instruction burst fetch (IB). This bit enables burst fill during instruction fetch.
106 unsigned int cacheControlRegister;
106 unsigned int cacheControlRegister;
107 cacheControlRegister = CCR_getValue();
107 cacheControlRegister = CCR_getValue();
108 // set the bit IB to 1
108 // set the bit IB to 1
109 cacheControlRegister = (cacheControlRegister | 0x10000);
109 cacheControlRegister = (cacheControlRegister | 0x10000);
110 CCR_setValue(cacheControlRegister);
110 CCR_setValue(cacheControlRegister);
111 }
111 }
112
112
113 void CCR_getInstructionAndDataErrorCounters( unsigned int* instructionErrorCounter, unsigned int* dataErrorCounter )
113 void CCR_getInstructionAndDataErrorCounters( unsigned int* instructionErrorCounter, unsigned int* dataErrorCounter )
114 {
114 {
115 // [13:12] Instruction Tag Errors (ITE) - Number of detected parity errors in the instruction tag cache.
115 // [13:12] Instruction Tag Errors (ITE) - Number of detected parity errors in the instruction tag cache.
116 // Only available if fault-tolerance is enabled (FT field in this register is non-zero).
116 // Only available if fault-tolerance is enabled (FT field in this register is non-zero).
117 // [11:10] Instruction Data Errors (IDE) - Number of detected parity errors in the instruction data cache.
117 // [11:10] Instruction Data Errors (IDE) - Number of detected parity errors in the instruction data cache.
118 // Only available if fault-tolerance is enabled (FT field in this register is non-zero).
118 // Only available if fault-tolerance is enabled (FT field in this register is non-zero).
119
119
120 unsigned int cacheControlRegister;
120 unsigned int cacheControlRegister;
121 unsigned int iTE;
121 unsigned int iTE;
122 unsigned int iDE;
122 unsigned int iDE;
123 unsigned int dTE;
123 unsigned int dTE;
124 unsigned int dDE;
124 unsigned int dDE;
125
125
126 cacheControlRegister = CCR_getValue();
126 cacheControlRegister = CCR_getValue();
127 iTE = (cacheControlRegister & COUNTER_FIELD_ITE) >> POS_ITE;
127 iTE = (cacheControlRegister & COUNTER_FIELD_ITE) >> POS_ITE;
128 iDE = (cacheControlRegister & COUNTER_FIELD_IDE) >> POS_IDE;
128 iDE = (cacheControlRegister & COUNTER_FIELD_IDE) >> POS_IDE;
129 dTE = (cacheControlRegister & COUNTER_FIELD_DTE) >> POS_DTE;
129 dTE = (cacheControlRegister & COUNTER_FIELD_DTE) >> POS_DTE;
130 dDE = (cacheControlRegister & COUNTER_FIELD_DDE) >> POS_DDE;
130 dDE = (cacheControlRegister & COUNTER_FIELD_DDE) >> POS_DDE;
131
131
132 *instructionErrorCounter = iTE + iDE;
132 *instructionErrorCounter = iTE + iDE;
133 *dataErrorCounter = dTE + dDE;
133 *dataErrorCounter = dTE + dDE;
134
134
135 // reset counters
135 // reset counters
136 cacheControlRegister = cacheControlRegister
136 cacheControlRegister = cacheControlRegister
137 & COUNTER_FIELD_ITE
137 & COUNTER_FIELD_ITE
138 & COUNTER_FIELD_IDE
138 & COUNTER_FIELD_IDE
139 & COUNTER_FIELD_DTE
139 & COUNTER_FIELD_DTE
140 & COUNTER_FIELD_DDE;
140 & COUNTER_FIELD_DDE;
141
141
142 CCR_setValue(cacheControlRegister);
142 CCR_setValue(cacheControlRegister);
143 }
143 }
144
144
145 //*******************************************
145 //*******************************************
146 // ASR16 Register protection control register
146 // ASR16 Register protection control register
147
147
148 static void ASR16_resetRegisterProtectionControlRegister()
148 static void ASR16_resetRegisterProtectionControlRegister()
149 {
149 {
150 *asr16Ptr = 0x00;
150 *asr16Ptr = 0x00;
151 }
151 }
152
152
153 void ASR16_get_FPRF_IURF_ErrorCounters( unsigned int* fprfErrorCounter, unsigned int* iurfErrorCounter)
153 void ASR16_get_FPRF_IURF_ErrorCounters( unsigned int* fprfErrorCounter, unsigned int* iurfErrorCounter)
154 {
154 {
155 /** This function is used to retrieve the integer unit register file error counter and the floating point unit
155 /** This function is used to retrieve the integer unit register file error counter and the floating point unit
156 * register file error counter
156 * register file error counter
157 *
157 *
158 * @return void
158 * @return void
159 *
159 *
160 * [29:27] FP RF error counter - Number of detected parity errors in the FP register file.
160 * [29:27] FP RF error counter - Number of detected parity errors in the FP register file.
161 * [13:11] IU RF error counter - Number of detected parity errors in the IU register file.
161 * [13:11] IU RF error counter - Number of detected parity errors in the IU register file.
162 *
162 *
163 */
163 */
164
164
165 unsigned int asr16;
165 unsigned int asr16;
166
166
167 asr16 = *asr16Ptr;
167 asr16 = *asr16Ptr;
168 *fprfErrorCounter = ( asr16 & COUNTER_FIELD_FPRF ) >> POS_FPRF;
168 *fprfErrorCounter = ( asr16 & COUNTER_FIELD_FPRF ) >> POS_FPRF;
169 *iurfErrorCounter = ( asr16 & COUNTER_FIELD_IURF ) >> POS_IURF;
169 *iurfErrorCounter = ( asr16 & COUNTER_FIELD_IURF ) >> POS_IURF;
170
170
171 // reset the counter to 0
171 // reset the counter to 0
172 asr16 = asr16
172 asr16 = asr16
173 & COUNTER_MASK_FPRF
173 & COUNTER_MASK_FPRF
174 & COUNTER_FIELD_IURF;
174 & COUNTER_FIELD_IURF;
175
175
176 *asr16Ptr = asr16;
176 *asr16Ptr = asr16;
177 }
177 }
178
178
179 static void faultTolerantScheme()
179 static void faultTolerantScheme()
180 {
180 {
181 // [20:19] FT scheme (FT) - “00” = no FT, “01” = 4-bit checking implemented
181 // [20:19] FT scheme (FT) - “00” = no FT, “01” = 4-bit checking implemented
182 unsigned int cacheControlRegister;
182 unsigned int cacheControlRegister;
183 unsigned int *plugAndPlayRegister;
183 unsigned int *plugAndPlayRegister;
184 unsigned int vendorId;
184 unsigned int vendorId;
185 unsigned int deviceId;
185 unsigned int deviceId;
186
186
187 plugAndPlayRegister = (unsigned int*) REGS_ADDR_PLUGANDPLAY;
187 plugAndPlayRegister = (unsigned int*) REGS_ADDR_PLUGANDPLAY;
188 vendorId = ( (*plugAndPlayRegister) & 0xff000000 ) >> 24;
188 vendorId = ( (*plugAndPlayRegister) & 0xff000000 ) >> 24;
189 deviceId = ( (*plugAndPlayRegister) & 0x00fff000 ) >> 12;
189 deviceId = ( (*plugAndPlayRegister) & 0x00fff000 ) >> 12;
190
190
191 cacheControlRegister = CCR_getValue();
191 cacheControlRegister = CCR_getValue();
192
192
193 if( (vendorId == VENDORID_GAISLER) & (deviceId ==DEVICEID_LEON3FT) )
193 if( (vendorId == VENDORID_GAISLER) & (deviceId ==DEVICEID_LEON3FT) )
194 {
194 {
195 PRINTF("in faultTolerantScheme *** Leon3FT detected\n");
195 PRINTF("in faultTolerantScheme *** Leon3FT detected\n");
196 PRINTF2(" *** vendorID = 0x%x, deviceId = 0x%x\n", vendorId, deviceId);
196 PRINTF2(" *** vendorID = 0x%x, deviceId = 0x%x\n", vendorId, deviceId);
197 PRINTF1("ASR16 IU RF protection, bit 0 (IDI) is: 0x%x (0 => protection enabled)\n",
197 PRINTF1("ASR16 IU RF protection, bit 0 (IDI) is: 0x%x (0 => protection enabled)\n",
198 (*asr16Ptr >> POS_IDI) & 1);
198 (*asr16Ptr >> POS_IDI) & 1);
199 PRINTF1("ASR16 FP RF protection, bit 16 (FDI) is: 0x%x (0 => protection enabled)\n",
199 PRINTF1("ASR16 FP RF protection, bit 16 (FDI) is: 0x%x (0 => protection enabled)\n",
200 (*asr16Ptr >> POS_FDI) & 1);
200 (*asr16Ptr >> POS_FDI) & 1);
201 PRINTF1("ASR16 IU FT ID bits [15:14] is: 0x%x (2 => 8-bit parity without restart)\n",
201 PRINTF1("ASR16 IU FT ID bits [15:14] is: 0x%x (2 => 8-bit parity without restart)\n",
202 (*asr16Ptr >> POS_IUFTID) & 0x3);
202 (*asr16Ptr >> POS_IUFTID) & 0x3);
203 PRINTF1("ASR16 FP FT ID bits [31:30] is: 0x%x (1 => 4-bit parity with restart)\n",
203 PRINTF1("ASR16 FP FT ID bits [31:30] is: 0x%x (1 => 4-bit parity with restart)\n",
204 (*asr16Ptr >> POS_FPFTID) & 0x03);
204 (*asr16Ptr >> POS_FPFTID) & 0x03);
205 PRINTF1("CCR FT bits [20:19] are: 0x%x (1 => 4-bit parity with restart)\n",
205 PRINTF1("CCR FT bits [20:19] are: 0x%x (1 => 4-bit parity with restart)\n",
206 (cacheControlRegister >> POS_FT) & 0x3 );
206 (cacheControlRegister >> POS_FT) & 0x3 );
207
207
208 // CCR The FFT bits are just read, the FT scheme is set to “01” = 4-bit checking implemented by default
208 // CCR The FFT bits are just read, the FT scheme is set to “01” = 4-bit checking implemented by default
209
209
210 // ASR16 Ancillary State Register configuration (Register protection control register)
210 // ASR16 Ancillary State Register configuration (Register protection control register)
211 // IU RF protection is set by default, bit 0 IDI = 0
211 // IU RF protection is set by default, bit 0 IDI = 0
212 // FP RF protection is set by default, bit 16 FDI = 0
212 // FP RF protection is set by default, bit 16 FDI = 0
213 }
213 }
214 else
214 else
215 {
215 {
216 PRINTF("in faultTolerantScheme *** not a Leon3FT not detected\n");
216 PRINTF("in faultTolerantScheme *** Leon3FT not detected\n");
217 PRINTF2(" *** vendorID = 0x%x, deviceId = 0x%x\n", vendorId, deviceId);
217 PRINTF2(" *** vendorID = 0x%x, deviceId = 0x%x\n", vendorId, deviceId);
218 }
218 }
219 }
219 }
220
220
221 #endif /* GSCMEMORY_HPP_ */
221 #endif /* GSCMEMORY_HPP_ */
@@ -1,14 +1,14
1 # LOAD FSW USING LINK 1
1 # LOAD FSW USING LINK 1
2 SpwPlugin0.StarDundeeSelectLinkNumber( 1 )
2 SpwPlugin0.StarDundeeSelectLinkNumber( 1 )
3
3
4 dsu3plugin0.openFile("/home/pleroy/DEV/DEV_PLE/FSW-qt/bin/fsw")
4 dsu3plugin0.openFile("/home/pleroy/DEV/DEV_PLE/build-DEV_PLE-Desktop-Default/src/fsw")
5 #dsu3plugin0.openFile("/opt/LFR/LFR-FSW/2.0.2.3/fsw")
5 #dsu3plugin0.openFile("/opt/LFR/LFR-FSW/2.0.2.3/fsw")
6 dsu3plugin0.loadFile()
6 dsu3plugin0.loadFile()
7
7
8 dsu3plugin0.run()
8 dsu3plugin0.run()
9
9
10 # START SENDING TIMECODES AT 1 Hz
10 # START SENDING TIMECODES AT 1 Hz
11 #SpwPlugin0.StarDundeeStartTimecodes( 1 )
11 #SpwPlugin0.StarDundeeStartTimecodes( 1 )
12
12
13 # it is possible to change the time code frequency
13 # it is possible to change the time code frequency
14 #RMAPPlugin0.changeTimecodeFrequency(2)
14 #RMAPPlugin0.changeTimecodeFrequency(2)
@@ -1,8 +1,9
1 set(CMAKE_SYSTEM_NAME rtems)
1 set(CMAKE_SYSTEM_NAME rtems)
2
2
3 set(CMAKE_C_COMPILER /opt/rtems-4.10/bin/sparc-rtems-gcc)
3 set(CMAKE_C_COMPILER /opt/rtems-4.10/bin/sparc-rtems-gcc)
4 set(CMAKE_CXX_COMPILER /opt/rtems-4.10/bin/sparc-rtems-g++)
4 set(CMAKE_CXX_COMPILER /opt/rtems-4.10/bin/sparc-rtems-g++)
5 set(CMAKE_LINKER /opt/rtems-4.10/bin/sparc-rtems-g++)
5 set(CMAKE_LINKER /opt/rtems-4.10/bin/sparc-rtems-g++)
6 SET(CMAKE_EXE_LINKER_FLAGS "-static")
6 SET(CMAKE_EXE_LINKER_FLAGS "-static")
7 set(CMAKE_C_FLAGS_RELEASE "-O3")
7 set(CMAKE_C_LINK_EXECUTABLE "<CMAKE_LINKER> <FLAGS> <CMAKE_CXX_LINK_FLAGS> <LINK_FLAGS> <OBJECTS> -o <TARGET> <LINK_LIBRARIES>")
8 set(CMAKE_C_LINK_EXECUTABLE "<CMAKE_LINKER> <FLAGS> <CMAKE_CXX_LINK_FLAGS> <LINK_FLAGS> <OBJECTS> -o <TARGET> <LINK_LIBRARIES>")
8 include_directories("/opt/rtems-4.10/sparc-rtems/leon3/lib/include")
9 include_directories("/opt/rtems-4.10/sparc-rtems/leon3/lib/include")
@@ -1,105 +1,105
1 cmake_minimum_required (VERSION 2.6)
1 cmake_minimum_required (VERSION 2.6)
2 project (FSW)
2 project (fsw)
3
3
4 include(sparc-rtems)
4 include(sparc-rtems)
5
5
6 include_directories("../header"
6 include_directories("../header"
7 "../header/lfr_common_headers"
7 "../header/lfr_common_headers"
8 "../header/processing"
8 "../header/processing"
9 "../LFR_basic-parameters"
9 "../LFR_basic-parameters"
10 "../src")
10 "../src")
11
11
12 set(SOURCES wf_handler.c
12 set(SOURCES wf_handler.c
13 tc_handler.c
13 tc_handler.c
14 fsw_misc.c
14 fsw_misc.c
15 fsw_init.c
15 fsw_init.c
16 fsw_globals.c
16 fsw_globals.c
17 fsw_spacewire.c
17 fsw_spacewire.c
18 tc_load_dump_parameters.c
18 tc_load_dump_parameters.c
19 tm_lfr_tc_exe.c
19 tm_lfr_tc_exe.c
20 tc_acceptance.c
20 tc_acceptance.c
21 processing/fsw_processing.c
21 processing/fsw_processing.c
22 processing/avf0_prc0.c
22 processing/avf0_prc0.c
23 processing/avf1_prc1.c
23 processing/avf1_prc1.c
24 processing/avf2_prc2.c
24 processing/avf2_prc2.c
25 lfr_cpu_usage_report.c
25 lfr_cpu_usage_report.c
26 ${LFR_BP_SRC}
26 ${LFR_BP_SRC}
27 ../header/wf_handler.h
27 ../header/wf_handler.h
28 ../header/tc_handler.h
28 ../header/tc_handler.h
29 ../header/grlib_regs.h
29 ../header/grlib_regs.h
30 ../header/fsw_misc.h
30 ../header/fsw_misc.h
31 ../header/fsw_init.h
31 ../header/fsw_init.h
32 ../header/fsw_spacewire.h
32 ../header/fsw_spacewire.h
33 ../header/tc_load_dump_parameters.h
33 ../header/tc_load_dump_parameters.h
34 ../header/tm_lfr_tc_exe.h
34 ../header/tm_lfr_tc_exe.h
35 ../header/tc_acceptance.h
35 ../header/tc_acceptance.h
36 ../header/processing/fsw_processing.h
36 ../header/processing/fsw_processing.h
37 ../header/processing/avf0_prc0.h
37 ../header/processing/avf0_prc0.h
38 ../header/processing/avf1_prc1.h
38 ../header/processing/avf1_prc1.h
39 ../header/processing/avf2_prc2.h
39 ../header/processing/avf2_prc2.h
40 ../header/fsw_params_wf_handler.h
40 ../header/fsw_params_wf_handler.h
41 ../header/lfr_cpu_usage_report.h
41 ../header/lfr_cpu_usage_report.h
42 ../header/lfr_common_headers/ccsds_types.h
42 ../header/lfr_common_headers/ccsds_types.h
43 ../header/lfr_common_headers/fsw_params.h
43 ../header/lfr_common_headers/fsw_params.h
44 ../header/lfr_common_headers/fsw_params_nb_bytes.h
44 ../header/lfr_common_headers/fsw_params_nb_bytes.h
45 ../header/lfr_common_headers/fsw_params_processing.h
45 ../header/lfr_common_headers/fsw_params_processing.h
46 ../header/lfr_common_headers/tm_byte_positions.h
46 ../header/lfr_common_headers/tm_byte_positions.h
47 ../LFR_basic-parameters/basic_parameters.h
47 ../LFR_basic-parameters/basic_parameters.h
48 ../LFR_basic-parameters/basic_parameters_params.h
48 ../LFR_basic-parameters/basic_parameters_params.h
49 ../header/GscMemoryLPP.hpp
49 ../header/GscMemoryLPP.hpp
50 )
50 )
51
51
52
52
53 option(FSW_verbose "Enable verbose LFR" ON)
53 option(FSW_verbose "Enable verbose LFR" ON)
54 option(FSW_boot_messages "Enable LFR boot messages" ON)
54 option(FSW_boot_messages "Enable LFR boot messages" ON)
55 option(FSW_debug_messages "Enable LFR debug messages" ON)
55 option(FSW_debug_messages "Enable LFR debug messages" ON)
56 option(FSW_cpu_usage_report "Enable LFR cpu usage report" OFF)
56 option(FSW_cpu_usage_report "Enable LFR cpu usage report" OFF)
57 option(FSW_stack_report "Enable LFR stack report" OFF)
57 option(FSW_stack_report "Enable LFR stack report" OFF)
58 option(FSW_vhdl_dev "?" OFF)
58 option(FSW_vhdl_dev "?" OFF)
59 option(FSW_lpp_dpu_destid "Set to debug at LPP" ON)
59 option(FSW_lpp_dpu_destid "Set to debug at LPP" ON)
60 option(FSW_debug_watchdog "Enable debug watchdog" OFF)
60 option(FSW_debug_watchdog "Enable debug watchdog" OFF)
61 option(FSW_debug_tch "?" OFF)
61 option(FSW_debug_tch "?" OFF)
62
62
63 set(SW_VERSION_N1 "3" CACHE STRING "Choose N1 FSW Version." FORCE)
63 set(SW_VERSION_N1 "3" CACHE STRING "Choose N1 FSW Version." FORCE)
64 set(SW_VERSION_N2 "1" CACHE STRING "Choose N2 FSW Version." FORCE)
64 set(SW_VERSION_N2 "1" CACHE STRING "Choose N2 FSW Version." FORCE)
65 set(SW_VERSION_N3 "0" CACHE STRING "Choose N3 FSW Version." FORCE)
65 set(SW_VERSION_N3 "0" CACHE STRING "Choose N3 FSW Version." FORCE)
66 set(SW_VERSION_N4 "4" CACHE STRING "Choose N4 FSW Version." FORCE)
66 set(SW_VERSION_N4 "4" CACHE STRING "Choose N4 FSW Version." FORCE)
67
67
68
68
69 if(FSW_verbose)
69 if(FSW_verbose)
70 add_definitions(-DPRINT_MESSAGES_ON_CONSOLE)
70 add_definitions(-DPRINT_MESSAGES_ON_CONSOLE)
71 endif()
71 endif()
72 if(FSW_boot_messages)
72 if(FSW_boot_messages)
73 add_definitions(-DBOOT_MESSAGES)
73 add_definitions(-DBOOT_MESSAGES)
74 endif()
74 endif()
75 if(FSW_debug_messages)
75 if(FSW_debug_messages)
76 add_definitions(-DDEBUG_MESSAGES)
76 add_definitions(-DDEBUG_MESSAGES)
77 endif()
77 endif()
78 if(FSW_cpu_usage_report)
78 if(FSW_cpu_usage_report)
79 add_definitions(-DPRINT_TASK_STATISTICS)
79 add_definitions(-DPRINT_TASK_STATISTICS)
80 endif()
80 endif()
81 if(FSW_stack_report)
81 if(FSW_stack_report)
82 add_definitions(-DPRINT_STACK_REPORT)
82 add_definitions(-DPRINT_STACK_REPORT)
83 endif()
83 endif()
84 if(FSW_vhdl_dev)
84 if(FSW_vhdl_dev)
85 add_definitions(-DVHDL_DEV)
85 add_definitions(-DVHDL_DEV)
86 endif()
86 endif()
87 if(FSW_lpp_dpu_destid)
87 if(FSW_lpp_dpu_destid)
88 add_definitions(-DLPP_DPU_DESTID)
88 add_definitions(-DLPP_DPU_DESTID)
89 endif()
89 endif()
90 if(FSW_debug_watchdog)
90 if(FSW_debug_watchdog)
91 add_definitions(-DDEBUG_WATCHDOG)
91 add_definitions(-DDEBUG_WATCHDOG)
92 endif()
92 endif()
93 if(FSW_debug_tch)
93 if(FSW_debug_tch)
94 add_definitions(-DDEBUG_TCH)
94 add_definitions(-DDEBUG_TCH)
95 endif()
95 endif()
96
96
97 add_definitions(-DMSB_FIRST_TCH)
97 add_definitions(-DMSB_FIRST_TCH)
98
98
99 add_definitions(-DSWVERSION=-1-0)
99 add_definitions(-DSWVERSION=-1-0)
100 add_definitions(-DSW_VERSION_N1=${SW_VERSION_N1})
100 add_definitions(-DSW_VERSION_N1=${SW_VERSION_N1})
101 add_definitions(-DSW_VERSION_N2=${SW_VERSION_N2})
101 add_definitions(-DSW_VERSION_N2=${SW_VERSION_N2})
102 add_definitions(-DSW_VERSION_N3=${SW_VERSION_N3})
102 add_definitions(-DSW_VERSION_N3=${SW_VERSION_N3})
103 add_definitions(-DSW_VERSION_N4=${SW_VERSION_N4})
103 add_definitions(-DSW_VERSION_N4=${SW_VERSION_N4})
104
104
105 add_executable(FSW ${SOURCES})
105 add_executable(fsw ${SOURCES})
@@ -1,939 +1,938
1 /** This is the RTEMS initialization module.
1 /** This is the RTEMS initialization module.
2 *
2 *
3 * @file
3 * @file
4 * @author P. LEROY
4 * @author P. LEROY
5 *
5 *
6 * This module contains two very different information:
6 * This module contains two very different information:
7 * - specific instructions to configure the compilation of the RTEMS executive
7 * - specific instructions to configure the compilation of the RTEMS executive
8 * - functions related to the fligth softwre initialization, especially the INIT RTEMS task
8 * - functions related to the fligth softwre initialization, especially the INIT RTEMS task
9 *
9 *
10 */
10 */
11
11
12 //*************************
12 //*************************
13 // GPL reminder to be added
13 // GPL reminder to be added
14 //*************************
14 //*************************
15
15
16 #include <rtems.h>
16 #include <rtems.h>
17
17
18 /* configuration information */
18 /* configuration information */
19
19
20 #define CONFIGURE_INIT
20 #define CONFIGURE_INIT
21
21
22 #include <bsp.h> /* for device driver prototypes */
22 #include <bsp.h> /* for device driver prototypes */
23
23
24 /* configuration information */
24 /* configuration information */
25
25
26 #define CONFIGURE_APPLICATION_NEEDS_CONSOLE_DRIVER
26 #define CONFIGURE_APPLICATION_NEEDS_CONSOLE_DRIVER
27 #define CONFIGURE_APPLICATION_NEEDS_CLOCK_DRIVER
27 #define CONFIGURE_APPLICATION_NEEDS_CLOCK_DRIVER
28
28
29 #define CONFIGURE_MAXIMUM_TASKS 20
29 #define CONFIGURE_MAXIMUM_TASKS 20
30 #define CONFIGURE_RTEMS_INIT_TASKS_TABLE
30 #define CONFIGURE_RTEMS_INIT_TASKS_TABLE
31 #define CONFIGURE_EXTRA_TASK_STACKS (3 * RTEMS_MINIMUM_STACK_SIZE)
31 #define CONFIGURE_EXTRA_TASK_STACKS (3 * RTEMS_MINIMUM_STACK_SIZE)
32 #define CONFIGURE_LIBIO_MAXIMUM_FILE_DESCRIPTORS 32
32 #define CONFIGURE_LIBIO_MAXIMUM_FILE_DESCRIPTORS 32
33 #define CONFIGURE_INIT_TASK_PRIORITY 1 // instead of 100
33 #define CONFIGURE_INIT_TASK_PRIORITY 1 // instead of 100
34 #define CONFIGURE_INIT_TASK_MODE (RTEMS_DEFAULT_MODES | RTEMS_NO_PREEMPT)
34 #define CONFIGURE_INIT_TASK_MODE (RTEMS_DEFAULT_MODES | RTEMS_NO_PREEMPT)
35 #define CONFIGURE_INIT_TASK_ATTRIBUTES (RTEMS_DEFAULT_ATTRIBUTES | RTEMS_FLOATING_POINT)
35 #define CONFIGURE_INIT_TASK_ATTRIBUTES (RTEMS_DEFAULT_ATTRIBUTES | RTEMS_FLOATING_POINT)
36 #define CONFIGURE_MAXIMUM_DRIVERS 16
36 #define CONFIGURE_MAXIMUM_DRIVERS 16
37 #define CONFIGURE_MAXIMUM_PERIODS 5
37 #define CONFIGURE_MAXIMUM_PERIODS 5
38 #define CONFIGURE_MAXIMUM_TIMERS 5 // [spiq] [link] [spacewire_reset_link]
38 #define CONFIGURE_MAXIMUM_TIMERS 5 // [spiq] [link] [spacewire_reset_link]
39 #define CONFIGURE_MAXIMUM_MESSAGE_QUEUES 5
39 #define CONFIGURE_MAXIMUM_MESSAGE_QUEUES 5
40 #ifdef PRINT_STACK_REPORT
40 #ifdef PRINT_STACK_REPORT
41 #define CONFIGURE_STACK_CHECKER_ENABLED
41 #define CONFIGURE_STACK_CHECKER_ENABLED
42 #endif
42 #endif
43
43
44 #include <rtems/confdefs.h>
44 #include <rtems/confdefs.h>
45
45
46 /* If --drvmgr was enabled during the configuration of the RTEMS kernel */
46 /* If --drvmgr was enabled during the configuration of the RTEMS kernel */
47 #ifdef RTEMS_DRVMGR_STARTUP
47 #ifdef RTEMS_DRVMGR_STARTUP
48 #ifdef LEON3
48 #ifdef LEON3
49 /* Add Timer and UART Driver */
49 /* Add Timer and UART Driver */
50
50
51 #ifdef CONFIGURE_APPLICATION_NEEDS_CLOCK_DRIVER
51 #ifdef CONFIGURE_APPLICATION_NEEDS_CLOCK_DRIVER
52 #define CONFIGURE_DRIVER_AMBAPP_GAISLER_GPTIMER
52 #define CONFIGURE_DRIVER_AMBAPP_GAISLER_GPTIMER
53 #endif
53 #endif
54
54
55 #ifdef CONFIGURE_APPLICATION_NEEDS_CONSOLE_DRIVER
55 #ifdef CONFIGURE_APPLICATION_NEEDS_CONSOLE_DRIVER
56 #define CONFIGURE_DRIVER_AMBAPP_GAISLER_APBUART
56 #define CONFIGURE_DRIVER_AMBAPP_GAISLER_APBUART
57 #endif
57 #endif
58
58
59 #endif
59 #endif
60 #define CONFIGURE_DRIVER_AMBAPP_GAISLER_GRSPW /* GRSPW Driver */
60 #define CONFIGURE_DRIVER_AMBAPP_GAISLER_GRSPW /* GRSPW Driver */
61
61
62 #include <drvmgr/drvmgr_confdefs.h>
62 #include <drvmgr/drvmgr_confdefs.h>
63 #endif
63 #endif
64
64
65 #include "fsw_init.h"
65 #include "fsw_init.h"
66 #include "fsw_config.c"
66 #include "fsw_config.c"
67 #include "GscMemoryLPP.hpp"
67 #include "GscMemoryLPP.hpp"
68
68
69 void initCache()
69 void initCache()
70 {
70 {
71 // ASI 2 contains a few control registers that have not been assigned as ancillary state registers.
71 // ASI 2 contains a few control registers that have not been assigned as ancillary state registers.
72 // These should only be read and written using 32-bit LDA/STA instructions.
72 // These should only be read and written using 32-bit LDA/STA instructions.
73 // All cache registers are accessed through load/store operations to the alternate address space (LDA/STA), using ASI = 2.
73 // All cache registers are accessed through load/store operations to the alternate address space (LDA/STA), using ASI = 2.
74 // The table below shows the register addresses:
74 // The table below shows the register addresses:
75 // 0x00 Cache control register
75 // 0x00 Cache control register
76 // 0x04 Reserved
76 // 0x04 Reserved
77 // 0x08 Instruction cache configuration register
77 // 0x08 Instruction cache configuration register
78 // 0x0C Data cache configuration register
78 // 0x0C Data cache configuration register
79
79
80 // Cache Control Register Leon3 / Leon3FT
80 // Cache Control Register Leon3 / Leon3FT
81 // 31..30 29 28 27..24 23 22 21 20..19 18 17 16
81 // 31..30 29 28 27..24 23 22 21 20..19 18 17 16
82 // RFT PS TB DS FD FI FT ST IB
82 // RFT PS TB DS FD FI FT ST IB
83 // 15 14 13..12 11..10 9..8 7..6 5 4 3..2 1..0
83 // 15 14 13..12 11..10 9..8 7..6 5 4 3..2 1..0
84 // IP DP ITE IDE DTE DDE DF IF DCS ICS
84 // IP DP ITE IDE DTE DDE DF IF DCS ICS
85
85
86 unsigned int cacheControlRegister;
86 unsigned int cacheControlRegister;
87
87
88 CCR_resetCacheControlRegister();
88 CCR_resetCacheControlRegister();
89 ASR16_resetRegisterProtectionControlRegister();
89 ASR16_resetRegisterProtectionControlRegister();
90
90
91 cacheControlRegister = CCR_getValue();
91 cacheControlRegister = CCR_getValue();
92 PRINTF1("(0) CCR - Cache Control Register = %x\n", cacheControlRegister);
92 PRINTF1("(0) CCR - Cache Control Register = %x\n", cacheControlRegister);
93 PRINTF1("(0) ASR16 = %x\n", *asr16Ptr);
93 PRINTF1("(0) ASR16 = %x\n", *asr16Ptr);
94
94
95 CCR_enableInstructionCache(); // ICS bits
95 CCR_enableInstructionCache(); // ICS bits
96 CCR_enableDataCache(); // DCS bits
96 CCR_enableDataCache(); // DCS bits
97 CCR_enableInstructionBurstFetch(); // IB bit
97 CCR_enableInstructionBurstFetch(); // IB bit
98
98
99 faultTolerantScheme();
99 faultTolerantScheme();
100
100
101 cacheControlRegister = CCR_getValue();
101 cacheControlRegister = CCR_getValue();
102 PRINTF1("(1) CCR - Cache Control Register = %x\n", cacheControlRegister);
102 PRINTF1("(1) CCR - Cache Control Register = %x\n", cacheControlRegister);
103 PRINTF1("(1) ASR16 Register protection control register = %x\n", *asr16Ptr);
103 PRINTF1("(1) ASR16 Register protection control register = %x\n", *asr16Ptr);
104
104
105 PRINTF("\n");
105 PRINTF("\n");
106 }
106 }
107
107
108 rtems_task Init( rtems_task_argument ignored )
108 rtems_task Init( rtems_task_argument ignored )
109 {
109 {
110 /** This is the RTEMS INIT taks, it is the first task launched by the system.
110 /** This is the RTEMS INIT taks, it is the first task launched by the system.
111 *
111 *
112 * @param unused is the starting argument of the RTEMS task
112 * @param unused is the starting argument of the RTEMS task
113 *
113 *
114 * The INIT task create and run all other RTEMS tasks.
114 * The INIT task create and run all other RTEMS tasks.
115 *
115 *
116 */
116 */
117
117
118 //***********
118 //***********
119 // INIT CACHE
119 // INIT CACHE
120
120
121 unsigned char *vhdlVersion;
121 unsigned char *vhdlVersion;
122
122
123 reset_lfr();
123 reset_lfr();
124
124
125 reset_local_time();
125 reset_local_time();
126
126
127 rtems_cpu_usage_reset();
127 rtems_cpu_usage_reset();
128
128
129 rtems_status_code status;
129 rtems_status_code status;
130 rtems_status_code status_spw;
130 rtems_status_code status_spw;
131 rtems_isr_entry old_isr_handler;
131 rtems_isr_entry old_isr_handler;
132
132
133 // UART settings
133 // UART settings
134 enable_apbuart_transmitter();
134 enable_apbuart_transmitter();
135 set_apbuart_scaler_reload_register(REGS_ADDR_APBUART, APBUART_SCALER_RELOAD_VALUE);
135 set_apbuart_scaler_reload_register(REGS_ADDR_APBUART, APBUART_SCALER_RELOAD_VALUE);
136
136
137 DEBUG_PRINTF("\n\n\n\n\nIn INIT *** Now the console is on port COM1\n")
137 DEBUG_PRINTF("\n\n\n\n\nIn INIT *** Now the console is on port COM1\n")
138
138
139
139
140 PRINTF("\n\n\n\n\n")
140 PRINTF("\n\n\n\n\n")
141
141
142 initCache();
142 initCache();
143
143
144 PRINTF("*************************\n")
144 PRINTF("*************************\n")
145 PRINTF("** LFR Flight Software **\n")
145 PRINTF("** LFR Flight Software **\n")
146
146
147 PRINTF1("** %d-", SW_VERSION_N1)
147 PRINTF1("** %d-", SW_VERSION_N1)
148 PRINTF1("%d-" , SW_VERSION_N2)
148 PRINTF1("%d-" , SW_VERSION_N2)
149 PRINTF1("%d-" , SW_VERSION_N3)
149 PRINTF1("%d-" , SW_VERSION_N3)
150 PRINTF1("%d **\n", SW_VERSION_N4)
150 PRINTF1("%d **\n", SW_VERSION_N4)
151
151
152 vhdlVersion = (unsigned char *) (REGS_ADDR_VHDL_VERSION);
152 vhdlVersion = (unsigned char *) (REGS_ADDR_VHDL_VERSION);
153 PRINTF("** VHDL **\n")
153 PRINTF("** VHDL **\n")
154 PRINTF1("** %d.", vhdlVersion[1])
154 PRINTF1("** %d.", vhdlVersion[1])
155 PRINTF1("%d." , vhdlVersion[2])
155 PRINTF1("%d." , vhdlVersion[2])
156 PRINTF1("%d **\n", vhdlVersion[3])
156 PRINTF1("%d **\n", vhdlVersion[3])
157 PRINTF("*************************\n")
157 PRINTF("*************************\n")
158 PRINTF("\n\n")
158 PRINTF("\n\n")
159
159
160 init_parameter_dump();
160 init_parameter_dump();
161 init_kcoefficients_dump();
161 init_kcoefficients_dump();
162 init_local_mode_parameters();
162 init_local_mode_parameters();
163 init_housekeeping_parameters();
163 init_housekeeping_parameters();
164 init_k_coefficients_prc0();
164 init_k_coefficients_prc0();
165 init_k_coefficients_prc1();
165 init_k_coefficients_prc1();
166 init_k_coefficients_prc2();
166 init_k_coefficients_prc2();
167 pa_bia_status_info = 0x00;
167 pa_bia_status_info = 0x00;
168 cp_rpw_sc_rw_f_flags = 0x00;
168 cp_rpw_sc_rw_f_flags = 0x00;
169 cp_rpw_sc_rw1_f1 = 0.0;
169 cp_rpw_sc_rw1_f1 = 0.0;
170 cp_rpw_sc_rw1_f2 = 0.0;
170 cp_rpw_sc_rw1_f2 = 0.0;
171 cp_rpw_sc_rw2_f1 = 0.0;
171 cp_rpw_sc_rw2_f1 = 0.0;
172 cp_rpw_sc_rw2_f2 = 0.0;
172 cp_rpw_sc_rw2_f2 = 0.0;
173 cp_rpw_sc_rw3_f1 = 0.0;
173 cp_rpw_sc_rw3_f1 = 0.0;
174 cp_rpw_sc_rw3_f2 = 0.0;
174 cp_rpw_sc_rw3_f2 = 0.0;
175 cp_rpw_sc_rw4_f1 = 0.0;
175 cp_rpw_sc_rw4_f1 = 0.0;
176 cp_rpw_sc_rw4_f2 = 0.0;
176 cp_rpw_sc_rw4_f2 = 0.0;
177 // initialize filtering parameters
177 // initialize filtering parameters
178 filterPar.spare_sy_lfr_pas_filter_enabled = DEFAULT_SY_LFR_PAS_FILTER_ENABLED;
178 filterPar.spare_sy_lfr_pas_filter_enabled = DEFAULT_SY_LFR_PAS_FILTER_ENABLED;
179 filterPar.sy_lfr_pas_filter_modulus = DEFAULT_SY_LFR_PAS_FILTER_MODULUS;
179 filterPar.sy_lfr_pas_filter_modulus = DEFAULT_SY_LFR_PAS_FILTER_MODULUS;
180 filterPar.sy_lfr_pas_filter_tbad = DEFAULT_SY_LFR_PAS_FILTER_TBAD;
180 filterPar.sy_lfr_pas_filter_tbad = DEFAULT_SY_LFR_PAS_FILTER_TBAD;
181 filterPar.sy_lfr_pas_filter_offset = DEFAULT_SY_LFR_PAS_FILTER_OFFSET;
181 filterPar.sy_lfr_pas_filter_offset = DEFAULT_SY_LFR_PAS_FILTER_OFFSET;
182 filterPar.sy_lfr_pas_filter_shift = DEFAULT_SY_LFR_PAS_FILTER_SHIFT;
182 filterPar.sy_lfr_pas_filter_shift = DEFAULT_SY_LFR_PAS_FILTER_SHIFT;
183 filterPar.sy_lfr_sc_rw_delta_f = DEFAULT_SY_LFR_SC_RW_DELTA_F;
183 filterPar.sy_lfr_sc_rw_delta_f = DEFAULT_SY_LFR_SC_RW_DELTA_F;
184 update_last_valid_transition_date( DEFAULT_LAST_VALID_TRANSITION_DATE );
184 update_last_valid_transition_date( DEFAULT_LAST_VALID_TRANSITION_DATE );
185
185
186 // waveform picker initialization
186 // waveform picker initialization
187 WFP_init_rings();
187 WFP_init_rings();
188 LEON_Clear_interrupt( IRQ_SPARC_GPTIMER_WATCHDOG ); // initialize the waveform rings
188 LEON_Clear_interrupt( IRQ_SPARC_GPTIMER_WATCHDOG ); // initialize the waveform rings
189 WFP_reset_current_ring_nodes();
189 WFP_reset_current_ring_nodes();
190 reset_waveform_picker_regs();
190 reset_waveform_picker_regs();
191
191
192 // spectral matrices initialization
192 // spectral matrices initialization
193 SM_init_rings(); // initialize spectral matrices rings
193 SM_init_rings(); // initialize spectral matrices rings
194 SM_reset_current_ring_nodes();
194 SM_reset_current_ring_nodes();
195 reset_spectral_matrix_regs();
195 reset_spectral_matrix_regs();
196
196
197 // configure calibration
197 // configure calibration
198 configureCalibration( false ); // true means interleaved mode, false is for normal mode
198 configureCalibration( false ); // true means interleaved mode, false is for normal mode
199
199
200 updateLFRCurrentMode( LFR_MODE_STANDBY );
200 updateLFRCurrentMode( LFR_MODE_STANDBY );
201
201
202 BOOT_PRINTF1("in INIT *** lfrCurrentMode is %d\n", lfrCurrentMode)
202 BOOT_PRINTF1("in INIT *** lfrCurrentMode is %d\n", lfrCurrentMode)
203
203
204 create_names(); // create all names
204 create_names(); // create all names
205
205
206 status = create_timecode_timer(); // create the timer used by timecode_irq_handler
206 status = create_timecode_timer(); // create the timer used by timecode_irq_handler
207 if (status != RTEMS_SUCCESSFUL)
207 if (status != RTEMS_SUCCESSFUL)
208 {
208 {
209 PRINTF1("in INIT *** ERR in create_timer_timecode, code %d", status)
209 PRINTF1("in INIT *** ERR in create_timer_timecode, code %d", status)
210 }
210 }
211
211
212 status = create_message_queues(); // create message queues
212 status = create_message_queues(); // create message queues
213 if (status != RTEMS_SUCCESSFUL)
213 if (status != RTEMS_SUCCESSFUL)
214 {
214 {
215 PRINTF1("in INIT *** ERR in create_message_queues, code %d", status)
215 PRINTF1("in INIT *** ERR in create_message_queues, code %d", status)
216 }
216 }
217
217
218 status = create_all_tasks(); // create all tasks
218 status = create_all_tasks(); // create all tasks
219 if (status != RTEMS_SUCCESSFUL)
219 if (status != RTEMS_SUCCESSFUL)
220 {
220 {
221 PRINTF1("in INIT *** ERR in create_all_tasks, code %d\n", status)
221 PRINTF1("in INIT *** ERR in create_all_tasks, code %d\n", status)
222 }
222 }
223
223
224 // **************************
224 // **************************
225 // <SPACEWIRE INITIALIZATION>
225 // <SPACEWIRE INITIALIZATION>
226 status_spw = spacewire_open_link(); // (1) open the link
226 status_spw = spacewire_open_link(); // (1) open the link
227 if ( status_spw != RTEMS_SUCCESSFUL )
227 if ( status_spw != RTEMS_SUCCESSFUL )
228 {
228 {
229 PRINTF1("in INIT *** ERR spacewire_open_link code %d\n", status_spw )
229 PRINTF1("in INIT *** ERR spacewire_open_link code %d\n", status_spw )
230 }
230 }
231
231
232 if ( status_spw == RTEMS_SUCCESSFUL ) // (2) configure the link
232 if ( status_spw == RTEMS_SUCCESSFUL ) // (2) configure the link
233 {
233 {
234 status_spw = spacewire_configure_link( fdSPW );
234 status_spw = spacewire_configure_link( fdSPW );
235 if ( status_spw != RTEMS_SUCCESSFUL )
235 if ( status_spw != RTEMS_SUCCESSFUL )
236 {
236 {
237 PRINTF1("in INIT *** ERR spacewire_configure_link code %d\n", status_spw )
237 PRINTF1("in INIT *** ERR spacewire_configure_link code %d\n", status_spw )
238 }
238 }
239 }
239 }
240
240
241 if ( status_spw == RTEMS_SUCCESSFUL) // (3) start the link
241 if ( status_spw == RTEMS_SUCCESSFUL) // (3) start the link
242 {
242 {
243 status_spw = spacewire_start_link( fdSPW );
243 status_spw = spacewire_start_link( fdSPW );
244 if ( status_spw != RTEMS_SUCCESSFUL )
244 if ( status_spw != RTEMS_SUCCESSFUL )
245 {
245 {
246 PRINTF1("in INIT *** ERR spacewire_start_link code %d\n", status_spw )
246 PRINTF1("in INIT *** ERR spacewire_start_link code %d\n", status_spw )
247 }
247 }
248 }
248 }
249 // </SPACEWIRE INITIALIZATION>
249 // </SPACEWIRE INITIALIZATION>
250 // ***************************
250 // ***************************
251
251
252 status = start_all_tasks(); // start all tasks
252 status = start_all_tasks(); // start all tasks
253 if (status != RTEMS_SUCCESSFUL)
253 if (status != RTEMS_SUCCESSFUL)
254 {
254 {
255 PRINTF1("in INIT *** ERR in start_all_tasks, code %d", status)
255 PRINTF1("in INIT *** ERR in start_all_tasks, code %d", status)
256 }
256 }
257
257
258 // start RECV and SEND *AFTER* SpaceWire Initialization, due to the timeout of the start call during the initialization
258 // start RECV and SEND *AFTER* SpaceWire Initialization, due to the timeout of the start call during the initialization
259 status = start_recv_send_tasks();
259 status = start_recv_send_tasks();
260 if ( status != RTEMS_SUCCESSFUL )
260 if ( status != RTEMS_SUCCESSFUL )
261 {
261 {
262 PRINTF1("in INIT *** ERR start_recv_send_tasks code %d\n", status )
262 PRINTF1("in INIT *** ERR start_recv_send_tasks code %d\n", status )
263 }
263 }
264
264
265 // suspend science tasks, they will be restarted later depending on the mode
265 // suspend science tasks, they will be restarted later depending on the mode
266 status = suspend_science_tasks(); // suspend science tasks (not done in stop_current_mode if current mode = STANDBY)
266 status = suspend_science_tasks(); // suspend science tasks (not done in stop_current_mode if current mode = STANDBY)
267 if (status != RTEMS_SUCCESSFUL)