LPP » INSTRU » VHDLib

# Mini LFR - Bitstream Generation

# Bitstream Generation Procedure #

------------------------------

## 1 Generates scripts files ##

Clean the project directory, and run the makefile scripts command to generate all project's files.

```bash

# clean the project and re-generates the scripts

$> make distclean scripts

```

The files MINI\_LFR\_top\_libero.prj should be created.

## 2 Launch Libero IDE ##

Open the project MINI\_LFR\_top\_libero.prj with Libero IDE v9.1.

!["Libero IDE v9.1"](Capture1.PNG)

### 2.1 Synthesis ###

Synthesis tools should be configured to use **Synplify** version **2012-03A-SP1-2**.

Launch the synthesis step (You must not add constraint file).

In the synplify Pro windows, click on the Run button.

The project status obtained should be :

!["Synplify Project Status"](Capture2.PNG)

> You must verfify the block RAM's usage. The expected value is 100.

>

> If it's around 60/70, LEON3 processor is not mapped. In this case, you must clean your project and restart the generation procedure.

You can close Synplify and return to Libero.

If the Sythesis step is green like that :

You must activate the option `Detect new files on disk automatically` in the project settings.

![](Capture3.PNG)

![](Capture4.PNG)

### 2.2 Place&Route ###

Launch the Place&Route step. You must add the constraint files :

  * `default.pdc` (Input/Output constraint)

  * `MINI-LFR_PlaceAndRoute.sdc` (Timing constraint)

![](Capture5.PNG)

#### 2.2.1 Compile Step ####

![](Capture6.PNG)

Run the Compile step.

#### 2.2.2 Layout Step ####

![](Capture7.PNG)

Run the Layout step.

In the Layout options windows, select Advanced Layout Options :

![](Capture8.PNG)

And checked those options :

![](Capture9.PNG)

Click Ok and wait...

![](Capture10.PNG)

#### 2.2.3 Timing Analyser ####

Launch theTiming Analyser.

![](Capture11.PNG)

#### 2.2.3.a SpaceWire Output ####

You must verify the SpaceWire output timing for the Max and Min delay.

![](Capture12.PNG)

![](Capture19.PNG)

The ouput skew is equal to Ouput\_SOut timing - Ouput\_DOut timing. This output skew must be positive.

> In this exemple,

>

> SPW\_NOM skew max = 13.907 - 15.882 = -1.975 ns

>

> SPW\_NOM skew min = 6.367 - 7.317 = -0.950 ns

>

> SPW\_RED skew max = 17.937 - 13.510 =  4.427 ns

>

> SPW\_RED skew min = 8.304 - 6.175 =  2.129 ns

>

> The SPW\_NOM interface must be modified. In ChipPlanner, we will move element in the SPW\_NOM path to have a positive skew in min and max delay.

> ![](Capture13.PNG)

> ![](Capture14.PNG)

#### 2.2.3.b SpaceWire Input ####

You must also verify the SpaceWire input timing. For that, you must add a new set for SPW_INPUT:

![](Capture15.PNG)

and configure it like that :

 you

![](Capture16.PNG)

You obtain those timing for min and max delay.

![](Capture17.PNG)

![](Capture18.PNG)

You must also add a new set for the FF setup time :

![](Capture20.PNG)

![](Capture21.PNG)

In resume, for the input SPW_NOM interface :

<table border=1 width=40% align=center>

    	<thead>

    		<tr>

			<th colspan=2> Signal Type </th>		<th> max delay</th>	<th>min delay</th>

    		</tr>

    	</thead>

    	<thead>

    		<tr>

			<th colspan=4 align="center"> SPW_NOM_IN </th>

    		</tr>

    	</thead>

    	<tbody>

        	<tr>	<td rowspan=4>r_FF</td> 	<td>Strobe to CLK</td>	<td>7.230 ns</td>	<td>3.497 ns</td>	</tr>

		<tr>					<td>Data   to CLK</td>	<td>8.046 ns</td>	<td>3.807 ns</td>	</tr>

		<tr>					<td>Data   to D  </td>	<td>1.700 ns</td>	<td>0.692 ns</td>	</tr>

		<tr>					<td>D to Q  </td>	<td>0.888 ns</td>	<td>0.413 ns</td>	</tr>

		<tr>	<td rowspan=4>nr_FF</td> 	<td>Strobe  to CLK</td>	<td>7.315 ns</td>	<td>3.543 ns</td>	</tr>

		<tr>					<td>Data    to CLK</td>	<td>8.131 ns</td>	<td>3.853 ns</td>	</tr>

		<tr>					<td>Data    to D  </td>	<td>1.767 ns</td>	<td>0.724 ns</td>	</tr>

		<tr>					<td>D to Q  </td>	<td>0.888 ns</td>	<td>0.413 ns</td>	</tr>

    	</tbody>

</table>

The input skew is equal to Ouput\_SOut timing - Ouput\_DOut timing. This output skew must be positive.