Clean the project directory, and run the makefile scripts command to generate all project's files.
# clean the project and re-generates the scripts
$> make distclean scripts
The files MINI_LFR_top_libero.prj should be created.
Open the project MINI_LFR_top_libero.prj with Libero IDE v9.1.
Synthesis tools should be configured to use Synplify version 2012-03A-SP1-2.
Launch the synthesis step (You must not add constraint file).
In the synplify Pro windows, click on the Run button.
The project status obtained should be :
You must verfify the block RAM's usage. The expected value is 100.
If it's around 60/70, LEON3 processor is not mapped. In this case, you must clean your project and restart the generation procedure.
You can close Synplify and return to Libero.
If the Sythesis step is green like that :
You must activate the option Detect new files on disk automatically
in the project settings.
Launch the Place&Route step. You must add the constraint files :
default.pdc
(Input/Output constraint) MINI-LFR_PlaceAndRoute.sdc
(Timing constraint)Run the Compile step.
Run the Layout step.
In the Layout options windows, select Advanced Layout Options :
And checked those options :
Click Ok and wait...
Launch theTiming Analyser.
You must verify the SpaceWire output timing for the Max and Min delay.
The ouput skew is equal to Ouput_SOut timing - Ouput_DOut timing. This output skew must be positive.
In this exemple,
SPW_NOM skew max = 13.907 - 15.882 = -1.975 ns
SPW_NOM skew min = 6.367 - 7.317 = -0.950 ns
SPW_RED skew max = 17.937 - 13.510 = 4.427 ns
SPW_RED skew min = 8.304 - 6.175 = 2.129 ns
The SPW_NOM interface must be modified. In ChipPlanner, we will move element in the SPW_NOM path to have a positive skew in min and max delay.
You must also verify the SpaceWire input timing. For that, you must add a new set for SPW_INPUT:
and configure it like that :
you
You obtain those timing for min and max delay.
You must also add a new set for the FF setup time :
In resume, for the input SPW_NOM interface :
header 1
header 2
header 3
line 1
1
value
row 2
2
value
line 3
3
value
The input skew is equal to Ouput_SOut timing - Ouput_DOut timing. This output skew must be positive.