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Mini LFR - Bitstream Generation » History » Version 1

Jean-Christophe Pellion, 01/12/2016 02:00 PM

1 1 Jean-Christophe Pellion
# Mini LFR - Bitstream Generation
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## 1 Generates scripts files ##
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Clean the project directory, and run the makefile scripts command to generate all project's files.
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```bash
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# clean the project and re-generates the scripts
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$> make distclean scripts
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```
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The files MINI\_LFR\_top\_libero.prj should be created.
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## 2 Launch Libero IDE ##
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Open the project MINI\_LFR\_top\_libero.prj with Libero IDE v9.1.
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![Capture1.PNG]( "Libero IDE v9.1")
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### 2.1 Synthesis ###
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Synthesis tools should be configured to use **Synplify** version **2012-03A-SP1-2**.
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Launch the synthesis step (You must not add constraint file). 
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In the synplify Pro windows, click on the Run button.
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The project status obtained should be :
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![image](./README_dir/Capture2.PNG "Synplify Project Status")
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> You must verfify the block RAM's usage. The expected value is 100.
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> 
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> If it's around 60/70, LEON3 processor is not mapped. In this case, you must clean your project and restart the generation procedure.
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You can close Synplify and return to Libero.
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If the Sythesis step is green like that :
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You must activate the option `Detect new files on disk automatically` in the project settings.
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![image](./README_dir/Capture3.PNG "Project > Settings...")
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![image](./README_dir/Capture4.PNG "Detect new files on disk automatically")
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### 2.2 Place&Route ###
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Launch the Place&Route step. You must add the constraint files :
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  * `default.pdc` (Input/Output constraint) 
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  * `MINI-LFR_PlaceAndRoute.sdc` (Timing constraint)
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![image](./README_dir/Capture5.PNG "Constraints")
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#### 2.2.1 Compile Step ####
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![image](./README_dir/Capture6.PNG "Compile Step")
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Run the Compile step. 
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#### 2.2.2 Layout Step ####
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![image](./README_dir/Capture7.PNG "An exemplary image")
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Run the Layout step.
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In the Layout options windows, select Advanced Layout Options :
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![image](./README_dir/Capture8.PNG "An exemplary image")
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And checked those options : 
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![image](./README_dir/Capture9.PNG "An exemplary image")
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Click Ok and wait...
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![image](./README_dir/Capture10.PNG "An exemplary image")
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#### 2.2.3 Timing Analyser ####
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Launch theTiming Analyser.
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![image](./README_dir/Capture11.PNG "An exemplary image")
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#### 2.2.3.a SpaceWire Output ####
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You must verify the SpaceWire output timing for the Max and Min delay.
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![image](./README_dir/Capture12.PNG "An exemplary image")
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![image](./README_dir/Capture19.PNG "An exemplary image")
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The ouput skew is equal to Ouput\_SOut timing - Ouput\_DOut timing. This output skew must be positive.
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> In this exemple,
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> SPW\_NOM skew max = 13.907 - 15.882 = -1.975 ns
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> SPW\_NOM skew min = 6.367 - 7.317 = -0.950 ns
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> SPW\_RED skew max = 17.937 - 13.510 =  4.427 ns
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> SPW\_RED skew min = 8.304 - 6.175 =  2.129 ns
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> The SPW\_NOM interface must be modified. In ChipPlanner, we will move element in the SPW\_NOM path to have a positive skew in min and max delay.
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> ![image](./README_dir/Capture13.PNG "An exemplary image")
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> ![image](./README_dir/Capture14.PNG "An exemplary image")
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#### 2.2.3.b SpaceWire Input ####
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You must also verify the SpaceWire input timing. For that, you must add a new set for SPW_INPUT:
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![image](./README_dir/Capture15.PNG "An exemplary image")
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and configure it like that :
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![image](./README_dir/Capture16.PNG "An exemplary image")
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You obtain those timing for min and max delay.
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![image](./README_dir/Capture17.PNG "An exemplary image")
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![image](./README_dir/Capture18.PNG "An exemplary image")
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You must also add a new set for the FF setup time :
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![image](./README_dir/Capture20.PNG "An exemplary image")
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![image](./README_dir/Capture21.PNG "An exemplary image")
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In resume, for the input SPW_NOM interface :
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<table>
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    <thead>
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        <tr>
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            <th>header 1</th>
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            <th align="center">header 2</th>
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            <th align="right">header 3</th>
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        </tr>
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    </thead>
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    <tbody>
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        <tr>
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            <td>line 1</td>
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            <td align="center">1</td>
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            <td align="right">value</td>
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        </tr>
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        <tr>
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            <td>row 2</td>
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            <td align="center">2</td>
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            <td align="right">value</td>
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        </tr>
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        <tr>
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            <td>line 3</td>
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            <td align="center">3</td>
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            <td align="right">value</td>
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        </tr>
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    </tbody>
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</table>
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The input skew is equal to Ouput\_SOut timing - Ouput\_DOut timing. This output skew must be positive.