IP documentation » History » Revision 8
Revision 7 (Jean-Christophe Pellion, 27/02/2014 01:40 PM) → Revision 8/38 (Jean-Christophe Pellion, 27/02/2014 04:00 PM)
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h1. IP documentation
h2. General Purpose
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h3. Synchronizer
{{collapse(SyncFF)
Sync_FF permit to synchronize a signal A in the clock domain clk. Normally, the A signal must be the output of a FF cloked in an other domain. You shouldtn't have "logic" between the 2 domain.
You can configure the FF number (default 2). This number is depending of the MTBF(Mean Time Between Failure).
p=. !{width: 25%}SYNC_FF.png! <pre><code class="vhdl"> class="C++">
COMPONENT SYNC_FF_LPP_JCP
GENERIC (
NB_FF_OF_SYNC : INTEGER);
INTEGER := 2);
PORT (
clk : IN STD_LOGIC;
rstn : IN STD_LOGIC;
A : IN STD_LOGIC;
A_sync : OUT STD_LOGIC);
END COMPONENT;
</code></pre>
|_.Parameter |_.Type |_.Size |_.Description |_.Default |
h1. IP documentation
h2. General Purpose
----
h3. Synchronizer
{{collapse(SyncFF)
|NB_FF_OF_SYNC |Integer | |Number of FF |2 |
|\5.|
!{width: 20%}SYNC_FF.png!
|_.Signal |_.Direction |_.Type |_.Size |_.Function |_. Active |
|clk |input |1 |clock |rising edge |
|rstn |input |1 |reset |low |
|A |input |1 |data in | |
|A_sync |ouput |1 |data out synchronized | |
}}
{{include(https://hephaistos.lpp.polytechnique.fr/rhodecode/HG_REPOSITORIES/LPP/INSTRUMENTATION/VHD_Lib/files/bf3115c7b73fabc361d1693b36a643a1f87c8897/lib/staging/LPP/JCP/general_purpose/Synchronizer/SYNC_FF.vhd)}}