IP documentation » History » Version 8
Jean-Christophe Pellion, 27/02/2014 04:00 PM
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8 | ---- |
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10 | 1 | Jean-Christophe Pellion | h1. IP documentation |
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12 | h2. General Purpose |
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14 | ---- |
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16 | h3. Synchronizer |
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18 | 8 | Jean-Christophe Pellion | |
19 | 1 | Jean-Christophe Pellion | {{collapse(SyncFF) |
20 | 8 | Jean-Christophe Pellion | Sync_FF permit to synchronize a signal A in the clock domain clk. Normally, the A signal must be the output of a FF cloked in an other domain. You shouldtn't have "logic" between the 2 domain. |
21 | You can configure the FF number (default 2). This number is depending of the MTBF(Mean Time Between Failure). |
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23 | p=. !{width: 25%}SYNC_FF.png! <pre><code class="vhdl"> |
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24 | COMPONENT SYNC_FF_LPP_JCP |
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25 | GENERIC ( |
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26 | NB_FF_OF_SYNC : INTEGER); |
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27 | PORT ( |
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28 | clk : IN STD_LOGIC; |
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29 | rstn : IN STD_LOGIC; |
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30 | A : IN STD_LOGIC; |
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31 | A_sync : OUT STD_LOGIC); |
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32 | END COMPONENT; |
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33 | </code></pre> |
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36 | |_.Parameter |_.Type |_.Size |_.Description |_.Default | |
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37 | |NB_FF_OF_SYNC |Integer | |Number of FF |2 | |
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38 | |\5.| |
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39 | |_.Signal |_.Direction |_.Size |_.Function |_. Active | |
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40 | 7 | Jean-Christophe Pellion | |clk |input |1 |clock |rising edge | |
41 | |rstn |input |1 |reset |low | |
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42 | 6 | Jean-Christophe Pellion | |A |input |1 |data in | | |
43 | 3 | Jean-Christophe Pellion | |A_sync |ouput |1 |data out synchronized | | |
44 | 2 | Jean-Christophe Pellion | |
45 | }} |